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| Semiconductor MSM9844 VOICE SYNTHESIS LSI with on-chip FIFO Memory * General Description Version1.20, Jun.16, 1999 MSM9844 is a Voice Synthesizer LSI with on-chip FIFO memory. A newly developed synthesis algorithm, OKI ADPCM2, promises superb sound quality. The LSI is fully controllable from an external CPU via 16/8-bit bus interface. MSM9844 is an ideal choice for application systems where such non-microchip data storage as CD ROM is used.. * Features * 16/8-bit Bus Interface * On-chip FIFO Memory Capacity : 1024 Bits 23 ms Buffering When Sampling Frequency at 8.0 kHz, 4-bit ADPCM and Monaural Playback selected * Synthesis Algorithms for User's Selection 4,5,6,7,8-bit OKI ADPCM2 4-bit OKI ADPCM 8/16-bit Straight PCM 8-bit OKI Non-Linear PCM * Oscillation Clock Frequency: 16.9344 MHz / 24.576 MHz * Sampling Frequency: 11.025 kHz, 22.05 kHz, 44.1 kHz at f OSC=16.9344 MHz OSC=24.576 MHz 4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz, 48.0 kHz at f * Sound Level Control (8 levels, 0dB ~ -21dB) * Built-in 14-bit D/A Converter * 3 types of Serial Interface for External DAC * Sampling Rate Conversion Function * Packaging: 56-pin Plastic QFP (QFP56-P-910-0.65-2K) Product Code: MSM9844GA Page1 Semiconductor MSM9844 * Pin Layout (Top View) 56-pin Plastic QFP IOW DREQL DACKL DGND TEST1 TEST0 VCK TEST2 48 47 46 45 56 55 54 52 51 53 50 49 44 43 SIOCK DASD NC XT XT NC D0 D1 D2 D3 DVDD D4 D5 D6 D7 NC D8 D9 D10 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 18 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 BUSY D/C CS RD WR FUL / DREQR MID EMP CH / DACKR RESET CBUSY DVDD AVDD AOUTR D12 D13 D14 D15 NC NC DGND AGND NC NC NC TEST3 NC AOUTL Page2 Semiconductor MSM9844 * Block Diagram AOUTR AOUTL EMP MID FUL/DREQR CH/DACKR FIFO LPF DAC DAC LPF AVDD AGND DVDD DGND Volume Controller VCK Serial Port ADPCM2 / ADPCM / PCM Synthesizer MCU I/F TEST0 TEST1 DMA I / F Timing Controller SIOCK DASD D15 to D0 WR RD CS D/C BUSY CBUSY RESET DREQL DACKL IOW XT XT Page3 Semiconductor MSM9844 * Pin Description Pin No. 11 - 14 16 - 19 Symbol D15 to D8 I/O Description When 8-bit bus interface selected, you can define, by using a command, these pins as input/output to/from external memory. When no definition I / O made, these pins are output mode. When 16-bit bus interface selected, they are one half of bi-directional data bus for data input / output from/to external micro-controller and memory. Another half of bi-directional data bus for data input/output from/to external I / O micro-controller and memory and for status output. I WRITE pulse input pin. Input "L" pulse before you can enter command and data to D15 to D0 pins. READ pulse input pin. Input "L" pulse before the LSI can output status and data to D15 to D0 pins. With this pin at "L" level, the LSI accepts WRITE or READ pulse input. At "H" level the LSI would not accept WRITE or READ pulse. While this pin being held "H", D15 to D0 pins are enabled to input/output sound data. While this pin being held "L", D7 to D0 pins are enabled to input a command or output status data. Output "L" level during playback/PAUSE operation. Output "L" level when the LSI is ready to accept a command. "H" level output from this pin indicates FIFO memory is empty. You can change this pin to "L" active by a command input. "H" level output from this pin indicates FIFO memory is more than half. During playback, voice synthesis starts when MID changes to "H" level. You can change this pin to "L" active by a command input. This pin outputs a synchro signal for voice data input / output when non-use of FIFO is selected. "H" level output from this pin indicates FIFO memory is full. During playback operation this pin is held "H" and FIFO memory is write -disabled. You can change this pin to "L" active by a command input. When DMA Transfer and stereo-playback selected by the command input, the output from this pin becomes DMA Transfer request signal. The pin outputs "H" when the right channel FIFO memory is empty. You can change this pin to "L" active by a command input. When stereo-playback selected, write sound data to the right channel FIFO at "H" level, while data to the left channel FIFO at "L" level. When monaural playback selected, keep this pin "L". You can change this pin to "L" active by a command input. When DMA Transfer and stereo-playback selected by the command input, this pin acknowledges the right channel DMA Transfer permission signal. With this pin at "L" level the LSI enabled the /IOW pin to accept the signal. You can change this pin to "H" active by a command input. Output "H" level to represent DMA Transfer request signal when FIFO gets empty. If stereo-playback selected, the pin outputs "H" level to represent DMA Transfer request signal when the left channel FIFO gets empty. DMA Transfer Permission Acknowledgement signal. With this pin at "L" level the LSI enables the /IOW pin to accept the signal. When stereoplayback selected, the pin acknowledges DMA Transfer permission signal for the left channel FIFO. You can change this pin to "H" active by a command input. When DMA Transfer is not in use, keep the pin "H". 1-4 6-9 38 D7 to D0 WR 39 RD I 40 41 CS D/C I I 42 32 35 BUSY CBUSY EMP O O O 36 MID O 37 FUL / DREQR O 34 CH / DACKR I 51 DREQL O 50 DACKL I Page4 Semiconductor MSM9844 Pin No. 52 Symbol IOW I/O I Description When DMA Transfer selected, the signal to start writing external memory data to the MSM9844 is entered to this pin. When DMA Transfer is not use, keep the pin "H". 16-bit serial data output pin when the external DAC is in use. Synchronizing clock signal for 16-bit serial data input/output when the external DAC is in use. Pins wired to the oscillator, When the external clock is used, input the clock signal to the XT pin and keep the /XT pin open. Input/Output the sampling frequency in use. The signal is used as the synchronizing signal when the external DAC is in use. "L" level input to this pin turns the LSI to the initial status. Pins for testing the LSI. Keep these pins "L". 44 43 DASD SIOCK O I/O I O I/O I I 54 55 46 XT XT VCK 33 47,48 45,26 28 29 RESET TEST0,1 TEST2,3 AOUTL AOUTR O The left channel output from the built-in LPF. Analog waveform output can be directly connected to an amplifirer to drive a speaker. The right channel output from the built-in LPF. Analog waveform output can be directly connected to an amplifirer to drive a speaker. Digital power supply pin. Insert a 0.1F or larger bypass capacitor between this pin and the DGND pin. Digital GND pin. Analog power supply pin. Insert a 0.1F or larger bypass capacitor between this pin and the AGND pin. Analog GND pin. O 31 21,49 30 DVDD DGND AVDD 22 AGND Page5 Semiconductor MSM9844 * Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TSTG Ta = 25C Conditions Rating - 0.3 to + 7.0 (GND = 0 V) Unit V V C - 0.3 to VDD + 0.3 - 55 to + 150 * Recommended Operating Ranges Parameter Power Supply Voltage Operating Temperature Master Clock Frequency Symbol VDD TOP fOSC Conditions DGND = AGND = 0V Rating + 4.5 to + 5.5 - 40 to + 85 24.576 (GND = 0 V) Unit V C MHz * DC Characteristics Parameter "H" Input Voltage "L" Input Voltage "H" Output Voltage note 1 "L" Output Voltage note 1 "H" Output Voltage note 2 "L" Output Voltage note 2 "H" Input Current "H" Input Current "L" Input Current "L" Input Current "L" Input Current note 3 note 4 note 5 note 4 note 6 Symbol VIH VIL VOH1 VOL1 VOH2 VOL2 IIH1 IIH2 IIL1 IIL2 IIL3 IDD IDDS DVDD = AVDD = + 4.5 V to + 5.5 V DGND = AGND = 0 VTa = - 40 to + 85 C Conditions Min. VDD x 0.85 VDD x 0.15 Typ. Max. Unit V V V IOH = - 40 A IOL = 2 mA IOH = - 40 A IOL = 2 mA VIH = VDD VIH = VDD VIL = GND VIL = GND VIL = GND fOSC = 24.576 MHz without load At power down without load Ta = - 40 to + 70 C At power down without load Ta = - 40 to + 85 C VDD - 0.3 0.45 VDD - 0.3 V V 0.8 10 20 - 10 - 20 - 400 - 20 40 V A A A A A mA Operating Current Consumption Standby Current Consumption 10 2 mA A 50 2 mA A note 1) Applies to output pins excluding XT pin. note 2) Applies to XT pin. note 3) Applies to input pins excluding XT pin. note 4) Applies to XT pins . note 5) Applies to input pins without pull-up-register excluding XT pin. note 6) Applies to input pins within pull-up-register excluding XT pin. Page6 Semiconductor MSM9844 * AC Characteristics Parameter RESET Pulse Width Setup Time after Rise of Power Supply for Fall of RESET Time to Active First RD, WR after Fall of RESET RD Pulse Width CS, D/C, CH Setup and Hold Time for RD Time from Fall of RD till Data and Status Definition Time from Fall of RD till Data Float Time from Rise of RD till Fall of Next RD WR Pulse Width CS, D/C, CH Setup and Hold Time for WR Setup Time of Data, and Command for Rise of WR Hold Time of Data, and Command for Rise of WR Time from Rise of WR till Fall of Next WR IOW Pulse Width Setup and Hold Time of DACK for IOW Setup Time of Data for Rise of IOW Hold Time of Data for Rise of IOW Time from Rise of IOW till Fall of Next IOW DVDD = AVDD = + 4.5 V to + 5.5 V DGND = AGND = 0 VTa = - 40 to + 85 C Symbol tRSTW tRSTD tRSTS tRR tCR tDRE tDRF tCRC tWW tCW tDWS tDWH tCWC tIOWW tDW tIOWS tIOWH tIOWC 500 160 30 100 10 500 160 10 100 10 200 10 Min. 300 500 200 160 30 120 50 Typ. Max. Unit ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * Analog Characteristics Parameter D/A Output Relative Error AOUT Output Load Resistance Symbol VDAE RAOUT DVDD = AVDD = + 4.5 V to + 5.5 V DGND = AGND = 0 VTa = - 40 to + 85 C Conditions No Load 50 Min. Typ. Max. 10 Unit mV k Page7 Semiconductor MSM9844 * Timing Chart RESET Timing VDD tRSTD tRSTW RESET (I) tRSTS RD or WR (I) READ Timing Status READ CS (I) D / C (I) tCR tCR RD (I) tRR tDRE tDRF D7 to D0 (I/O) Don't Care Page8 Semiconductor MSM9844 WRITE Timing (1) DATA WRITE CH (I) CS (I) D / C (I) tCW tCW WR (I) tWW tDWS tDWH D7 to D0 (I/O) Don't Care (2) COMMAND WRITE CS (I) D / C (I) tCW tCW WR (I) tWW tDWS tDWH D7 to D0 (I/O) Don't Care (3) WRITE CYCLE WR (I) tCWC Page9 Semiconductor MSM9844 DMA Timing IOW Timing (for Playback and Write 2 bytes DATA) DACKL (I) or DACLR (I) tDW tIOWC tDW IOW (I) tIOWW tIOWS D7 to D0 (I/O) tIOWH Page10 Semiconductor MSM9844 Playback Timing with using External MCU and Memory RESET (I) MCU I/F BUSY (O) EMP (O) MID (O) FUL (O) 1/2 VDD PLAY 1 Command Write Cycle 2 3 4 5 Data Write Cycle AOUT (O) Output the last data or Input STOP Command End of Playback Playback Timing with using DMA Controller RESET (I) MCU I/F BUSY (O) DREQ (O) DACK (I) IOW (I) EMP (O) MID (O) FUL internal 1/2 VDD PLAY 1 Command Write Cycle 2 3 4 5 Data Write Cycle No use CS,WR, and RD pins AOUT (O) Output the last data or Input STOP Command End of Playback Page11 Semiconductor MSM9844 * Functional Description * Voice Synthesis Algorithms To meet user's varying sound quality requirements, 4 different types of voice synthesis algorithms are available for user's selection as follows: 1. OKI 4-bit ADPCM 2. OKI 4/5/6/7/8-bit ADPCM2 3. 8/16-bit Straight PCM 4. 8-bit Non-linear PCM * Data Formats When 8-bit Bus Selected 1. Oki 4-bit ADPCM, Oki 4-bit ADPCM2 D7 MSB1 MSB3 D6 3SB1 3SB3 D5 2SB1 2SB3 D4 LSB1 LSB3 D3 MSB2 MSB4 D2 3SB2 3SB4 D1 2SB2 2SB4 D0 LSB2 LSB4 2. Oki 5-bit ADPCM2 D7 X X D6 X X D5 X X D4 MSB1 MSB2 D3 4SB1 4SB2 D2 3SB1 3SB2 D1 2SB1 2SB2 D0 LSB1 LSB2 3. Oki 6-bit ADPCM2 D7 X X D6 X X D5 MSB1 MSB2 D4 5SB1 5SB2 D3 4SB1 4SB2 D2 3SB1 3SB2 D1 2SB1 2SB2 D0 LSB1 LSB2 4. Oki 7-bit ADPCM2 D7 X X D6 MSB1 MSB2 D5 6SB1 6SB2 D4 5SB1 5SB2 D3 4SB1 4SB2 D2 3SB1 3SB2 D1 2SB1 2SB2 D0 LSB1 LSB2 5. Oki 8-bit ADPCM2, 8-bit Linear PCM, and 8-bit Oki Non-Linear PCM D7 MSB1 MSB2 D6 7SB1 7SB2 D5 6SB1 6SB2 D4 5SB1 5SB2 D3 4SB1 4SB2 D2 3SB1 3SB2 D1 2SB1 2SB2 D0 LSB1 LSB2 6. 16-bit Linear PCM D7 MSB1 8SB1 D6 15SB1 7SB1 D5 14SB1 6SB1 D4 13SB1 5SB1 D3 12SB1 4SB1 D2 11SB1 3SB1 D1 10SB1 2SB1 D0 9SB1 LSB1 Page12 Semiconductor MSM9844 * Data Formats When 16-bit Bus Selected 1. Oki 4-bit ADPCM, Oki 4-bit ADPCM2 D15 MSB1 D7 MSB3 D14 3SB1 D6 3SB3 D13 2SB1 D5 2SB3 D12 LSB1 D4 LSB3 D11 MSB2 D3 MSB4 D10 3SB2 D2 3SB4 D9 2SB2 D1 2SB4 D8 LSB2 D0 LSB4 2. Oki 5-bit ADPCM2 D15 X D7 X D14 X D6 X D13 X D5 X D12 MSB1 D4 MSB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2 3. Oki 6-bit ADPCM2 D15 X D7 X D14 X D6 X D13 MSB1 D5 MSB2 D12 5SB1 D4 5SB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2 4. Oki 7-bit ADPCM2 D15 X D7 X D14 MSB1 D6 MSB2 D13 6SB1 D5 6SB2 D12 5SB1 D4 5SB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2 5. Oki 8-bit ADPCM2, 8-bit Linear PCM, and 8-bit Oki Non-Linear PCM D15 MSB1 D7 MSB2 D14 7SB1 D6 7SB2 D13 6SB1 D5 6SB2 D12 5SB1 D4 5SB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2 6. 16-bit Linear PCM D15 MSB1 D7 8SB1 D14 15SB1 D6 7SB1 D13 14SB1 D5 6SB1 D12 13SB1 D4 5SB1 D11 12SB1 D3 4SB1 D10 11SB1 D2 3SB1 D9 10SB1 D1 2SB1 D8 9SB1 D0 LSB1 Page13 Semiconductor * Playback Operation When Micro-controller Interface in Use MSM9844 (1) Define a synthesis algorithm, sampling frequency, bus width, playback mode, and etc. as required, by using an appropriate command. (2) To start playback, input the PLAY command. Or, write one word data to FIFO, letting the LSI ready for playback, and turn the EMP pin to "L" to initiate playback. (3) Status shifting indicated by the EMP and FUL pins (EMP="L", MID="L", FUL="L") Indicates the state where no one-word data is written to FIFO memory. (EMP="H", MID="L", FUL="L") Indicates the state where one-word or more data is written to FIFO memory. (EMP="L", MID="H", FUL="L") Indicates the state where data is written to more than half of FIFO memory. (EMP="L", MID="H", FUL="H") Indicates the state where FIFO memory is full. (4) Ending playback When a write cycle is not completed within pre-fixed time, the LSI deems it as a completed write cycle and ends playback. * FIFO Memory's Status Shift : Empty Block : Write Done Block : Block Being Read EMP=H MID =L FUL =L EMP=L MID =L FUL =L EMP=L MID =H FUL =L EMP=L MID =H FUL =H EMP=L MID =L FUL =L EMP=L MID =L FUL =L EMP=H MID =L FUL =L Start Playback Playing Back End Playback Page14 Semiconductor MSM9844 *Playback Operation When DMA Interface in Use MSM9844 issues a DMA Transfer request to the DMA Controller, and starts data transfer in sync with transfer cycles of the DMA Controller after acknowledging a DMA Transfer permission. Enable/Disable of DMA Transfer function can be defined by using the command. The DREQL pin rises to "H" at the Start Playback command, requesting a write cycle to FIFO memory, and maintains "H" level until FIFO gets full. At the point of time when one-word data is written to FIFO, playback starts. When FIFO becomes half, the DREQL returns to "H". *Pausing Playback You can suspend on-going playback by using the Pause command. At this time, you may suspend Write operation to FIFO memory while in pause. Write is resumed from where having been paused, when playback restarts. Or, you may continue Write operation to FIFO memory according to the EMP, MID and FUL pins' status. *Stopping On-going Playback You can stop on-going playback by using the STOP command. When this happens, FIFO memory is cleared to return to the initial status. Page15 Semiconductor *Serial Port Data Format You can select one of the following three types of serial interface by using the command. 1. MSB First (Master/Slave) 2. LSB First (Master/Slave) 3. IIS Format (Master/Slave) MSM9844 (1) MSB 16 bit (J1 = 0, J0 = 0) VCK SIOCK DASD 1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516 MSB LEFT LSB MSB RIGHT LSB (2) LSB 16 bit (J1 = 0, J0 = 1) VCK SIOCK DASD 1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516 LSB LEFT MSB LSB RIGHT MSB (3) MSB, VCK Inverted, and DASD Shifted 1 bit16 bit (J1 = 1, J0 = 1) VCK SIOCK DASD 1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516 MSB LEFT LSB MSB RIGHT LSB Page16 Semiconductor MSM9844 * Sampling RATE Conversion You can convert a sampling frequency for data output to another sampling frequency. You can select an input sampling frequency with Sampling Rate Conversion Command and select SRC available. The SRC function supports only to convert monaural 44.1 kHz sampling. Select 26H data with PLAY Command. 4.0, 6.4, 8.0, 12.8, 16.0kHz sampling frequencies are available to convert. Master oscillation frequency is at 16.9344 MHz. Page17 Semiconductor MSM9844 * Command Code Format D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D3 X L3 H3 C3 C3 H3 W3 P3 R3 A3 X F3 G2 I3 X T3 D2 X L2 S2 C2 C2 V2 W2 P2 R2 A2 X D2 G1 X X T2 D1 X L1 S1 X C1 V1 X P1 R1 E1 B1 D1 G0 J1 X T1 D0 X L0 S0 X C0 V0 X P0 R0 E0 B0 D0 X J0 X T0 NOP Function Sampling RATE Conversion PLAY STOP PAUSE VOLUME POWER DOWN SELECT ALGORITHM ANALOG SETUP 1 ANALOG SETUP 2, BUS WIDTH DEFINE FIFO SIZE SIGNAL OUTPUT FORMAT SELECT DMA TRANSFER SELECT Serial Port FORMAT NOP TEST X = Don't Care Page18 Semiconductor MSM9844 1) NOP Command D7 0 1 D6 0 1 D5 0 1 D4 0 0 D3 X X D2 X X D1 X X D0 X X NOP NOP Function No particular function 2) Sampling RATE Conversion Command D7 0 D6 0 D5 0 D4 1 D3 L3 D2 L2 D1 L1 D0 L0 Function Sampling RATE Conversion By using this command you can select enable / disable Sampling Rate Conversion and input sampling frequency when enable this function. Note that this command is enable with monaural playback. L3 0 1 Function NOT used Sampling Rate Conversion * Used Sampling Rate Conversion * Default L2 0 0 0 0 1 1 1 1 L1 0 0 1 1 0 0 1 1 L0 0 1 0 1 0 1 0 1 Sampling Frequency 16.0 kHz 4.0 kHz 8.0 kHz 6.4 kHz 12.8 kHz Page19 Semiconductor MSM9844 3) PLAY Command D7 0 D6 0 D5 1 D4 0 D3 C3 D2 S2 D1 S1 D0 S0 PLAY Function To start playback, use this command. You can select either the left or right channel playback with C3, as well as sampling frequency with S2 ~ S0. When stereo-playback is selected, data at C3 is disregarded. You can select only one sampling frequency. When the rate converter is used, the frequency defined by S2 ~ S0 is output sampling frequency. C3 0 1 Function PLAY LEFT * PLAY RIGHT * Default S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Sampling Frequency XT = 16.9344MHz XT = 24.576MHz 11.025 kHz * 22.05 kHz 2.76 kHz 5.51 kHz 4.41 kHz 8.82 kHz 44.1 kHz 16.0 kHz * 32.0 kHz 4.0 kHz 8.0 kHz 6.4 kHz 12.8kHz 48.0 kHz * Default Page20 Semiconductor MSM9844 4) STOP Command D7 0 D6 0 D5 1 D4 1 D3 C3 D2 C2 D1 X D0 X STOP Function Use this command to stop playback. After the command input, FIFO data is cleared. C3 allows you to select the left channel or the right channel playback to be stopped. When you want to stop playback on both channels, use C2. C3 0 1 X C2 0 0 1 Function STOP LEFT * STOP RIGHT STOP LEFT and RIGHT * Default 5) PAUSE Command D7 0 D6 1 D5 0 D4 0 D3 C3 D2 C2 D1 C1 D0 X PAUSE Function Use this command to temporarily suspend on-going playback. C1 enables you to control PAUSE/reset. You can select either the left channel or right channel with C3. When you want to suspend playback on both channels, use C2. C3 0 1 X C2 0 0 1 Function PAUSE LEFT * PAUSE RIGHT PAUSE LEFT and RIGHT * Default C1 0 1 PAUSE RESUME Function Page21 Semiconductor MSM9844 6) VOLUME Command D7 0 D6 1 D5 0 D4 1 D3 C3 D2 V2 D1 V1 D0 V0 Function VOLUME You can control sound level of playback by using this command. C3 is to select either the left channel or right channel, and V2 ~ V0 is to select a proper sound level. C3 0 1 Function LEFT VOLUME CONTROLL RIGHT VOLUME CONTROLL V2 0 0 0 0 1 1 1 1 V1 0 0 1 1 0 0 1 1 V0 0 1 0 1 0 1 0 1 VOL.VALUE 0 dB * - 3 dB - 6 dB - 9 dB - 12 dB - 15 dB - 18 dB - 21 dB * Default 7) POWER DOWN Command D7 0 D6 1 D5 1 D4 0 D3 W3 D2 W2 D1 X D0 X Function POWER DOWN Inputting this command puts the LSI into power down status, where the LSI stops oscillation and minimize power consumption. Output from the AOUTL and AOUTR dropped down to the GND level instantaneously. W3 enables you to control power down/reset and W2 to define whether initialize the LSI or not. W3 0 1 Function RESUME POWER DOWN POWER DOWN W2 0 1 Function NOT initialize the LSI Initialize the LSI Page22 Semiconductor MSM9844 8) Select Algorithm Command D7 0 D6 1 D5 1 D4 1 D3 P3 D2 P2 D1 P1 D0 P0 Function SELECT ALGORITHM You can select a voice synthesis algorithm with this command. You can select one out of ten listed below with P3 ~ P0. You cannot change the algorithm during playback operation. P3 0 0 0 0 0 0 0 0 1 1 P2 0 0 0 0 1 1 1 1 0 0 P1 0 0 1 1 0 0 1 1 0 0 P0 0 1 0 1 0 1 0 1 0 1 4bit ADPCM2 * 5bit ADPCM2 6bit ADPCM2 7bit ADPCM2 8bit ADPCM2 4bit ADPCM 8bit Linear PCM 8bit Non-Linear PCM 16bit Linear PCM * Default Algorithm Page23 Semiconductor MSM9844 9) Analog Setup 1 Command D7 1 D6 0 D5 0 D4 0 D3 R3 D2 R2 D1 R1 D0 R0 Function ANALOG SETUP 1 This command allows you to select either internal/external DAC to be used, binary or two's compliment and stereo or monaural for playback. At powering up, output from the AOUTL and AOUTR pins rises to 1/2 VDD level instantaneously, disregarding the setup value at R0. Function 2's Complimentary Binary * Binary R2 0 1 Function INTERNAL D/A C * EXTERNAL D/A C R1 X Function No particular function R0 0 1 Function Monaural PLAYBACK * Stereo PLAYBACK * Default R3 0 1 Page24 Semiconductor MSM9844 10) Analog Setup 2 Command D7 1 D6 0 D5 0 D4 1 D3 A3 D2 A2 D1 E1 D0 E0 Function ANALOG SETUP 2 You can select enable/disable driving amplifier and enable/ disable LPF for the AOUTL and AOUTR pins with A3 and A2. You can also select a data bus width with E1 and E0, and when 8-bit bus selected, you can further select whether to use D15 ~ D8 pins for sound data transfer. A3 0 1 Function USED Output Amplifire * NOT USED Output Amplifire A2 0 1 Function USED internal LPF * NOT USED intrenal LPF E1 0 0 1 E0 0 1 X Function 8bit BUS Width, D15 to D8 unused * 8bit BUS Width, D15 to D8 used 16bit BUS Width * Default 11) Define FIFO Size Command D7 1 D6 0 D5 1 D4 0 D3 X D2 X D1 B1 D0 B0 Function DEFINE FIFO SIZE By using this command you can define the size of FIFO memory. B1 0 0 1 1 B0 0 1 0 1 8bit BUS Width 16bit BUS Width 128 bytes 64 bytes 32 bytes 64 words 32 words 16 words NOT USED FIFO Memory Page25 Semiconductor MSM9844 12) Signal Output Format Command D7 1 D6 0 D5 1 D4 1 D3 F3 D2 D2 D1 D1 D0 D0 Function SIGNAL OUTPUT FORMAT By using this command you can select output format from the EMP, FUL and DREQL/R pins, and input format to the DACKL/R pins. Function "H" Active for EMP, MID, and FUL Output * "L" Active for EMP, MID, and FUL Output D2 0 1 Function "H" Active for DREQL, and DREQR Output * "L" Active for DREQL, and DREQR Output D1 0 1 Function "L" Active for DACKL, and DACKR Input * "H" Active for DACKL, and DACKR Input D0 0 1 Function No particular function NOT USED * Default F3 0 1 13) Select DMA Transfer Command D7 1 D6 1 D5 0 D4 0 D3 G3 D2 G2 D1 G1 D0 X Function SELECT DMA TRANSFER By using this command you can select enable/disable DMA Transfer and DMA Transfer mode. G3 0 1 1 G2 X 0 0 G1 X 0 1 Function Not used DMA Transfer * DMA Transfer by Single Mode DMA Transfer by Block Mode * Default Page26 Semiconductor MSM9844 14) Select Serial Port Data Format Command D7 1 D6 1 D5 0 D4 1 D3 I3 D2 X D1 J1 D0 J0 Function SELECT PORT DATA FORMAT By using this command you can select a data format for the Serial Port. Note that this command is valid only when R2 value of the Analog Setup 1 command is set to "1" I3 0 1 Function VCK, SIOCK Master Mode * VCK, SIOCK Slave Mode J1 0 0 1 1 J0 0 1 0 1 I IS FORMAT, 16bit(Mode2) * Default Function MSB First, 16 bit(Mode 1) * LSB First Page27 Semiconductor MSM9844 15) Test Command D7 1 D6 1 D5 1 D4 1 D3 T3 D2 T2 D1 T1 D0 T0 TEST Function This command is used only for testing the LSI. You are not allowed to use the command. 16) Status Read You can monitor the MSM9844 internal status with read-out data from D7 to D0. The table shows the each status from D7 to D0. Pin Name Status During Playback Lch During Playback Rch Pausing Lch Pausing Rch FIFO EMP Signal FIFO MID Signal FIFO FUL Signal Data is writen to FIFO at FUL status D7 D6 D5 D4 D3 D2 D1 D0 Page28 Semiconductor MSM9844 * The Internal LPF Characteristics for AOUTL and AOUTR pins There are two LPFs on MSM9844, which is consisted of Digital Filter Technology. Figure shows each Frequency Characteristics of internal LPFs when the sampling frequency is at 8kHz and 16kHz. 0 -10 -20 -30 -40 dB -50 -60 -70 -80 -90 -100 100 1000 Hz Frequency Characteristics of internal LPF at 8kHz sampling Frequency. 10000 100000 0 -10 -20 -30 -40 dB -50 -60 -70 -80 -90 -100 100 1000 Hz Frequency Characteristics of internal LPF at 16kHz sampling Frequency. 10000 100000 Page29 Semiconductor MSM9844 *Application Circuit Sample Sample 1 for interface with DMA Controller Data Bus MEMORY MSM9844 DMA Controller D15 to D0 DREQL DACKL IOW DREQR DACKR CPU or MCU RD WR CS D/C Sample 2 for interface with External Memory Data Bus MEMORY MSM9844 D15 to D0 CPU or MCU RD WR CS D/C EMP MID FUL Page30 Semiconductor MSM9844 *Package Dimensions (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5m or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code, and desired mounting conditions (reflow method, temperature and times). Page31 Semiconductor MSM9844 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-todate. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit and assembly designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g. office automation, communication equipment, measurement equipment, consumer electronics ,etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co.,Ltd. Page32 |
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