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Correlated Double Sampler (CDS) AD9823
FEATURES
40 MHz correlated double sampler (CDS) Fixed 3.5 dB CDS gain Low noise optical black clamp circuit 3 V single-supply operation 14-lead TSSOP package
FUNCTIONAL BLOCK DIAGRAM
AD9823
3.5dB FIXED GAIN OUTPUT BUFFER
CCDIN
CDS
OUTPUT
APPLICATIONS
Digital still cameras Digital video camcorders CCTV cameras PC cameras Portable CCD imaging devices
BYP2
CLP
CLP OUTPUT BUFFER REFOUT
INTERNAL TIMING
INTERNAL REFERENCE
VDD GND
04538-0-001
SHP
SHD
BYP1
BYP3
Figure 1. Functional Block Diagram
PRODUCT DESCRIPTION
The AD9823 is a correlated double sampler for digital camera applications. It features a 40 MHz CDS amplifier with 3.5 dB of fixed gain, an internal voltage reference supply, and timing control for the SHP and SHD sampling clocks. Output buffers are also included, providing drive strength for PCB traces and direct connection to an image signal processor such as the AD9821. The AD9823 is ideal for applications that need to place the CDS and VGA/ADC circuits on separate PC boards. The "pseudo differential" outputs of the AD9823 provide good signal integrity when interfaced with the differential input AD9821. The AD9823 operates from a single 3 V power supply, typically dissipates 50 mW, and is packaged in a 14-lead TSSOP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9823 TABLE OF CONTENTS
Specifications..................................................................................... 3 General Specifications ................................................................. 3 Analog Specifications................................................................... 3 Digital Specifications ................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics ...............................................................5 ESD Caution...................................................................................5 Pin Configuration and Function Descriptions..............................6 SHP and SHD Timing ..................................................................6 Outline Dimensions ..........................................................................8 Ordering Guide .............................................................................8
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 8
AD9823 SPECIFICATIONS
GENERAL SPECIFICATIONS
Table 1.
Parameter Temperature Range Operating Storage Power Supply Voltage Power Consumption: fSAMP = 40 MHz, VDD = 3.0 V Maximum Clock Rate Minimum Clock Rate Min -25 -65 2.7 50 40 5 Typ Max +85 +150 3.6 Unit C C V mW MHz MHz
ANALOG SPECIFICATIONS
Table 2. TMIN to TMAX, VDD = 3.0 V, fSAMP = 40 MHz, unless otherwise noted.
Parameter Analog Input (CCDIN) Max Input Range Before Saturation1 Allowable CCD Reset Transient1 Max CCD Black Pixel Amplitude1 Gain Nonlinearity, 500 mV Input Input Referred Noise Clamp Time Constant Analog Outputs Typical Data Out Signal Range REFOUT Voltage Level Min Typ 850 500 100 3.5 1.0 100 190 Max Unit mV p-p mV mV dB % V rms sec V V Notes
2.5
4.5
Max deviation from ideal straight line Output noise divided by 3.5 dB gain 0.1 F BYP2 capacitor (proportional to capacitor value) 0.5 V corresponds to black level Fixed dc reference for signal output
0.5 0.5
1.5
1
Input signal characteristics defined as follows:
All specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Table 3.
Parameter Logic Inputs (SHP, SHD, CLP) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Symbol VIH VIL IIH IIL CIN Min 2.1 0.6 10 10 10 Typ Max Unit V V A A pF
04538-0-002
500mV TYP RESET TRANSIENT 100mV TYP OPTICAL BLACK PIXEL 850mV TYP INPUT SIGNAL RANGE
Rev. 0 | Page 3 of 8
AD9823
TIMING SPECIFICATIONS
Table 4. TMIN to TMAX, VDD = 3.0 V, fSAMP = 40 MHz, unless otherwise noted.
Parameter (See Figure 3) Sample Clocks SHP, SHD Clock Period SHP Pulse Width SHD Pulse Width CLP Pulse Width1 SHP Rising Edge to SHD Rising Edge SHD Rising Edge to SHP Rising Edge Internal Clock Delay Recommended Data CLK Timing (for AD9821) Symbol tCP tSHP tSHD tCOB tS1 tS2 tID tREC Min 25 5 5 4 12.0 12.0 Typ Max Unit ns ns ns pixels ns ns ns ns
6.25 6.25 10 12.5 12.5 3.0 4.5
1
Minimum CLP pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to change without notice.
Rev. 0 | Page 4 of 8
AD9823 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter VDD SHP, SHD BYP1, BYP2, BYP3 CCDIN DATAOUT, REFOUT CLP Junction Temperature Lead Temperature (10 sec) With Respect To GND GND GND GND GND GND Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max 3.9 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 150 350 Unit V V V V V V C C
THERMAL CHARACTERISTICS
Thermal Resistance 14-Pin, TSSOP Package JA = 89.2C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 8
AD9823 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLP 1 NC 2 VDD 3
14 13
SHP SHD
GND TOP VIEW 11 CCDIN (Not to Scale) DATAOUT 5 10 NC
12
AD9823
REFOUT 4
GND 6 BYP1 7
9 8
BYP3 BYP2
NC = NO CONNECT
Figure 2. Pin Configurations
Table 6. Pin Function Descriptions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name CLP NC VDD REFOUT DATAOUT GND BYP1 BYP2 BYP3 NC CCDIN GND SHD SHP Type1 DI NC P AO AO P AO AO AO NC AI P DI DI Description Input Clamp Clock Input (active low, not latched internally). No connection should be connected to GND or VDD. Analog Supply. Output Reference Level. Output Data Signal. Analog Ground. Internal Bias Level Decoupling. Internal Bias Level Decoupling. Internal Bias Level Decoupling. No connection should be connected to GND or VDD. CCD Input. Analog Ground. CDS Sampling Clock Input (For CCD Data Level). CDS Sampling Clock Input (For CCD Ref Level).
1
AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power, NC = No Connect.
SHP AND SHD TIMING
CCD SIGNAL
N
N+1
N+2
04538-0-003
N+9
N+10
tID tID
SHP
tCP
tSHD
SHD
tSHP
tS1
tS2
DATAOUT
tREC
Figure 3. SHP and SHD Timing
Rev. 0 | Page 6 of 8
04538-0-004
DATACLK (FOR AD9821)
AD9823
EFFECTIVE PIXELS OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS
CCD SIGNAL
CLP
Figure 4. CLP Timing
3V ANALOG SUPPLY
4.7F CLP
0.1F CLP NC VDD
1 2 3 4 5 6 7 14 13
SHP SHD GND 0.1F
SHP SHD
REFOUT
(CONNECT TO VIN- ON AD9821)
REFOUT DATAOUT GND BYP1 0.1F
AD9823
12
DATAOUT
(CONNECT TO VIN+ ON AD9821)
TOP VIEW 11 CCDIN (Not to Scale) NC
10 9 8
CCDIN
BYP3 BYP2
04538-0-005
NC = NO CONNECT
0.1F
0.1F
Figure 5. AD9823 Circuit Configuration
3V ANALOG SUPPLY 0.1F 1.0F SERIAL INTERFACE 3 1.0F
NC NC SCK SDATA SL STBY NC DVSS DVDD2 VRB VRT NC
3V 3V ANALOG SUPPLY ANALOG SUPPLY
36 35 34 33
48 47 46 45 44 43 42 41 40 39 38 37
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 (MSB) D11 DATA 12 OUTPUTS
1 2 3 4 5 6 7 8 9 10 11 12
PIN 1 IDENTIFIER
AD9821
TOP VIEW (Not to Scale
32 31 30 29 28 27 26 25
TEST AVSS TEST AVDD2 BYP1 VIN- VIN+ TEST TEST AVDD1 AVSS AVSS
0.1F 4.7F 0.1F IMAGER INPUT, NEGATIVE IMAGER INPUT, POSITIVE 0.1F
CLP NC VDD REFOUT DATAOUT GND BYP1 0.1F
CLP SHP SHD
1 2 3 4 14 13
AD9823
12
TOP VIEW 11 5 (Not to Scale) 10
6 7 9 8
SHP SHD GND CCDIN NC BYP3 BYP2 0.1F
0.1F
OUTPUT FROM CCD
0.1F
3V ANALOG SUPPLY 0.1F 4.7F
13 14 15 16 17 18 19 20 21 22 23 24
3V DRIVER SUPPLY
DRVDD DRVSS DVSS DATACLK DVDD1 NC PBLK CLPOB TEST TEST TEST NC
NC = INTERNALLY NOT CONNECTED
0.1F 3 CLOCK INPUTS
04538-0-006
0.1F 3V ANALOG SUPPLY
Figure 6. Circuit Configuration with the AD9821 12-Bit Image Signal Processor
Rev. 0 | Page 7 of 8
04538-0-007
AD9823 OUTLINE DIMENSIONS
5.10 5.00 4.90
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 8 0 0.75 0.60 0.45
SEATING COPLANARITY PLANE 0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 7. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9823BRUZ1 Temperature Range -25C to +85C Package Description TSSOP Package Option RU-14
1
Z = Pb-free part.
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.. C04538-0-11/03(0)
Rev. 0 | Page 8 of 8

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