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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
PM5382
S/UNI-16X155
SATURN USER NETWORK INTERFACE (16X155)
REFERENCE DESIGN
PRELIMINARY
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue No. 1 Issue Date August 2001 Details of Change Document created
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
CONTENTS 1 INTRODUCTION ......................................................................................1 1.1 1.2 2 REFERENCE DESIGN FUNCTIONALITY.....................................1 REFERENCE DESIGN FEATURES ..............................................2
APPLICATIONS ........................................................................................3 2.1 2.2 2.3 2.4 2.5 ATM DROP SIDE LOOP BACK......................................................4 ATM TRANSPARENT ....................................................................5 POS DROP SIDE LOOP BACK .....................................................6 POS TRANSPARENT ....................................................................7 AUTOMATIC PROTECTION SWITCHING (APS)..........................8 2.5.1 SINGLE BOARD 1+1 APS ..................................................8 2.5.2 SINGLE BOARD 1:N APS ...................................................9 2.5.3 MULTIPLE BOARD 1+1 APS ............................................10 2.6 WAN SYNCHONIZATION FUNCTIONALITY............................... 11 2.6.1 SYNCHRONIZATION USING RECOVERED CLOCK SIGNALS........................................................................... 11 2.6.2 SYNCHRONIZATION USING PHASE COMPARATOR.....12 2.7 2.8 REFERENCE DESIGN WITH OTHER ATM DEVICES................13 REFERENCE DESIGN WITH PACKET SWITCH .......................14
3 4 5
REFERENCES .......................................................................................15 DEVICE BLOCK DIAGRAM....................................................................16 REFERENCE DESIGN FUNCTIONAL DESCRIPTION..........................17 5.1 BLOCK DIAGRAM .......................................................................17
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PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
6 7
SYSTEM FUNCTIONAL DESCRIPTION................................................18 IMPLEMENTATION DESCRIPTION .......................................................19 7.1 7.2 ROOT DRAWING, SHEET 1 ........................................................19 SUNI_BLOCK SHEET 2 ..............................................................19 7.2.1 OPTICAL TRANSCEIVER INTERFACES .........................19 7.3 7.4 7.5 7.6 S/UNI BLOCK, SHEET 2..............................................................19 S/UNI BLOCK SHEET 3 ..............................................................23 S/UNI BLOCK SHEET 4 ..............................................................24 SUNI_BLOCK, SHEET 5..............................................................24 7.6.1 UTOPIA/POS-PHY LEVEL 3 INTERFACE ........................24 7.6.2 APS INTERFACE ..............................................................24 7.7 S/UNI BLOCK, SHEET 6..............................................................26 7.7.1 MICROPROCESSOR INTERFACE ..................................26 7.7.2 JTAG INTERFACE ............................................................26 7.7.3 RECEIVE ALARM OUTPUTS ...........................................26 7.7.4 CLOCKS............................................................................26 7.7.5 SECTION AND LINE STATUS DCC SIGNALS .................27 7.8 S/UNI BLOCK, SHEET 7..............................................................28 7.8.1 POWER SUPPLY FILTER AND REGULATOR SHEET.....28 7.8.2 PASSIVE RC LOW PASS POWER SUPPLY FILTER .......29 7.8.3 LINEAR REGULATOR FILTER METHOD .........................31 7.9 FPGA BLOCK , SHEET 8.............................................................32 7.9.1 CONTROL REGISTER FUNCTION ..................................33
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
REGISTER 0X2000H: S/UNI CONTROL REGISTER..................34 REGISTER 0X2200H: S/UNI CLOCK CONTROL REGISTER ....36 REGISTER 0X2400H: S/UNI RALRM REGISTER.......................38 REGISTER 0X2600H: LED REGISTER......................................39 7.9.2 ATM LOOP-BACK LOGIC .................................................39 7.9.3 POS LOOPBACK LOGIC ..................................................40 7.9.4 ATM AND POS TRANSPARENT.......................................40 7.9.5 PROCESSOR INTERFACE LOGIC ..................................40 7.9.6 S/UNI-16X155 UL3/PL3 INTERFACE ...............................40 7.9.7 STATUS LEDS AND RESET CIRCUIT..............................41 7.10 FPGA BLOCK, SHEET 9.............................................................42 7.10.1 SYSTEM SIDE UL3/PL3 INTERFACE ..............................42 7.11 FPGA BLOCK, SHEET 8..............................................................42 7.11.1 CONFIGURATION CIRCUIT .............................................42 7.11.2 POWER SUPPLY DECOUPLING .....................................42 7.12 FPGA BLOCK, SHEET 9..............................................................43 7.12.1 100 MHZ UL3/PL3 CLOCK DISTRIBUTION .....................43 7.12.2 100 MHZ CLOCK SOURCE SWITCHING.........................43 7.12.3 REFERENCE CLOCK OSCILLATOR AND SELECTION CIRCUITRY.......................................................................43 7.12.4 RECOVERED CLOCK ......................................................44 7.13 CPCI INTERFACE BLOCK, SHEET 12 .......................................46 7.13.1 CPCI INTERFACE CONTROLLER ...................................46 7.13.2 CPCI BUS PRECHARGE CIRCUIT ..................................47
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
7.14
CPCI INTERFACE BLOCK, SHEET 13 .......................................48 7.14.1 CPCI J1 CONNECTOR .....................................................48 7.14.2 ESD STRIP .......................................................................48
7.15
CPCI POWER_BLOCK, SHEET 14 .............................................48 7.15.1 HOT SWAP CONTROLLER SYSTEM BLOCK .................48
7.16
SYSTEM INTERFACE, SHEET 14 ..............................................49 7.16.1 UTOPIA/POS-PHY LEVEL 3 INTERFACE ........................49 7.16.2 APS AND SYS_REF INTERFACES ..................................56
8
PCB CONSIDERATIONS .......................................................................57 8.1 8.2 8.3 8.4 8.5 8.6 SUNI BLOCK, SHEET 2 ..............................................................57 SUNI BLOCK, SHEET 3 ..............................................................59 SUNI BLOCK, SHEET 4 ..............................................................61 SUNI BLOCK, SHEET 6 ..............................................................62 SUNI BLOCK, SHEET 7 ..............................................................62 GENERAL DESIGN NOTES ........................................................63
9 10 11
SCHEMATICS REVISION 1 ...................................................................64 PCB LAYOUT REVISION 1 ....................................................................65 BILL OF MATERIALS (BOM) REVISION 1 .............................................66
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
LIST OF FIGURES FIGURE 1: ATM DROP SIDE LOOP BACK.........................................................4 FIGURE 2: ATM TRANSPARENT........................................................................5 FIGURE 3: POS DROP SIDE LOOP BACK ........................................................6 FIGURE 4: POS TRANSPARENT .......................................................................7 FIGURE 5: SINGLE BOARD 1+1 APS ................................................................8 FIGURE 6: SINGLE BOARD 1:3 APS EXAMPLE ...............................................9 FIGURE 7: MULTIPLE BOARD 1+1 APS ..........................................................10 FIGURE 8: SYNCHRONIZATION USING RECOVERED CLOCK SIGNAL ...... 11 FIGURE 9: SYNCHRONIZATION USING PHASE COMPARATOR ..................12 FIGURE 10: REF DESIGN WITH OTHER ATM CHIPSETS..............................13 FIGURE 11: REF DESIGN WITH POS LINK LAYER DEVICE ..........................14 FIGURE 12: S/UNI-16X155 BLOCK DIAGRAM ................................................16 FIGURE 13: REFERENCE DESIGN BLOCK DIAGRAM ..................................17 FIGURE 14: SYSTEM LEVEL BLOCK DIAGRAM.............................................18 FIGURE 16: INTERFACING THE S/UNI-16X155 TO 3.3V OPTICS. ...............21 FIGURE 17: INTERFACING THE S/UNI-16X155 TO 5V OPTICS. ..................21 FIGURE 18: ECL BIAS VOLTAGE CIRCUITS..................................................22 FIGURE 19: OC-3 OPTICAL TRANSCEIVER TERMINATION LAYOUT..........23 FIGURE 20: DOUBLE ENDED APS TERMINATIONS .....................................25 FIGURE 21 SINGLE ENDED APS TERMINATIONS........................................25 FIGURE 22: TANTALUM & X5R CERAMIC CAP IMPEDANCE VS. FREQUENCY29 FIGURE 23: PASSIVE RC POWER SUPPLY FILTERING ................................30
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
FIGURE 24: LINEAR REGULATOR ANALOG POWER SUPPLY FILTERING..31 FIGURE 25: FPGA BLOCK DIAGRAM..............................................................33 FIGURE 26: HOST PROCESSOR CPCI INTERFACE......................................46 FIGURE 27: CPCI BUS PRECHARGE CIRCUIT ..............................................47 FIGURE 28: CPCI HOT SWAP CONTROLLER ................................................49
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
LIST OF TABLES TABLE 1: FPGA PIN ASSIGNMENT .................................................................32 TABLE 2: LED DISPLAY FUNCTION ................................................................41 TABLE 3: UL3/PL3 HIGH SPEED RX INTERFACE ..........................................50 TABLE 4: UL3/PL3 HIGH SPEED TX INTERFACE ...........................................53 TABLE 5: APS AND SYS_REF INTERFACE, J12 .............................................56
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
1
INTRODUCTION The PM5382 S/UNI-16X155 standard product supports 16 SATURN User Network Interfaces with SONET/SDH processing, ATM and Packet mapping functions at the STS-3c (STM-1) 155.52 Mbit/s rate with on-chip clock and data recovery and clock synthesis. The S/UNI-16X155 is intended for use in equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI), ATM Network-Network Interfaces (NNI), and Packet Over SONET/SDH (POS) interfaces. The POS interface can be used to support several packet based protocols, including the Point-to-Point Protocol (PPP). The S/UNI-16x155 may find application at either end of switch-to-switch links or switch-to-terminal links, both in public network (WAN) and private network (LAN) situations. This S/UNI-16X155 reference design provides a physical interface implementation of a 16 Port SONET/SDH line card for both ATM and POS applications. It provides sixteen single-mode or multi-mode optical interfaces at OC-3c rate, and a POS/PHY Level 3/UTOPIA Level 3, 104MHz, 32-bit wide system side synchronous interface. The in-system programmable FPGA provides a simple means to manipulate ATM cells and POS packets. The reference design board is also compatible with the S/UNI-4x622 device and can be assembled to support 4 OC-12c links. Refer to the S/UNI-4x622 Reference Design (PMC-2000064) and the Application Note Integrating Designs Using the S/UNI-16x155 and S/UNI-4x622 (PMC-2000539) for further information regarding this device and integrated design recommendations. The PM5382 is packaged in a 520 pin Super Ball Grid Array (SBGA) as shown below. For detailed information on the PM5382 device, please refer to the Standard Product Datasheet. The terms "CompactPCITM" and "cPCI" are used interchangeably within this document and should be considered equivalent.
1.1
Reference Design Functionality * * Supports 16 Single-Mode or Multi-Mode OC-3c 155.52 Mbit/s SONET/SDH Physical Layer ATM or POS Interfaces. Performs dropside loop back of ATM cells or POS Packets.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
* * * *
Provides a Utopia Level 3, 104 MHz, 32-bit ATM Multi-PHY System Interface to an external high-speed connector. Provides a POS-PHY Level 3, 104 MHz, 32-bit Packet Over SONET/SDH Multi-PHY System Interface to an external high-speed connector. Supports 1+1 or 1:n Automatic Protection Switching (APS). Provides hardware support for implementing a 16 port OC-3 linecard using a S/UNI-16x155 or a 4 port OC-12 linecard using a S/UNI-4x622 device.
1.2 Reference Design Features The reference design is based on a cPCI form factor card. The reference design will consist of * * * * * * * one PM5382 S/UNI-16x155. Sixteen OC-3 small form factor (SFF) optical data link transceivers. FPGA to support ATM & POS drop-side loop back and transparent operation. PLX cPCI Bridge for interfacing to the host processor. reference oscillators required for SONET and UL3/POS-PHY L3 interfaces. external 77.76 MHz reference clock interface for inter-board synchronization. powered by +3.3 Volts supply. +5.0 Volt components are avoided where possible.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2
APPLICATIONS The S/UNI-16X155 Reference Design demonstrates the physical interface implementation for both ATM and POS applications. The list below shows the networking equipment that can incorporate the S/UNI-16X155 device: * * * WAN and Edge ATM switches physical interfaces LAN switches and hubs physical interfaces Packet switches and hubs physical interfaces.
The S/UNI-16X155 Reference Design can be used in four modes: * * * * ATM Drop Side Loop Back ATM Transparent POS Drop Side Loop Back POS Transparent.
Each of these modes is described in detail in the following sections. APS (Automatic Protection Switching) may be enabled during any one of these modes, and is described separately. Support for WANS (WAN Synchronization) is provided, and is described separately.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.1
ATM Drop Side Loop Back Each optical data link (ODL) transceiver will provide a received STS-3c signal to the S/UNI-16x155. Clock and Data recovery will be performed independently for each of the 16 input signals, and ATM cells will be extracted from the STS-3c payloads. After payload descrambling and error processing, ATM cells will be provided to the Utopia Level 3 (UL3) compliant RX interface on the PM5382. The FPGA can be configured to loop the received ATM cells back to the UL3 compliant TX interface on the PM5382. This loop back is performed on a PHY by PHY basis (i.e. each ATM cell will be looped back to the ODL transceiver from which it was received.) The UL3 compliant TX interface will accept ATM cells from the FPGA. The ATM cell payload will be scrambled and inserted into the transmitted STS-3c payload. Each of the 16 optical transceivers will accept one STS-3c signal for transmission via the optical data link. Figure 1: ATM Drop Side Loop Back
S/UNI-16X155 REFERENCE DESIGN
PM5382 S/UNI-16X155 in ATM mode
STS-3c UTOPIA Level 3 ATM Cell Loop-back
ODL 1 ODL 2 OC-3c ATM TESTER
OC-3c
FPGA
SYS I/F Conn
ODL 15 ODL 16
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PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.2
ATM Transparent Each ODL transceiver will provide a received STS-3c signal to the S/UNI-16x155. Clock and Data recovery will be performed on the input signals, and ATM cells will be extracted from the STS-3c payloads. After payload descrambling and error processing, ATM cells will be provided to the Utopia Level 3 (UL3) compliant RX interface on the PM5382. The FPGA can be configured to direct the cells to the UL3 compliant RX interface provided by the System Interface connector. This interface will provide ATM cells to an external system such as an ATM tester or Link layer device, and accept cells originating from the external system. The UL3 compliant TX interface will accept cells via the FPGA. The ATM cell payload will be scrambled and inserted into the transmitted STS-3c payload. Each of the 16 optical transceivers will accept one STS-3c signal for transmission via the optical data link. Figure 2: ATM Transparent
S/UNI-16x155 REFERENCE DESIGN
PM5382 PM5382 S/UNI 16x155 in S/UNI-16X155 in ATM mode ATM mode
UTOPIA Level 3
ODL 1 ODL 2 OC-3c ATM TESTER
OC-3c STS-3c
FPGA
SYS I/F Conn UTOPIA L3 ATM Tester
ODL 15 ODL 16 ATM Cell Transparent
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PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.3
POS Drop Side Loop Back Each ODL transceiver will provide a received STS-3c signal to the S/UNI-16x155. Clock and Data recovery will be performed for each of the input signals, and POS packets will be extracted from the STS-3c payloads. After payload descrambling and error processing, POS packets will be provided to the POS-PHY Level 3 compliant RX interface on the PM5382. The FPGA can be configured to loop the received POS packets back to the PL3 compliant TX interface on the PM5382. This loop back is performed on a PHY by PHY basis. The POS-PHY L3 compliant TX interface will accept POS packets from the FPGA. The POS packet payload will be scrambled and inserted into the transmitted STS-3c payload. Each of the 16 optical transceivers will accept one STS-3c signal for transmission via the optical data link. Figure 3: POS Drop Side Loop Back
S/UNI-16X155 REFERENCE DESIGN
PM5382 S/UNI-16X155 in POS mode
STS-3c POS/PHY Level 3
ODL 1 ODL 2 OC-3c SONET TESTER
OC-3c
FPGA
SYS I/F Conn
ODL 15 ODL 16
POS Packet Loop-back
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PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.4
POS Transparent Each ODL transceiver will provide a received STS-3c signal to the S/UNI-16x155. Clock and Data recovery will be performed for each of the input signals, and POS packets will be extracted from the STS-3c payloads. After payload descrambling and error processing, ATM cells will be provided to the POS-PHY Level 3 (PL3) compliant RX interface on the PM5382. The FPGA can be configured to direct the POS traffic to the PL3 compliant TX System interface on the backplane connector. This interface will provide POS packets to an external system such as a POS tester or Link Layer device, as well as accept packets from the external system. The POS-PHY L3 compliant TX interface on the PM5382 will accept packets via the FPGA. The POS packets will be scrambled, and inserted into the transmitted STS-3c payload. Each of the 16 optical transceivers will accept one STS-3c signal for transmission via the optical data link. Figure 4: POS Transparent
S/UNI-16x155 REFERENCE DESIGN
PM5382 PM5382 S/UNI 16x155 in S/UNI-16X155 in ATM mode POS mode
UTOPIA Level 3
ODL 1 ODL 2 OC-3c SONET TESTER
OC-3c STS-3c
FPGA
SYS I/F Conn
ODL 15 ODL 16 POS Packetl Transparent
POS Tester or Higher Layer PL3 devices
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.5
Automatic Protection Switching (APS) The S/UNI-16x155 has the ability to exchange transmit path data with another S/UNI-16x155 in order to implement an APS interface. The APS support logic may also be used to reassign at the path level the channel numbers in a single S/UNI-16x155. With this logic, 1+1 or 1:N APS configurations can be implemented internal to a single PM5382.
2.5.1 Single Board 1+1 APS The APS logic on the S/UNI-16x155 allows implementation of 1+1 APS without any external connections. Eight of the sixteen channels supported by the PM5382 are configured as working circuits, while the remaining eight are configured as protection circuits. Should the "Working TX" or "Working RX" optical links be interrupted, the "Protection TX" and "Protection RX" links will be utilized. Figure 5: Single Board 1+1 APS
Working TX Protection TX Working TX Protection RX Protection TX Working RX Working RX Protection RX
APST
APST
APST
APST
PM5382, (Ch. 0) Working
APSR
PM5382, (Ch 1) Protection
APSR
PM5382, (Ch. 14) Working
APSR
PM5382, (Ch. 15) Protection
APSR
UL3 or POS-PHY L3 Interface
All APS switching performed internal to PM5382. No external connections required.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.5.2 Single Board 1:N APS This mode allows a single reference design to demonstrate 1:N APS functionality with N-1 channels supported by the PM5382 configured as working circuits, and a remaining channel configured as a protection circuit. Should the "Working TX" or "Working RX" optical links be interrupted, the "Protection TX" and "Protection RX" links will be utilized to restore the highest priority "Working" link. Figure 6: Single Board 1:3 APS Example
Working TX Working RX Working TX Working RX Protection TX Protection RX
APS Output APS Input
Working TX
APS Output
Working RX
APS Output
APS Output
PM5382, (Ch. 0) Working
APS Input
PM5382, (Ch 1) Working
APS Input
PM5382, (Ch. 2) Working
APS Input
PM5382, (Ch. 3) Protection
UL3 or POS-PHY L3 Interface
All APS switching performed internal to PM5382. No external connections required.
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PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.5.3 Multiple Board 1+1 APS When implementing APS across two devices, four 622.08Mbit/sec links are used. Each link carries path information for four channels of the PM5382 device. The receive APS logic can be configured to map the channels within the link data stream to specific outputs as required. For protection schemes implemented using multiple devices, care should be taken to ensure that the REFCLKs on all the boards are frequency locked to guarantee the data recovery units will function properly. Figure 7 below outlines a 1+1 protection scheme. Four channels of a possible 16 are shown for simplicity. Figure 7: Multiple Board 1+1 APS
Working TX Working TX Working RX Working RX Working TX Working RX Working TX Working RX
APS Output
APS Output
APS Output
APS Output
PM5382, (Ch. 0) Working
APS Input
PM5382, (Ch 1) Working
APS Input
PM5382, (Ch. 2) Working
APS Input
PM5382, (Ch. 3) Working
Working Card
APS Input
UL3 or POS-PHY L3 Interface
APSO[x]
Protection TX
Protection RX
Protection TX
Protection RX
APSI[x]
APS Output
Protection RX
Protection RX
Protection TX
Protection TX
APS Output
APS Output
APS Output
PM5382, (Ch. 0) Protection
APS Input
PM5382, (Ch 1) Protection
APS Input
PM5382, (Ch. 2) Protection
APS Input
PM5382, (Ch. 3) Protection APS
Protection Card
Input
UL3 or POS-PHY L3 Interface
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.6
WAN Synchonization Functionality The S/UNI-16x155 Reference Design can be used to facilitate WAN Synchronization (WANS) Functionality in two different ways:
2.6.1 Synchronization Using Recovered Clock Signals The WANS block on the S/UNI-16x155 performs a digital phase comparison between a recovered receive clock from one of the STS-3c channels and an external reference clock, usually implemented with a VCXO. This external reference clock is used to generate transmit timing for all channels. On the S/UNI-16x155 Reference Design, the recovered clock signal is routed to an external connector that can interface to a separate timing card. The adjusted reference clock is distributed from the timing card to all cards in the system. Figure 8: Synchronization Using Recovered Clock Signal
S/UNI-2488 REFERENCE DESIGN S/UNI-4x622 REFERENCE DESIGN S/UNI-16x155 REFERENCE DESIGN
S/UNI-16x155 REFERENCE DESIGN
ODL 1 ODL 2
OC-3c STS-3c
PM5382 S/UNI-16x155 77.76 MHz Reference Clock
ODL 15 ODL 16
from CRU
Selected Recovered Clock
WANS Clocking Card 77.76 MHz Reference Clock High Stability Oscillator Phase Comparator Recovered 77.76 MHZ clocks from other boards
Control
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PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.6.2 Synchronization Using Phase Comparator The PM5382 is also able to compare the phase of the locally provided 77.76 MHz Reference Clock to that of the data clocks recovered from the incoming OC3c signal. An external clocking card would then use phase information to lock a local high stability reference oscillator. Performing the phase comparisons within the PM5382 eliminates the need to transmit all recovered clocks back to the clocking card. Figure 9: Synchronization Using Phase Comparator
S/UNI-2488 REFERENCE DESIGN S/UNI-4X622 REFERENCE DESIGN S/UNI-16x155 REFERENCE DESIGN PM5382 S/UNI-16x155
Phase Comp
S/UNI-16x155 REFERENCE DESIGN
ODL 1 ODL 2
OC-3c STS-3c
77.76 MHz Reference Clock
ODL 15 ODL 16
Host I/F
Phase information read via Host Interface
WANS Clocking Card 77.76 MHz Reference Clock High Stability Oscillator
Digital PLL
Controller
with Host I/F
Phase information read via Host Interface
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PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
2.7
Reference Design with other ATM Devices This reference board may potentially be used within a larger system utilizing PMC-Sierra's ATM chip sets. Figure 10: Ref Design with other ATM Chipsets
Utopia Level 3 Utopia Level 3 Optics
OC-3 (x16)
Traffic Management
ATM Layer
PM5382 S/UNI-16x155 Ref Design
ATM Switch Fabric
Optics
Traffic Management
ATM Layer
PM5381 S/UNI-2488 Ref Design
OC-48
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S/UNI-16X155 REFERENCE DESIGN
2.8
Reference Design with Packet Switch This reference board may potentially be used within a larger system utilizing packet switch and link layer processors as shown below. Figure 11: Ref Design with POS Link Layer Device
POS-PHY Level 3 Optics
OC-3 (x16)
Packet/IP Switch
Packet PHY Port Interface Processor
PM5382 S/UNI-16x155 Ref Design
Optics
OC-48
Packet PHY Port Interface Processor
PM5381 S/UNI-2488 Ref Design
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
3
REFERENCES 1. ATM Forum - STR-PHY-UL3-01.00, "UTOPIA Level 3", July 1999. 2. Bell Communication Research - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, December 1995. 3. CompactPCITM specification, PICMG 2.0 R2.1, September 2, 1997. 4. PMC-Sierra, Inc., PMC-200-0495 "PM5382 S/UNI-16x155 Data Sheet", Issue 1,.September, 2000. 5. PMC-Sierra, Inc., PMC-200-0056 "PM5358 S/UNI-4X622 Data Sheet", Issue 1, January 5, 2000. 6. PMC-Sierra, Inc., PMC-200-0539 "Integrating Board Designs Using the S/UNI-16x155 and S/UNI-4x622", Issue 1, April 2000. 7. PMC-Sierra, Inc., PMC-980495 "POS-PHY Level 3", Issue 4, November 1999.
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4
PMC-2000506
PRELIMINARY
REFERENCE DESIGN
TDCC[15:0]
TCLK TFCLK TENB TADR[3:0] TSX TCA/TPA STPA TSOC/TSOP TPRTY TDAT[31:0] TMOD[1:0] TEOP TERR RFCLK RENB RADR[3:0] RSX RCA/RVAL RSOC/RSOP RPRTY RDAT[31:0] RMOD[1:0] REOP RERR JTAG Test Access Port External APS Interface Microprocessor Interface Tx Tx ATM Tx ATMCell ATMCell Cell Processor Processor Processor Section/ Section/ Section/ Line DCC Line DCC Line DCC Insertion Insertion Insertion Tx Tx Tx POS Frame POS Frame POS Frame Processor Processor Processor
TDCLK[15:0]
TFPO
TFPI
TXD[15:0]+/Tx Tx Tx Section O/H Section O/H Section O/H Processor Processor Processor Tx Tx Tx Line O/H Line O/H Line O/H Processor Processor Processor Tx Tx Path Tx PathO/H PathO/H O/H Processor Processor Processor
RXD[15:0]+/-
ISSUE 1
DEVICE BLOCK DIAGRAM
SD[15:0]
REFCLK+/-
TDREF1, TDREF0 Section Section Section Trace Buffer Trace Buffer Trace Buffer Rx Rx ATM Rx ATMCell ATMCell Cell Processor Processor Processor WAN WAN WAN Synch. Synch. Synch. Path Path Trace Path TraceBuffer TraceBuffer Buffer
ATP[1:0]
QAVD
Path Crossbar/ APS Crossconnect
Serial Line Interface Serial Line Interface Serial Line Interface
QAVS Rx Rx Rx Section O/H Section O/H Section O/H Processor Processor Processor Rx Rx Rx Line O/H Line O/H Line O/H Processor Processor Processor Rx Rx Path Rx PathO/H PathO/H O/H Processor Processor Processor
AVD[8:0]
Figure 12: S/UNI-16X155 Block Diagram
UTOPIA Level 3/POS-PHY Level 3 System Interface
AVS[8:0]
SPECLV Section/ Section/ Section/ Line DCC Line DCC Line DCC Extraction Extraction Extraction Sync Status, Sync Status, Sync Status, BERM BERM BERM
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Rx Rx Rx POS Frame POS Frame POS Frame Processor Processor Processor TDI ALE TCK CSB TDO RDB TMS INTB WRB RCLK RSTB D[7:0] A[13:0] TRSTB APECLV APSI[3:0]+/RDCC[15:0] POS_ATMB APSO[3:0]+/RDCLK[15:0]
SDTTL
S/UNI-16X155 REFERENCE DESIGN
16
APREF0, APREF1
RFPO
PM5382 - S/UNI 16X155
RALRM[15:0]
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
5 5.1
REFERENCE DESIGN FUNCTIONAL DESCRIPTION BLOCK DIAGRAM This figure depicts the major functional blocks of the Reference Design. Figure 13: Reference Design Block Diagram
OC-3c
OC-3 ODL 1
TX/RX
Power Supply Filters and Regulator OC-3 ODL 2
PECL STS-3 TX/RX
100 MHz Reference Osc.
UTOPIA/ POS-PHY Level 3
OC-3c
PM 5382 S/UNI-16x155 OC-3 ODL 15
TX/RX
UTOPIA/ POS-PHY Level 3
Control Signals
ATM Cell/ POS Packet Loopback/ Transparent FPGA AMP HS3 Connector
FPGA PROM
OC-3c
OC-3c
OC-3 ODL 16
TX/RX
TX
Processor Interface
APS I/O 8 x 622 Mbps PECL
Ext. FPGA Download or 1 of 2 PROMS
77.76 MHz External Reference clock
Status LEDs
77.76 MHz Internal Reference clock 77.76 MHz Ref Osc.
77.76 MHz Recovered clock 77.76 MHz External Reference clock
PLX PCI Bridge cPCI J1 Connector
cPCI Power Management
cPCI PCI Bus
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
6
SYSTEM FUNCTIONAL DESCRIPTION This Reference Design conforms to cPCI standards and implements a cPCI interface for configuration and control. A minimal implementation of the system is composed of a cPCI chassis, the S/UNI-16x155 Reference Design PCB, Pentium PCI board with operating system SW, and an external PC with terminal emulation software. In addition, an external SONET ATM and/or POS tester is required to generate and receive ATM or POS data to/from the S/UNI-16X155 framer. Figure 14: SYSTEM LEVEL BLOCK Diagram
cPCI CHASSIS Power supply
SONET/SDH ATM or POS Tester
S/UNI-16X155 Reference Design PCB X of 16 OC-3c
uP I/F J1 cPCI Backplane
O/S on Floppy
HD
cPCI Host Processor
RS-232
UTOPIA Level 3 (UL3) and POS-PHY Level 3 Interface
UL3 ATM or POS-PHY Level 3 Tester (optional)
Dumb Terminal or PC Terminal Emulator
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
7 7.1
IMPLEMENTATION DESCRIPTION ROOT DRAWING, Sheet 1 This sheet provides an overview of the major functional blocks of the S/UNI16x155 reference design. The schematic was designed in a hierarchical format. The interconnections between the top level SUNI_BLOCK, FPGA BLOCK, SYS_INTERFACE, POWER_BLOCK, CPCI_BLOCK, and OPTICS_CARD are identified on the Root sheet, and labeled with a "\I" designation on all subsequent sheets.
7.2
SUNI_BLOCK Sheet 2
7.2.1 Optical Transceiver Interfaces The S/UNI-16x155 Reference Design is based on a 9U form factor CPCI card and uses Small Form Factor (SFF) ODL modules that adhere to the Multiple Source Agreement (MSA) standard 2 x 5 pinout. Vendors supplying MSAcompliant ODLs include: AMP, Methode, MRV, Infineon, or Agilent Technologies (Hewlett Packard). 7.3 S/UNI BLOCK, Sheet 2 Sheet 2 shows the circuits for the optical modules for channels 0-4 and channel 7 on the S/UNI-16x155. All of the transmitted data (TXD) and received data (RXD) signals on this sheet are routed with controlled impedance 50 ohm transmission lines. Each differential pair is length matched. A minimum of passive components are required to interface the S/UNI-16x155 PECL I/Os to the optical tranceivers. Figure 15 and Figure 16 below outline the recommended terminations for 3.3V and 5V devices respectively. Note that the RXD+/- signals are internally terminated with a 100 ohm resistor. The SPECLV input is used to configure the PECL inputs to 3.3V or 5V tolerance. The SDTTL input is used to configure the Signal Detect inputs to accept either PECL or TTL input levels. The TXD+/- outputs are AC coupled so the ECL inputs of the optical module are free to swing around the ECL bias voltage (VBB). Generally the bias voltage is set 1.3V below the supply voltage. The bias voltage can be generated using a resistor divider (shown in Figure 17).
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
The TXD+/- outputs on the S/UNI-16x155 swing approximately 3.3V and require the combination of the series source resistor and the termination resistors to divide the output voltage down to a nominal 800mV swing. The series resistor attenuates the signal and dampens any signal reflections from the optics module. For calculations, the source impedance of the TXD+/- outputs is between 15 and 20 ohms. Vias should be avoided on the signal path between the optical module and the S/UNI-16x155 as they can affect the jitter performance of the interface. Vias may be used for the termination networks.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Figure 15: Interfacing the S/UNI-16x155 to 3.3V Optics.
RD+ 150W
3.3V Optical Module Interface
50W Trace Impedance 50W Trace Impedance 150W
RXD+ RXDS/UNI Optical Interface
S/UNI Optical Interface
RD-
TD+ 49.9W
50W Trace Impedance VBB (2.0V) 158W 0.1uF
TXD+
0.1uF 49.9W TDSD (PECL) 150W
158W 0.1uF 50W Trace Impedance TXDSD
Figure 16: Interfacing the S/UNI-16x155 to 5V Optics.
RD+ 330W
5.0V Optical Module Interface
50W Trace Impedance 50W Trace Impedance 330W
RXD+ RXD-
RD-
TD+ 49.9W
50W Trace Impedance VBB (3.7V) 158W 0.1uF
TXD+
0.1uF 49.9W TDSD (PECL) 330W
158W 50W Trace Impedance
0.1uF TXDSD
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Figure 17: ECL Bias Voltage Circuits.
+3.3V (OMD Supply) 220W VBB (2.0V) 330W 698W 237W VBB (3.7V) +5.0V (OMD Supply)
The bias voltage circuits can be shared between optical modules to reduce component count. Ensure that the divider is well decoupled and connected in a star configuration to the termination networks. Other configurations may cause data dependent jitter to be coupled between the optical modules. On the S/UNI-16x155 Reference Design, the resistor dividers are shared between the following modules: * * * * * Channel 0, 1, 2 and 15. Channel 3, 4 and 5. Channel 6, 7 and 8. Channel 9, 10 and 11. Channel 12, 13 and 14.
Figure 18 below outlines the termination component layout of the S/UNI-16x155 reference design optical modules. Placing the termination components on the solder side of the board after the pins reduces the effects of transmission line stubs and improves signal quality.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Figure 18: OC-3 Optical Transceiver Termination Layout
ODL Top View
49R9 49R9
via
0.1uF 220 330
VCC
TXDTXD+ 50 ohm transmission lines both equal length
GND
2 x 49.9 ohm termination after TXD+/- balls under the chip
The ODL power supplies are filtered as recommended by the manufacturer. The TX and RX supplies are filtered with a 1H series coiI, and a 0.1F ceramic cap. If the power supply is `noisy', greater than 100mVp-p, additional filtering may be required. The 3.3V supply for the optical modules is provided by a DATEL UNR3V5 8 Amp DC/DC converter to reduce the current load on the cPCI 3.3V rails. The S/UNI16x155 reference design will require 4.7A worst case and 3.2A nominal for the 16 optical module power supplies. 7.4 S/UNI BLOCK Sheet 3 Sheet three shows the optical module connections for channels 5, 6, 9, and 14. It also provides an extra optical module that is populated only in S/UNI-4x622 applications. An additional optical module is required as the S/UNI-4x622 channel 2 PECL transmit pins are shared with the S/UNI-16x155 channel 5 receive pins and the S/UNI-4x622 channel 2 receive pins are shared with the S/UNI-16x155 channel 6 transmit pins. Because the transmit and receive pins are not common signals on the two devices an extra optical module footprint was added and can be populated in S/UNI-4x622 applications. See Section 8 and application note PMC-2000539 for additional details on the S/UNI-4x622 assembly option of the S/UNI-16x155 reference design.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
7.5 S/UNI BLOCK Sheet 4 Sheet four shows the connections for the remaining optical channels 8, 10, 11, 12, 13 and 15. 7.6 SUNI_BLOCK, Sheet 5 7.6.1 UTOPIA/POS-PHY Level 3 Interface The PM5382 supports a 32 bit 104 MHz UTOPIA Level 3 interface while operating in ATM mode. During POS (Packet Over SONET) operation, the PM5382 provides a 32 bit 104 MHz POS-PHY Level 3 interface. In this reference design, output signals from the PM5382 are source terminated with a 33 ohm resistor. The series source terminations eliminate reflections from the high impedance, far end of the trace. No end terminations are used. All connections are made with short 50W traces. 7.6.2 APS Interface The APS interface on the S/UNI-16x155 allows two devices to exchange SONET/SDH path data streams. The transmit interface generates a SONET/SDH serial data stream with valid section and path overheads. The receive interface accepts a SONET/SDH serial data stream with valid section and path overheads ignoring all line overhead information. This allows performance monitoring and alarm generation to be done in a similar manner to the serial line side interfaces. The APS serial interface and the REFCLK input operate similarly to the optical interfaces, except that they run at 622.08MHz. The APECLV input controls the ECL levels for all of the APS pins. Figure 19, and Figure 20 outline the recommended termination configurations. For interfaces with trace lengths less than 4cm in length, no buffering is required as shown in Figure 19. These traces are double terminated at both source and sink, so the APREF resistor should be set to 1KW. For traces of longer length, running over a backplane for instance, an ECL buffer should be used to ensure proper signal levels at the APSI+/- inputs with minimum undershoot or overshoot. For these single ended terminations the APREF resistor should be set to 2KW. The S/UNI-16x155 reference design routes the APS outputs to the backplane connector and sources the APS inputs from the backplane. The terminations are single ended with an MC100LVEL17 differential receiver to drive the APSO+/signals.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
All APSO+/- and APSI+/- traces are routed using 50 ohm controlled impedance traces and each differential pair should be length matched. Figure 19: Double Ended APS Terminations
S/UNI APS Interface
APSO+
49.9W
50W Trace Impedance 0.1uF VCC
APSI-
APSO-
49.9W
R1 50W Trace Impedance APSI-
For VCC = 3.3V, R1 should be 19.2W. For VCC=5V R1 should be 63.4W.
Figure 20 Single Ended APS Terminations
S/UNI APS Interface
S/UNI APS Interface
APSO+
49.9W
50W Trace Impedance 0.1uF VCC
APSI+
49.9W APSO-
63.4W 50W Trace Impedance APSI-
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S/UNI APS Interface
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
7.7
S/UNI Block, Sheet 6
7.7.1 Microprocessor Interface The PM5382 supports an 8 bit microprocessor interface that can be accessed by either a local microprocessor, or a remote host processor. Access to the entire register set of the S/UNI-16x155 requires a 12 bit address range of 0x00000x11FF. A13 is used to select the test mode registers. Separate busses for address and data or a multiplexed address/data bus configuration may be used, as the device contains an internal address latch. When separate busses are used, the ALE (Address Latch Enable) pin should be tied high through a resistor. This reference design uses separate address and data busses that are driven by the PCI9054 cPCI bridge. The FPGA implements glue logic to generate proper control signals to interface to the PM5382 micro interface. More details regarding the cPCI controller may be found in Section 7.13.1, CPCI Interface Controller. 7.7.2 JTAG Interface The PM5382 also supports JTAG functionality for boundary scan. The JTAG functionality is not used in this reference design, but the JTAG pins are brought out to a header so that they can be accessed easily. When the JTAG pins are not used, the inputs should be tied high through a resistor. The TRSTB signal should be tied to the RSTB signal. 7.7.3 Receive Alarm Outputs The PM5382 provides one receive alarm output per channel. Each of these signals can be configured to indicate multiple alarm conditions. These alarm conditions are fully described in the S/UNI-16x155 Data Sheet. In this reference design, the 16 receive alarm signals are routed to the FPGA and their status can be read in register 0x2400, the S/UNI RALRM Register. 7.7.4 Clocks The PM5382 makes the recovered Receive Clock and outgoing Transmit Clock signals available for any one channel, as selected by Register 0x2200 - S/UNI Clock Control Register.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
In this reference design, the Recovered Clock (RCLK) signal is padded to a level of 1 Volt peak to peak into 50W, and is brought to the front panel for distribution to an external clocking card. All other signals are brought to test points. The TFPI pin is an input pin, and needs to be pulled low when not in use. 7.7.5 Section and Line Status DCC Signals The PM5382 provides access to both the Section data communications channel (DCC) signals as well as the Line DCC signals for all 16 channels. When configured for section DCC, the RDCC output is the extracted section DCC bytes, D1, D2, D3. The TDCC inputs can be used to insert section DCC bytes D1, D2, D3 into the data stream. In line DCC mode, RDCC outputs the line DCC bytes D4 to D12. Similarly, the TDCC inputs can be used to insert the line DCC bytes D4 to D12. These signals are not used in this reference design, but are brought out to a SAMTEC QSE matched impedance connector for optional external access. The TDCC pins should be pulled low when not in use.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
7.8
S/UNI Block, Sheet 7
7.8.1 Power Supply Filter and Regulator Sheet This sheet shows all power supply filtering and regulation components required for PM5382 operation. The PM5382 requires 4 different voltage sources for operation. * +3.3 Volt I/O Digital Power (VDD) +3.3V Digital I/O power is supplied via the cPCI bus interface. VDD is well decoupled to ground, VSS. +2.5 Volt Core Digital Power (VDDI) +2.5 Digital Core power is regulated from the +3.3 Volt supply provided by the cPCI bus interface. VDDI is well decoupled to ground. A National Semiconductor LP3965ES-2.5 fixed linear regulator is used to regulate the ~1.6 A of current required for the S/UNI-16x155 core supply. The regulator will use the PCB as a heatsink, allowing it remain at a safe operating temperature. This device was selected for its exceptionally low dropout voltage, and low thermal resistance. * +3.3 Volt Analog Power (AVD) +3.3 Volt Analog power is supplied via the cPCI interface. Digital and Analog 3.3V supplies are split as soon as power leaves the Hot Swap Controller and are routed separately. AVD is well decoupled to ground, and filtered with a combination of resistors and capacitors. +3.3 Volt Quiet Analog Power (QAVD) As little (no) current is drawn on this supply line, it is filtered passively. QAVD is decoupled to ground.
*
*
Analog circuitry responsible for clock and data recovery must be free of noise to ensure reliable operation. Less sensitive analog power pins are grouped together and filtered with a single 0.1 F capacitor. The more sensitive analog power pins of the S/UNI-16x155 are filtered using a low pass RC circuit. If there is a lot of power supply noise, >100mVp-p in the 3.3V rail, and a 5V supply is available, then a linear regulator approach is recommended.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
7.8.2 Passive RC Low Pass Power Supply Filter If there is no 5V supply available and the 3.3V supply is not very noisy (less than 100mVp-p at all frequencies), passively filtering the analog supply is acceptable. Several capacitors may be paralleled to achieve the filtering across the desired frequency band. The 10F capacitors should be X5R ceramics and not Tantalum. A 0.1F X5R or X7R is used for high frequency noise reduction. The reference design uses this passive filter method. The X5R type capacitors have excellent low and high frequency response as seen in the graph below. The lower the impedance is, the better the capacitor for filtering. The X5R capacitors are similar to X7R except the high temperature spec is +85C instead of 125C for the X7R. These X5R ceramics are available up to 10F at 6.3 Volts. Taiyo Yuden is a quality source for these passive devices. Figure 21: Tantalum & X5R Ceramic Cap Impedance vs. Frequency
100,000 10,000 1,000 Impedance ESR (ohms 100 10 1 0.1 0.01 0.001 0.1
10uF Tantalum 10uF X5R 0.1uF X5R
1
100 1,000 10,000 100,000 10 Frequency (kHz)
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Figure 22: Passive RC Power Supply Filtering
+3.3V Analog 4W7 Pin V4
10uF X5R
10uF X5R
0.1uF +3.3V Pins C3, AJ3, AG5, AG11, AG16, AG21, AK30, AA27, L27, B30, E21, E16, E11, E5, K5, T5, AA5. One cap as close as possible to each of these digital pins.
15W0 Pin P1 0.1uF (17 caps)
10uF X5R
0.1uF +2.5V Pins AG12, AG19, W27, AD27, N27, H27, E20, E13, G5, M5, AB5, AF5. One cap as close as possible to each of these digital pins.
15W0 Pin N2 0.1uF (12 caps)
10uF X5R
0.1uF
15W0 Pin P3
10uF X5R
0.1uF
Pin U1 0.1uF
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
7.8.3 Linear Regulator Filter Method If a 5V supply is available, and the 3.3V supply is noisy, (>100mVp-p), a low dropout linear regulator can be used to generate the analog supply. Further noise attenuation is achieved with a front end RC pre-filter (2.7 ohm + 10 F) and a high frequency 0.1F ceramic at the input to the regulator. A 10 F Tantalum is required at the output for regulator stability. Figure 23: Linear Regulator Analog Power Supply Filtering
2W7
+
5V
3.3V Regulator Linear Tech LT1129-3.3
0.1uF
Pin V4
+
10uF
10uF
0.1uF
Pin P1
0.1uF
Pin N2
0.1uF
Pin P3
0.1uF
Pin U1
0.1uF
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
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S/UNI-16X155 REFERENCE DESIGN
7.9
FPGA Block , Sheet 8 The FPGA supports a number of functions on the S/UNI-16x155 Reference Design. These include: * * * * ATM (UL3) or POS (PL3) system side loopback. Reset Logic. Clock mode selection. LED control for status monitoring.
As two full UL3/PL3 interfaces are implemented on the FPGA to allow for loopback, cell/packet processing, and transparent interfacing to the system side, the FPGA requires a very high number of I/Os. This reference design uses a Xilinx Virtex-E FPGA. The XCV200E-6BG352 provides up to 260 I/Os in a low power 1.8V and 3.3V 352 pin BGA package. This device supports UL3 and PL3 cores to reduce FPGA development time and simplify design. Table 1 below outlines the distribution of I/Os on the device. Table 1: FPGA Pin Assignment
Signal group S/UNI-16x155 UL./PL3 I/F SYS UL./PL3 I/F Host I/F On-board control Status LEDs No. of pins 42 TX, 42 RX. 84 Total. 42 TX, 42 RX. 84 Total. 44 I/O pins 2 I/O pins 2 I/O pins 1 I/O pins 16 I/O pins 8 I/O pins Function UTOPIA/POS-PHY Level 3 data bus + control signals UTOPIA/POS-PHY Level 3 data bus + control signals 16 data lines, 14 address lines, 14 chip select and control lines. Recovered Clock Multiplexer control Reference Clock Multiplexer control POS/ATM Select Alarm Signals Control 8 LED display on front panel
Additional `glue-logic' functions such as address decoding is implemented in the FPGA. All unused I/O pins are routed to test points. Figure 24 below shows a block diagram of the FPGA architecture used on the S/UNI-16x155 Reference Design.
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Figure 24: FPGA Block Diagram
SUNI_TDAT<31..0> SUNI_TMOD<1..0> SUNI_TSOC/TSOP SUNI_TCA/PTPA SUNI_TPRTY SUNI_TENB SUNI_TERR SUNI_TADR<3..0> SUNI_TSX SUNI_STPA SUNI_TFCLK LA<13..2> LD<15..0> SUNI_CSB WRB RDB SUNI_RSTB L_CLK L_INTB CPCI INTERFACE L_RSTB LOCAL SIGNALS L_WRB L_READYB L_ADSB S/UNI-16X155 uP I/F SIGNALS SUNI_RALRM<15..0> SYS_TDAT<31..0> SYS_TMOD<1..0> SYS_TSOC/TSOP SYS_TCA/PTPA SYS_TPRTY SYS_TENB SYS_TERR SYS_TADR<3..0> SYS_TSX SYS_STPA SYS_TFCLK SYS_TSYSCLK
Latch
Latch
LED<6..0> uP I/F & CNTL REGISTERS Loopback / Transparent Select POS OR ATM SELECT REFLCK SOURCE SELECT SUNI_POS_ATMB REF_SEL<1..0>
SUNI_RDAT<31..0> SUNI_RMOD<1..0> SUNI_RSOC/RSOP SUNI_RPRTY SUNI_RENB SUNI_RERR SUNI_REOP SUNI_RADR<3..0> SUNI_RSX SUNI_RFCLK
Latch Latch Latch
SYS_RDAT<31..0> SYS_RMOD<1..0> SYS_RSOC/RSOP SYS_RPRTY SYS_RENB SYS_RERR SYS_REOP SYS_RADR<3..0> SYS_RSX SYS_RFCLK SYS_RSYSCLK
7.9.1 Control Register Function The S/UNI-16x155 FPGA functionality is controlled via the S/UNI Control Register. The register functions are outlined below.
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Register 0x2000H: S/UNI Control Register Bit
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Type
R/W R/W
Function
RESET POS_ATMB Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused TXENA RXENA XPRNT_ENA LPBK_ENA
Default
0 0 X X X X X X X X X X 0 0 0 1
Bits 0 and 1 configure the loopback/transparent functionality of the FPGA. The following combinations are valid. * 0x01: LPBK_ENA. The receive bus (either UTOPIA or POS-PHY Level 3, depending on state of POS_ATMB bit) is looped back to the S/UNI-16x155 transmit interface. 0x10: XPRNT_ENA. The FPGA passes the RX and TX interfaces transparently to/from the backplane connector. 0x11: Loop and Pass. In this mode the Receive data will be looped back to the TX inputs and passed to the backplane connector. 0x00: Not used. Could be used to implement cell/packet generation or processing functionality as desired.
* * *
RXENA:
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RXENA is used to enable the receive UL3/PL3 interface. Setting this bit to a 1 enables the interface. TXENA: TXENA is used to enable the transmit UL3/PL3 interface. Setting this bit to a 1 enables the interface. POS_ATMB: The POS_ATMB bit is used to select the operating mode of the S/UNI-16x155. Setting this bit to a 1 selects POS mode for Packet transfer via the POS-PHY Level 3 interface. Setting this bit to a 0 selects ATM mode for ATM cell transfer via the UTOPIA Level 3 interface. RESET: Global soft reset. Setting this bit to a 1 resets the S/UNI-16x155. RESET does not clear automatically. When set, the device is held in reset. To clear the reset condition the user must clear the RESET bit.
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Register 0x2200H: S/UNI Clock Control Register Bit
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W
Type
R/W R/W
Function
REF_SEL1 REF_SEL0 Unused Unused Unused Unused Unused Unused Unused Unused SYRFSRC SYTFSRC SRFSRC STFSRC FRFSRC FTFSRC
Default
0 0 X X X X X X X X 0 0 0 0 0 1
FTFSRC: The FTFSRC bit selects the clock source for the FPGA UL3/PL3 S/UNI side transmit interface. Setting this bit to a 0 selects the FPGA_TFCLK1 source generated by the on board 100MHz oscillator. Setting this bit to a 1 selects the SYS_TFCLK source from the backplane connector. FRFSRC: The FRFSRC bit selects the clocks source for the FPGA UL3/PL3 S/UNI side receive interface. Setting this bit to a 0 selects the FPGA_RFCLK1 source generated by the on board 100MHz oscillator. Setting this bit to a 1 selects the SYS_RFCLK source from the backplane connector. STFSRC: The STFSRC bit selects the source of the SUNI_F_TFCLK output. This output can be routed via solder bridge SB2 to provide the SUNI_TFCLK input to the transmit UL3/PL3 interface on the PM5382. Setting this bit to a 0 selects the
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FPGA_TFCLK1 source generated by the on board 100MHz oscillator. Setting this bit to a 1 selects the SYS_RFCLK source from the backplane connector. SRFSRC: The SRFSRC bit selects the source of the SUNI_F_RFCLK output. This output can be routed via solder bridge SB3 to provide the SUNI_RFCLK input to the receive UL3/PL3 interface on the PM5382. Setting this bit to a 0 selects the FPGA_RFCLK1 source generated by the on board 100MHz oscillator. Setting this bit to a 1 selects the SYS_RFCLK source from the backplane connector. SYTFSRC: The SYTFSRC bit selects the clock source for the FPGA UL3/PL3 system side transmit interface. Setting this bit to a 0 selects the FPGA_TFCLK1 source generated by the on board 100MHz oscillator. Setting this bit to a 1 selects the SYS_TFCLK source from the backplane connector. SYRFSRC: The SYRFSRC bit selects the clocks source for the FPGA UL3/PL3 receive interfaces. Setting this bit to a 0 selects the FPGA_RFCLK1 source generated by the on board 100MHz oscillator. Setting this bit to a 1 selects the SYS_RFCLK source from the backplane connector.
REF_SEL<1..0>: The REF_SEL bits are used to select between three sources for the 77.76MHz reference clock input to the S/UNI-16x155. * * * 0x00: Reference clock source from backplane connector. 0x01: External clock source via SMB connector. 0x10: On board 77.76MHz PECL oscillator. This signal is also routed to the SYS_REF_OUT signal on the backplane connector.
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Register 0x2400H: S/UNI RALRM Register Bit
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type
R R R R R R R R R R R R R R R R
Function
RALRM15 RALRM14 RALRM13 RALRM12 RALRM11 RALRM10 RALRM9 RALRM8 RALRM7 RALRM6 RALRM5 RALRM4 RALRM3 RALRM2 RALRM1 RALRM0
Default
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The S/UNI RALRM register indicates the current value of the receive alarm signals associated with each channel on the S/UNI-16x155. If no alarms are active the RALRM signal will be low. RALRM is can be configured to go high if various conditions are present on the channel. Please refer to the S/UNI-16x155 datasheet PMC-2000495 for further information on RALRM function.
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Register 0x2600H: LED Register Bit
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type
R R R R R R R R R R R R/W R/W R/W R/W R/W
Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LED_REG4 LED_REG3 LED_REG2 LED_REG1 LED_REG0
Default
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The LED Register provides software control over the front panel LEDs on the S/UNI-16x155 Reference Design.
7.9.2 ATM Loop-back Logic In ATM Loop-back mode, the FPGA polls the PM5382 to determine which PHYs have cells ready for transfer. The PM5382 RX interface is polled by placing addresses on the RxAddr<3..0> lines and monitoring the response on RCA. Once a particular PHY has been determined to have a complete ATM cell in its RX FIFO, data is clocked out of PM5382, latched, and simultaneously clocked into the PM5382 TX FIFO. No TX FIFO flow control is performed, but would require logic similar to RX polling. (TX polling would be used to identify all PHYs capable of accepting at least one cell. Prior to the initiation of a transfer from the RX FIFO, the status of the TX
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FIFO would be verified. If the TX FIFO couldn't accept the RX cell, the RX logic would `skip' the `blocked' PHY and continue polling for the next available PHY. ) Once the transfer of cell data has been initiated, the FPGA will poll to determine if any other PHYs have cells ready for transfer. If another PHY is found to have a complete cell in its RX FIFO before the end of the current transfer, that cell will be transferred to the appropriate TX FIFO as soon as the current transfer is finished. If no other PHYs have complete cells ready, the FPGA will sequentially poll all PHYs until a complete cell is available. 7.9.3 POS Loopback Logic In POS Loop-back mode, the PM5382 initiates the transfers from the RX FIFO. The user can enable the receive side transfer by setting the RXENA bit in the S/UNI Control Register. Setting this bit will assert the RENB signal on the PM5382 PL3 interface. Transfers will begin with the PM5382 specifying the PHY for which the transfer is occurring. The FPGA will latch the PHY address, and clock it into the PM5382 TX interface one clock cycle later. The FPGA will subsequently latch each double word of packet data from the RX interface, and clock it into the PM5382 TX interface one clock cycle later. The user also has control over the state of the TX interface via the TXENA bit in the S/UNI Control Register. 7.9.4 ATM and POS Transparent When set to Transparent Mode in either ATM or POS mode, the FPGA latches the bus signals from the S/UNI-16x155 RX interface and system TX interface and clocks them out to the system RX interface and S/UNI-16x155 TX interface respectively, on the following clock cycle. 7.9.5 Processor Interface Logic * * performs address decoding, and provides chip select to S/UNI-16x155. handles local bus signals for PLX PCI bridge.
7.9.6 S/UNI-16x155 UL3/PL3 Interface Each output on the UL3/PL3 (transmit) interface is source terminated with a 33 W resistor. On the receive side, the signals are source terminated at the PM5382 and no end terminations are used since the trace lengths between the S/UNI16x155 and the Virtex device are relatively short.
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7.9.7 Status LEDs and Reset Circuit Sheet 8 also provides the status LEDs and the pushbutton reset circuit for the S/UNI-16x155 Reference Design. A single LED is wired to the DONE pin and will turn on after the FPGA is successfully configured. The remaining LEDs are software configurable via the LED_REG register in the FPGA. Bits 4 and 5 output the loopack or transparent functional state of the FPGA. Table 2 below outlines the function of the remaining LEDs. Table 2: LED Display Function Bit (D4)
Bit 3 Bit 2 Bit 1 Bit 0
Function
LED_REG<4> LED_REG<3> LED_REG<2> LED_REG<1>
Bit (D3)
Bit 7 Bit 6 Bit 5 Bit 4
Function
Done LED_REG<0> XPRNT_ENA LPBK_ENA
The pushbutton reset is provided via a MAX811 voltage monitor device that will assert a reset signal when the voltage supply is below 3.08V. The minimum reset pulse is 140ms. By logically ORing the RESET_PB signal with RSTOB (from the cPCI bus) and the RESET bit within the FPGA, the system reset signal (SUNI_RSTB) is generated. A 16x2 100mil header provides access to the microprocessor interface bus for debugging purposes. Matched impedance MICTOR connectors that have been used in past reference designs for access to the PL3 bus are not used in this design due to the constraints they put on routing and the excessive lead times of the parts themselves. No headers are provided on the board due to space contstraints, but if probing of the UL3/PL3 bus is required the user can pass all UL3/PL3 bus signals through the FPGA and probe the signals at the backplane connector (Transparent Mode). A small test jig could be built to interface to a logic analyzer if desired.
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7.10 FPGA Block, Sheet 9 7.10.1 System Side UL3/PL3 Interface Sheet 9 provides the remainder of the S/UNI UL3/PL3 interface signals and the system side UL3/PL3 interface. As on the S/UNI interface, all outputs are source terminated with 33 W resistors. 7.11 FPGA Block, Sheet 8 7.11.1 Configuration Circuit The S/UNI-16x155 Reference Design FPGA can be configured in 3 ways: * * * Via a One Time Programmable EPROM. Via an XCHECKER cable. Via the JTAG port.
Jumpers allow the user to select between EPROM configuration or configuration via the XCHECKER cable. By default the FPGA will download configuration information from the EPROM. To configure the device via the XCHECKER cable, install all jumpers on J4 and remove the EPROM. If the EPROM is installed and the configuration is downloaded via the XCHECKER cable, the downloaded configuration will be overwritten by the contents of the EPROM. The JTAG port is always active and takes priority over the other configuration modes, if used. 7.11.2 Power Supply Decoupling The Virtex family of devices are capable of operating at speeds well above 200MHz. With a number of I/Os switching simultaneously at high speeds, a stable power supply is essential to achieve good performance and signal quality. The XCV200E is part of the Virtex-E family of 0.18m devices which uses 3.3V for I/O and 1.8V for core power. On the S/UNI-16x155 reference design the 3.3V digital supply is provided by the cPCI interface and is well decoupled to ground. The 1.8V digital supply provided via a local linear regulator is also well decoupled to ground. Based on Xilinx recommendations, eight 10uF bulk capacitors are placed near each I/O bank to further decouple the device. Finally, four bulk 0.47uF capacitors are placed at the corners.
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7.12 FPGA Block, Sheet 9 7.12.1 100 MHz UL3/PL3 Clock Distribution A 100 MHz oscillator, 100 ppm, is used for the Utopia Level 3 and POS-PHY Level 3 interface. No series termination resistor is used between the oscillator output and the input to due to the extremely short trace length. A clock distribution driver is used to provide low skew clocks to the PM5382, the FPGA, and to the external HS3 connector. The PI49FCT3807D (the 110MHz rated FCT3807C would suffice) was selected as the clock driver as it provides up to 10 outputs with a maximum skew of 350 ps and can operate from a +3.3 Volt supply. The +3.3 Volt supply is bypassed with two capacitors to help reduce power supply glitches when all 10 outputs switch simultaneously at 100 MHz. Each output from the FCT3807 is source terminated through a 33 W resistor in order to match the impedance of the 50 W traces distributing the clock signal. Correct termination of the clock signals is especially important to ensure monotonic, glitch-free, clocking of the S/UNI device, the FPGA, and the external system. 7.12.2 100 MHz Clock Source Switching The clock architecture on the S/UNI-16x155 Reference Design has been developed to operate as either a clock master or a clock slave when connected to an external system. The 100MHz UL3/PL3 clock is distributed to the FPGA and the S/UNI device via solder bridges. By configuring the solder bridges to source the clock from the on board oscillator or from the FPGA, the board can operate as a clock master or clock slave. If the external system is the clock master, The FPGA routes the TFCLK and RFCLK signals from the backplane to the S/UNI-16x155, taking advantage of the built in Delay Lock Loop architecture to improve clock performance. 7.12.3 Reference Clock Oscillator and Selection Circuitry The PM5382 requires a 77.76 MHz Reference Clock from which to synthesize the line rate clock. One source for this clock is an on-board oscillator. Any jitter at the S/UNI-16X155 Reference Clock input may be seen at the TXD+/- data outputs and this translates into Optical output jitter. The 3.3V Connor Winfield EE14-541, 77.7600MHz Oscillator is specified at 10ps RMS output jitter and its PECL
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outputs have rise/fall times of 550ps. The Connor Winfield 5V EH13-541 is specified with much higher rise/fall times of 2.3ns max. No appreciable difference in intrinsic jitter results have been noted during testing of other reference designs using these oscillators. In order to minimize the effects of noise on the 3.3V power supply rail, the power to the 77.76 MHz oscillator is filtered by a passive RC network. The values of this RC network are selected to provide a significant amount of noise reduction, while keeping IR loss to a minimum. The 77.76 MHz Reference Clock used by the PM5382 is selected through a 4 Input, differential PECL multiplexer. This multiplexer selects between the following signals: * * 77.76 MHz signal from the on-board oscillator. 77.76 MHz external Reference Clock from front mounted coaxial input. The inverting input of the multiplexer is biased to the centre of logic switching voltage by the VBB output pin. 77.76 MHz external Reference Clock from the HS3 connector. The differential signal from the HS3 connector is terminated with a 100 ohm resistor across the differential inputs to the multiplexer.
*
The S/UNI Clock Control Register within the FPGA is used to control the selection of a Reference Clock. Power supply filtering has been applied to the PECL Differential Multiplexer used to select the REF_CLK signal, and to the PECL Driver used to buffer the SYS_REF_OUT signal. In situations where there is an excessive amount of noise on the 3.3V supply line (greater than 100 mV peak to peak), an alternative method of providing clean 3.3V power to the reference oscillator and PECL components should be considered. A low-dropout, three terminal regulator such as the LT1117 or LP3963 could be used to provide a noise-free 3.3 Volt power supply from the +5 volt rail. All of the REF_CLK signals are 50 ohm, differential, low-voltage PECL. 7.12.4 Recovered Clock The 77.76 MHz recovered data clock is provided to a front mounted coaxial connector. The source of the recovered clock is selected through the RSEL[1:0} bits in register 0x2400, the S/UNI Clock Control Register.
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The RCLK signal provided by the PM5382 is an LVCMOS-level signal with up to 8mA of drive current. By using a resistive pad at the output of the RCLK, the drive impedance can be changed to 50 ohm. The output signal level is decreased to a nominal level of 1 volt peak to peak.
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7.13 CPCI Interface Block, Sheet 12 7.13.1 CPCI Interface Controller The cPCI Host Processor Interface is based on the PCI 9054 device. This device is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Master Interface Controller, that provides flexible local bus configurations and Hot Swap capability. The PCI 9054 operates with a 32-bit non-multiplexed bus (C-mode) on the local bus side. All bus accesses are 32 bit, so the least significant bits of the address bus (LA<0..1>) should be permanently pulled low. The 9054 provides 16 or 8 bit access using LA<0..1>, if required. This feature will not be used on the reference design. A serial EEPROM is used for device configuration after a reset or upon power-up. This design uses the Fairchild Semiconductor 93CS66LEN (2K) serial EEPROM. Figure 25: Host Processor cPCI Interface
LA<31..2> LD<31..0> CONTROL LA<31..2> LD<31..0> CONTROL AD<31:0> C/BE<3:0> CONTROL
CPCI J1
LOCAL BUS
PLX 9054 PCI BRIDGE
RESET\
PCI BUS
EEPROM
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EECS EESK EEDI/O
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7.13.2 CPCI Bus Precharge Circuit A Linear Technology LT1117 adjustable regulator is used to provide the potential for precharging the cPCI data bus lines. A resistive divider is used to adjust the output of the voltage regulator to a nominal output of 1.78 Volts. The DL4148 diode will drop approximately 0.7 Volts, resulting in a precharge voltage near 1 Volt. Figure 26: cPCI Bus Precharge Circuit
1N4148 LT1117-ADJ
130
0.1uF
24 56
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7.14 CPCI Interface Block, Sheet 13 7.14.1 CPCI J1 Connector An AMP Z-PACK connector is used to provide a cPCI compliant J1 interface 7.14.2 ESD Strip An ESD strip in integrated into the PCB along the front edge. 7.15 cPCI Power_Block, Sheet 14 The standard cPCI interface system blocks will be used. These blocks perform the following functions: 7.15.1 Hot Swap Controller System Block The Hot Swap Controller is used to allow a board to be safely inserted or removed from a live cPCI slot. The Hot Swap controller on the Power Supply Board System Block is implemented using the Linear Technology LTC1643L-1 The Hot swap controller allows the supply voltages to be ramped up at a programmable rate. The hot swap controller also detects over-current and overvoltage conditions, and shuts down power to the board until those conditions are rectified. The LTC1643-1 ignores the +12V and -12V supplies when generating the /PWRGD signal. External N-channel MOSFETS are used to control the 3.3V and 5V supplies. When the 3.3V and 5V supplies are valid, /PWRGD is asserted.
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Figure 27: cPCI Hot Swap Controller
Q IRF7413 Q IRF7413 10 W 10 W V(I/O) CompactPCI Connector 100 W
+5V_PCI +3.3V_PCI
5V 5A 3.3V 7.6A
3Vin 3Vsense GATE 3Vout 5Vin 5Vsense 5Vout 12Vin VEEin ON# V(I/O) 12V 2k PWRGD# 0.1uF 0.1uF GND TIMER 0.01uF FAULT# 12Vout VEEout 12V 500mA -12V 100mA
+12V_PCI -12V_PCI BD_SELB
LT1643L
HEALTHYB GND
7.16 System Interface, Sheet 14 7.16.1 UTOPIA/POS-PHY Level 3 Interface The S/UNI-16X155-POS UTOPIA/POS-PHY L3 interface is connected to the drop side HS3 connector through switches as described in Section 7.10. The pin names shown below have the prefix "SYS_" added on the signal names of the schematic. The HS3 connector uses a PMC-Sierra, Inc. proprietary pin out for the UTOPIA Level 3 bus as shown in the following two tables
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Table 3: UL3/PL3 High Speed RX Interface Pin Name RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RDAT[16] RDAT[17] RDAT[18] RDAT[19] RDAT[20] RDAT[21] RDAT[22] RDAT[23] RDAT[24] RDAT[25] RDAT[26] RDAT[27] RDAT[28] RDAT[29] RDAT[30] RDAT[31] RPRTY RENB Type Output Pin No. B4 A4 E5 D5 C5 B5 A6 E6 D6 C6 B6 A6 E7 D7 C7 B7 A7 E8 D8 C8 B8 A9 E9 D9 C9 B9 A9 E10 D10 C10 B10 A10 A3 D1 Function UTOPIA: Receive Cell Data Bus For Utopia Level 3 this bus carries the ATM cell octets that are read from the receive FIFO POS-PHY: Receive Packet Data Bus For POS-PHY Level 3 this bus carries Packets that are read from the selected receive FIFO.
Output Input
Receive Bus Parity The receive parity signal indicates the parity of the RDAT bus. Receive Write Enable The RENB signal is an active low input which is used to initiate reads from the receive FIFO.
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Pin Name RCA RVAL
Type Output
Pin No. B3
Function UTOPIA: Receive Cell Available This signal indicates an available cell. POS-PHY: Receive Data Valid RAVL indicates signals RDAT, RSOP, REOP, RMOD, RPRTY and RERR are valid. This signal is not used in UTOPIA mode. UTOPIA: Receive Start of Cell This signal marks the start of cell on the RDAT bus. POS-PHY: Receive Start of Packet This signal marks the start of packet on the RDAT bus. POS-PHY: Receive Error This signal indicates that the current packet has been aborted. This signal is not used in Utopia ATM mode. POS-PHY: Receive End of Packet This signal marks the end of packet on the RDAT bus. This signal is not used in UTOPIA mode. POS-PHY: Receive Word Modulo Indicates number of bytes in the last RDAT bus transaction of a packet. This signal is not used in UTOPIA mode. UTOPIA: Rx PHY Address Allows selection of particular PHY on MPHY devices. Only RXADDR[0..3] are used on this board These signals are not used in POS-PHY mode. POS-PHY: Receive Start of Transfer RSX indicates when the in-band PHY port address is present on RDAT bus. This signal is not used in UTOPIA mode. 104 MHz Receive Bus Slave Clock Input Provided to the PM5382 RFCLK input via CMOS switches during RX Slave mode operation.
RSOC
Output
D4
RSOP RERR Output C4
REOP
Output
E4
RMOD[1] RMOD[0] RXADDR[0] RXADDR[1] RXADDR[2] RXADDR[3] RXADDR[4] RXADDR[5] RSX
Output
D3 C3 A2 B2 C2 D2 E2 A1 E3
Input
Output
RFCLK
Input
F1
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Pin Name RSYSCLK
Type Output
Pin No. C1
Function 104 MHz Receive Bus Master Clock Output Provided to the external system and timed to coincide with RFCLK signal to PM5382 during RX Master mode operation.
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PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Table 4: UL3/PL3 High Speed TX Interface Pin Name TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] TDAT[16] TDAT[17] TDAT[18] TDAT[19] TDAT[20] TDAT[21] TDAT[22] TDAT[23] TDAT[24] TDAT[25] TDAT[26] TDAT[27] TDAT[28] TDAT[29] TDAT[30] TDAT[31] TPRTY TENB Type Input Pin No. C4 B4 A4 E5 D5 C5 B5 A6 E6 D6 C6 B6 A6 E7 D7 C7 B7 A7 E8 D8 C8 B8 A9 E9 D9 C9 B9 A9 E10 D10 B10 A10 D4 C2 Function UTOPIA: Transmit Cell Data Bus This bus carries the ATM cell octets that are written to the selected transmit FIFO. POS-PHY: Transmit Packet Data Bus This data bus carries the POS packet octets that are written to the selected transmit FIFO.
Input Input
Transmit Bus Parity. The transmit parity signal indicates the parity of the TDAT bus. Transmit Write Enable. The TENB signal is an active low input which is used to initiate writes to the transmit FIFO
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Pin Name TCA
Type Output
Pin No. E3
Function UTOPIA: Transmit Cell Available This signal is used to indicate available cell FIFO space by the PHY port. POS-PHY: Polled Transmit Packet Available. This signal transitions to high when a programmable minimum number of free space is available in the transmit FIFO of the polled PHY. POS-PHY: Selected Transmit Packet Available This signal transitions to high when a programmable minimum number of free space is available in the transmit FIFO of the selected PHY. This signal is not used in UTOPIA mode. UTOPIA: Transmit Start of Cell The transmit start of cell signal marks the start of cell on the TDAT bus. POS-PHY: Transmit Start of Packet This signal indicates the first byte in a packet. POS-PHY: Transmit Error This signal indicates the current packet must be aborted. This signal is not used in UTOPIA mode. POS-PHY: Transmit End of Packet This signal marks the end of a packet on the TDAT bus. This signal is not used in UTOPIA mode. POS-PHY: Transmit Word Modulo This signal indicates the size of the current word. This signal is not used in UTOPIA mode.
PTPA
STPA
Output
D3
TSOC
Input
B3
TSOP TERR Input E4
TEOP
Input
C3
TMOD[1] TMOD[0]
Input
B2 A2
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Pin Name TXADDR[0] TXADDR[1] TXADDR[2] TXADDR[3] TXADDR[4] TXADDR[5]
Type Input
Pin No. E1 D1 C1 B1 A1 E2
Function UTOPIA: Tx PHY Address Allows selection of particular PHY on MPHY devices. Only TXADDR[0..3] are used on this board. POS-PHY: Allows selection of a particular PHY for polling. Only TXADDR[0..3] are used on this board. POS-PHY: Transmit Start of Transfer TSX indicates when the in-band PHY port address is present on TDAT bus. 104 MHz Transmit Bus Slave Clock Input Provided to the PM5382 TFCLK input via switches during TX Slave mode operation. 104 MHz Transmit Bus Master Clock Output Provided to the external system and timed to coincide with TFCLK signal to PM5382 during RX Master mode operation.
TSX TFCLK TSYSCLK
Input Input Output
A3 F10 C10
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55
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
7.16.2 APS and SYS_REF Interfaces The J12 HS3 connector supports the APS connections between boards as well as connections for SYS_REF clocks exchanged between boards. Table 5: APS and SYS_REF Interface, J12 Pin Name APSI0 APSI1 APSI2 APSI3 APSI4 APSI5 APSI6 APSI7 APSO0 APSO1 APSO2 APSO3 APSO4 APSO5 APSO6 APSO7 REF_INP REF_INN REF_OUTP REF_OUTN Type Input Pin No. C5 B5 C4 B4 C3 B3 C2 B2 E5 D5 E4 D4 E3 D3 E2 D2 B1 C1 D1 E1 APS Inputs Function
Output
APS Outputs
Input Output
77.76 MHz Reference Clock Input 77.76 MHz Reference Clock Output
The high frequency characteristics of the HS3 connector preserve the signal integrity of the 622 Mbps APS PECL signals.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
56
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
8
PCB CONSIDERATIONS This section discusses the implementation requirements for a four port OC-12c linecard using a S/UNI-4x622 on the S/UNI-16x155 reference design board. The S/UNI-4x622 and S/UNI-16x155 devices are pin compatible, and the majority of the pins are common to both devices. However, since one is a four port device, and the other is a 16 port device, there are a number of pins which are not shared and special care must be taken in board design to implement a combined design. The majority of pins which are not common between the two devices map to a no-connect on one or the other, simplifying the implementation. There are, however; a number of pins that require special attention in design and layout. The following sections outline the build options on applicable schematic sheets.
8.1 SUNI BLOCK, Sheet 2 Channel 0 S/UNI-16x155 Option: * * Assemble solder bridges SB6, SB7 and SB10. Install OC-3 ODL U23, power filter and termination components.
S/UNI-4x622 Option * * Assemble solder bridges SB11, SB13, SB16, SB19. Do not assemble U23, power filter or termination components.
Channel 1 S/UNI-16x155 Option: * * Install OC-3 ODL, filter and terminations. Do not install R73.
S/UNI-4x622 Option: * * Install OC-12 ODL. Replace R187 with a 64.3 W resistor. Do not install R188.
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57
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
* *
Install R73 if the OC-12 ODL uses a TTL SD pin rather than PECL. Ensure that the SDTTL pin is configured correctly.
Channel 2 S/UNI-16x155 Option: * * Assemble Solder Bridges SB5, SB8 and SB9. Install OC-3 optics, filter and termination components.
S/UNI-16x155 Option: * * * Assemble Solder Bridges SB12, SB15, SB17. Install 0.047uF cap C200. Do not assemble ODL, filter or termination components.
Channel 3 S/UNI-16x155 Option: * * * Assemble SB58 and SB59 Assemble ODL, filter and termination components. Do not install R199.
S/UNI-4x622 Option: * * * Assemble SB24 and SB25. Install R199 Do not assemble ODL, filter or termination components.
Channel 4 S/UNI-16x155 Option: * * Assemble SB14. Assemble ODL, filter and termination components.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
S/UNI-4x622 Option: * * Assemble SB18, SB20, and SB21. Do not assemble ODL, filter or termination components.
Channel 7 S/UNI-16x155 Option: * * * Install SB22. Assemble ODL, filter and termination components. Do not install C218.
S/UNI-4x622 Option: * * Install SB23 and C218. Do not assemble ODL, filter or termination components.
8.2 SUNI BLOCK, Sheet 3 Channel 6 S/UNI-16x155 Option: * * * Install SB26, SB27 and SB28. Install ODL circuitry Do not install R230 or R231.
S/UNI-4x622 Option: * * * Install SB29, SB30, SB31. Install R230, R231. Do not install ODL circuitry.
Channel 5 S/UNI-16x155 Option:
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59
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
* * *
Install SB60, SB61, SB62 Assemble ODL circuitry Do not install 4_TXD2 terminations.
S/UNI-4x622 Option: * * * * Assemble SB63. Install R248, R248, C252 and C253. Do not assemble ODL circuitry. Assemble U36 OC-12 optics module, filter and termination components. PECL (R213 pulldown) and TTL (R83 pullup) terminations are provided for the SD pin.
Channel 9 S/UNI-16x155 Option: * Install OC-3 ODL circuitry
S/UNI-4x622 Option: * * * * Assemble U34 with an OC-12 ODL. Assemble R218 with a 63.4W resistor. Do not install R219. PECL (R203 pulldown) and TTL (R82 pullup) terminations are provided for the SD pin. Ensure SDTTL is set correctly.
Channel 14 S/UNI-16x155 Option: * Install OC-3 ODL circuitry
S/UNI-4x622 Option: * * Assemble U37 with an OC-12 ODL. Assemble R245 with a 63.4W resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
60
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
* *
Do not install R246. PECL (R234 pulldown) and TTL (R89 pullup) terminations are provided for the SD pin. Ensure SDTTL is set correctly.
8.3 SUNI BLOCK, Sheet 4 Do not assemble J9. The add-on board is not required for a S/UNI-4x622 implementation. Channel 8 S/UNI-16x155 Option: * * Assemble SB34, SB37 and SB38. Assemble termination components
S/UNI-4x622 Option: * Assemble SB40, SB42, SB45, SB46.
Channel 10 S/UNI-16x155 Option: * * Assemble SB49, SB50, SB51. Install terminations.
S/UNI-4x622 Option: * * Assemble SB54, SB55, SB56 and C267. Do not install terminations.
Channel 11 and Channel 12 S/UNI-16x155 Option: * Assemble terminations.
S/UNI-4x622 Option: * Do not assemble terminations.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
Channel 13 S/UNI-16x155 Option: * * Install SB32, SB33, SB35. Install terminations
S/UNI-4x622 Option: * * Install SB36, SB39, SB41, SB43, SB44. Do not install terminations.
Channel 15 S/UNI-16x155 Option: * * Install SB47, SB48, SB64 Install terminations
S/UNI-4x622 Option: * Install SB52, SB53, SB57 and C265.
8.4 SUNI BLOCK, Sheet 6 DCC Signals S/UNI-16x155 Option: * Assemble pulldown resistors RN86, RN87, RN90, RN91.
S/UNI-4x622 Option. * * Do not assemble pulldown resistors RN86, RN87, RN90, RN91 Assemble SB65, SB66, SB67, SB68, SB69.
8.5 SUNI BLOCK, Sheet 7 Sheet 7 shows the power supply configuration for the S/UNI-16x155 reference design and provides filtering and decoupling for a S/UNI-16x155 or S/UNI-4x622 build option.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
62
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
S/UNI-16x155 Option: * * Assemble AVD0, AVD1, AVD2, and AVD7 filter circuits. Install decoupling capacitors listed in the schematics.
S/UNI-4x622 Option: * * In addition to the AVDx filter circuits, assemble the 4_CRU_AVD_x filter circuits and analog 3.3V decoupling capacitors. Install decoupling capacitors listed in the schematics.
8.6 General Design Notes Ensure that the critical 622 nets are well isolated from potentially long 155 traces. These include: * 4x622 Pins: RXD[2]+/-, TXD[2]+/-, C0[0,2,3], C1[0,2,3] TXREF[0,1]. All these pins map to controlled impedance 155Mbit traces on the 16x155 and care should be taken in layout to ensure the 622 traces are well isolated from the 155 traces to maintain good signal quality.
On the S/UNI-16x155 reference design, solder bridges have been added to connections for those pins that map to signal pins on the S/UNI-16x155 and power or ground pins on the S/UNI-4x622. Special care in layout is required to ensure that the 155Mbit differential PECL traces have a minimum of stub traces that can affect signal quality severely. Zero ohm resistors can be used in place of solder bridges. On the reference design, solder bridges are used so that two different solder masks can be created to implement either build option, reducing component count, simplifying the BOM, and reducing the complexity of the assembly process.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
63
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
9
SCHEMATICS REVISION 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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REVISIONS
ZONE REV DESCRIPTION DATE APPR
H PAGES 2 TO 7 SUNI_BLOCK PAGES 16 TO 17 OPTICS_CARD 11P SYS_APSO<7..0> SYS_APSI<7..0> PAGES 8 TO 11 FPGA SUNI_TDAT<31..0> SUNI_TSOC/TSOP SUNI_TCA/PTPA SUNI_TPRTY SUNI_TENB SUNI_TMOD<1..0> SUNI_TERR SUNI_TEOP SUNI_TADR<3..0> SUNI_TSX SUNI_STPA SUNI_TFCLK SUNI_TDAT<31..0> SUNI_TSOC/TSOP SUNI_TCA/PTPA SUNI_TPRTY SUNI_TENB SUNI_TMOD<1..0> SUNI_TERR SUNI_TEOP SUNI_TADR<3..0> SUNI_TSX SUNI_STPA SUNI_TFCLK 10P 8P PAGE 15 SYS_INTERFACE 9P
H
SYS_APSO<7..0> SYS_APSI<7..0>
SYS_APSO<7..0> SYS_APSI<7..0>
OPTICS MODULES 8 TO 15 ARE MOUNTED ON A DAUGHTER CARD WHICH MOUNTS ONTO THE MAIN BOARD. G THIS BOARD IS A SNAP OFF PART OF THE PCB.
SUNI_TDAT<31..0> SUNI_TSOC/TSOP SUNI_TCA/PTPA SUNI_TPRTY SUNI_TENB SUNI_TMOD<1..0> SUNI_TERR SUNI_TEOP SUNI_TADR<3..0> SUNI_TSX SUNI_STPA SUNI_TFCLK
SYS_TDAT<31..0> SYS_TSOC/TSOP SYS_TCA/PTPA SYS_TPRTY SYS_TENB SYS_TMOD<1..0> SYS_TERR SYS_TEOP SYS_TADR<3..0> SYS_TSX SYS_STPA SYS_TFCLK SYS_TSYSCLK SYS_RDAT<31..0> SYS_RSOC/RSOP SYS_RCA/RVAL SYS_RPRTY SYS_RENB SYS_RMOD<1..0> SYS_RERR SYS_REOP SYS_RADR<3..0> SYS_RSX SYS_RFCLK SYS_RSYSCLK
SYS_TDAT<31..0> SYS_TSOC/TSOP SYS_TCA/PTPA SYS_TPRTY SYS_TENB SYS_TMOD<1..0> SYS_TERR SYS_TEOP SYS_TADR<3..0> SYS_TSX SYS_STPA SYS_TFCLK SYS_TSYSCLK SYS_RDAT<31..0> SYS_RSOC/RSOP SYS_RCA/RVAL SYS_RPRTY SYS_RENB SYS_RMOD<1..0> SYS_RERR SYS_REOP SYS_RADR<3..0> SYS_RSX SYS_RFCLK SYS_RSYSCLK
SYS_TDAT<31..0> SYS_TSOC/TSOP SYS_TCA/PTPA SYS_TPRTY SYS_TENB SYS_TMOD<1..0> SYS_TERR SYS_TEOP SYS_TADR<3..0> SYS_TSX SYS_STPA SYS_TFCLK SYS_TSYSCLK SYS_RDAT<31..0> SYS_RSOC/RSOP SYS_RCA/RVAL SYS_RPRTY SYS_RENB SYS_RMOD<1..0> SYS_RERR SYS_REOP SYS_RADR<3..0> SYS_RSX SYS_RFCLK SYS_RSYSCLK
G
F
SUNI_RDAT<31..0> SUNI_RSOC/RSOP SUNI_RCA/RVAL SUNI_RPRTY SUNI_RENB SUNI_RMOD<1..0> SUNI_RERR SUNI_REOP SUNI_RADR<3..0> SUNI_RSX SUNI_RFCLK
SUNI_RDAT<31..0> SUNI_RSOC/RSOP SUNI_RCA/RVAL SUNI_RPRTY SUNI_RENB SUNI_RMOD<1..0> SUNI_RERR SUNI_REOP SUNI_RADR<3..0> SUNI_RSX SUNI_RFCLK
SUNI_RDAT<31..0> SUNI_RSOC/RSOP SUNI_RCA/RVAL SUNI_RPRTY SUNI_RENB SUNI_RMOD<1..0> SUNI_RERR SUNI_REOP SUNI_RADR<3..0> SUNI_RSX SUNI_RFCLK
F
E
SUNI_RCLK SUNI_REFCLKP SUNI_REFCLKN SUNI_POS_ATMB
SUNI_RCLK SUNI_REFCLKP SUNI_REFCLKN SUNI_POS_ATMB
SUNI_RCLK SUNI_REFCLKP SUNI_REFCLKN SUNI_POS_ATMB
SYS_REF_INP SYS_REF_INN SYS_REF_OUTP SYS_REF_OUTN
SYS_REF_INP SYS_REF_INN SYS_REF_OUTP SYS_REF_OUTN
SYS_REF_INP SYS_REF_INN SYS_REF_OUTP SYS_REF_OUTN
E
SUNI_RALRM<15..0>
SUNI_RALRM<15..0>
SUNI_RALRM<15..0> L_CLK L_INTB L_RSTOB L_USERO L_USERI L_WRB L_READYB L_ADSB LHOLDA LHOLD FPGA_CONFIG
SUNI_CSB RDB WRB SUNI_RSTB SUNI_INTB
LD<31..0>
LA<31..2>
PAGES 12 TO 13 CPCI_BLOCK LD<31..0> LA<31..2>
6P
D SUNI_CSB RDB WRB SUNI_RSTB SUNI_INTB LD<31..0> LA<31..2>
D
SUNI_CSB RDB WRB SUNI_RSTB SUNI_INTB LD<31..0> LA<31..2>
C FPGA_CONFIG LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK B PAGE 14 5P POWER_BLOCK FPGA_CONFIG LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK
C
B DRAWING: SUNI_16X155_R1_ROOT SUNI_16X155_R1_ROOT 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI Wed Oct 18 13:44:42 2000
5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-200-0506 DOCUMENT ISSUE NUMBER: 1 TITLE: SUNI 16X155 REFERENCE DESIGN ROOT DRAWING ENGINEER: BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:1 1 OF 17 A
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ZONE
3.3VA
100NH C187 0.1UF 10UF C180 C183 0.1UF
REV
DESCRIPTION
U9 SUNI16X155 PMC PART# 11 of 23
DATE
APPR
3.3VA
L15
C207
TXDP0
158 R158
0.1UF C195
0.1UF
0.1UF
10UF
H
C201 C204
U9 SUNI16X155 PMC PART# 12 of 23
D2
100NH L19
H
+
+
TXDP0/NC
TXDP1
158
0.1UF C216
G2
TXDP1/TXDP1
3.3VA R193
R176 0.1UF 49.9 100NH C208 0.1UF L20
49.9
R99
100NH C188 0.1UF L16
C213 220 330
VBB_0
C191 0.1UF
3.3VA VBB_1
R188
49.9
R100
6
2
NU
U25 TXDN0 RXDP0 RXDN0 SD0
R118 158 R160 SB6 2 1 12 SB10 1 2 12 SB SB7 SB 1 122 0.1UF C197 E2 F2 E1 G3
R74
U23 G
13 14 15 16 11 12
49.9
R177
6
2
R187
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R93 150 R96 150 150
TXDN0/AVD1 RXDP0/AVD3 RXDN0/AVD2 SD0/AVD4
LINE_SIDE_CH_0
13 14 15 16 11 12
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
G TXDN1
158 R194 0.1UF C217 G1 H1 H2 J5
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R172 150 R174 150 R179 150
TXDN1/TXDN1 RXDP1/RXDP1 RXDN1/RXDN1 SD1/SD1
LINE_SIDE_CH_1
RXDP1 RXDN1 SD1
CHASS1 CHASS2 VEET
7
SB
CHASS1 CHASS2 VEET
7
VEER
1
VEER
1
SB11 12 SB SB13 12 SB SB16 12 SB SB19 12 SB
3.3 V
4X622 OPTION DO NOT INSTALL OPTICS
4X622 OPTION: REPLACE WITH OC-12 OPTICS REPLACE R193, R194, C216, C217 REPLACE R187 WITH 63.4 OHMS DO NOT INSTALL R188 3.3 V
2
2
2
2
WITH 0 OHMS
1
1
1
1
F 3.3VA
100NH C185 0.1UF 0.1UF L13 10UF C179 C182
4_CRU_AVD_1
F
C211
TXDP2
158 R157
0.1UF C194
0.1UF
0.1UF
10UF
C203 C206
+
U9 SUNI16X155 PMC PART# 10 of 23
J2
100NH L23
SB25 2 12 SB
3.3VA
U9 SUNI16X155 PMC PART# 9 of 23 TXDP3/AVD8
+
TXDP2/C0[1]
TXDP3
158 R197
0.1UF C221
1 L2 49.9 R183
49.9
R97
100NH C186 0.1UF L14
C200
C212
0.1UF
E
0.047UF
100NH L24
VBB_1
C192 0.1UF
E VBB_1
C215 0.1UF
49.9
6
2
13 14 15 16 11 12
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
U32 TXDN2 RXDP2 1 RXDN2 SD2
R117 158 0.1UF C196 J1 K1 K2 K3
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R92 150 R95 150 150
TXDN2/C1[1] RXDP2/AVS7 RXDN2/AVD6 SD2/AVS6
LINE_SIDE_CH_2
CHASS1 CHASS2 VEET
7
SB8 SB5 12 2 12 SB SB SB9 1 12 SB
1
2 2
R159
13 14 15 16 11 12
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R175 150 R180 150 150
49.9
R184
6
2
U22
R98
TXDN3 RXDP3 RXDN3 SD3
R186 1
158
0.1UF C222
L3 M2 M1 M3
TXDN3/AVS8 RXDP3/TXREF1 RXDN3/TXREF0 SD3/NC LINE_SIDE_CH_3 D 4X622 OPTION: DO NOT ASSEMBLE OPTICS ASSEMBLE R199
2.00K
VEER
1
SB12 2 12 SB SB15 2 12 SB SB17 2 12 SB
VEET 3.3 V 4X622 OPTION DO NOT INSTALL OPTICS INSTALL C200
7
VEER
1
D
1
1
1
3.3 V
SB20 2 12 SB
10UF
100NH C209 0.1UF 0.1UF L21 C202 C205
SB23 2 12 SB
3.3VA 3.3VA
100NH C189 0.1UF L17 10UF C181 C184 0.1UF
1
SB24 2 12 SB
1 AF2
CHASS1 CHASS2
SB59R198 1 SB58 1 2 2 2 12 SB SB
R199
3.3 V
+
C
U9 SUNI16X155 PMC PART# 8 of 23 TXDP4/AVD20
U9 SUNI16X155 PMC PART# 5 of 23 TXDP7/AVD27 4X622 OPTION DO NOT ASSEMBLE OPTICS ASSEMBLE C218 C
+
TXDP7
158 R195
0.1UF C219
R163 R122 100NH C190 0.1UF L18
C198 C210 0.1UF L22
49.9
49.9
R181
TXDP4
158
0.1UF
1 Y2
100NH
VBB_2
C214 0.1UF
C193
0.1UF
U30
13 14 15 16 158 R164 0.1UF Y1
R123
49.9
U24 B
13 14 15 16 11 12
R173 150
R178 150
R101 150
R94 150
SB18 2 12 SB
SB21 2 12 SB
150
VEET
7
VEER
1
R124
SD TDIS
7
LINE_SIDE_CH_4
4X622 OPTION DO NOT INSTALL OPTICS
1
1
1
3 8
SD4
1
Y3
SD4/AVS20
C218
CHASS1 CHASS2
SB14 2 12 SB
150
VEET
VEER
R185
RXDP RXDN
0.047UF
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN
9 10 5 4
TXDN4 RXDP4 RXDN4
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8
49.9
R182
VBB_1
6 2
TXDN7 RXDP7 RXDN7 SD7
1
158
TXDN4/AVS22 RXDP4/NC RXDN4/NC
C199 AA2 AA3
11 12
CHASS1 CHASS2
0.1UF AG1 R196 C220 AH2 SB22 2 AG2 12 SB AG3
6
2
TXDN7/C2[0] RXDP7/NC RXDN7/C2[1] SD7/NC
LINE_SIDE_CH_7
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=SUNI_BLOCK ABBREV=SUNI_BLOCK LAST_MODIFIED=Thu Dec 14 10:38:16 2000 10 9 8 7 6 5 4 3 TITLE: S/UNI 16X155 REFERENCE DESIGN OPTICS INTERFACE ENGINEER: BDV 2 ISSUE DATE: A
REVISION NUMBER: 1.0 PAGE:2 1 OF 17
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H 4_RXDN2 3.3VA
100NH C231 0.1UF L27 10UF C224 C226 0.1UF
0 R230
H
4_RXDP2
0 R231
C246
TXDP6
158 R226
0.1UF C240
AD1
TXDP6/RXDN2
0.1UF
0.1UF
10UF
C242 C244
U9 SUNI16X155 PMC PART# 6 of 23
3.3VA
100NH L31
U9 SUNI16X155 PMC PART# 7 of 23 TXDP5
158 R249 0.1UF C254 AB1
+
+
TXDP5/NC
C232
0.1UF
C247
VBB_2
C236 0.1UF
0.1UF
G
L32
49.9
100NH
R236
L28
49.9
100NH
R209
G
VBB_2
C250 0.1UF
U35
13 14 15 16 11 12
49.9
R210
6
2
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R204 150 150
TXDN6 RXDP6 RXDN6 SD6
R206 150 R212 1
158 R227 SB27 1 2 SB26 1 2 2 12 SB SB SB28 1 2 12 SB
0.1UF AD2 C241 AE2 AE1 AE3
U8 TXDN6/RXDP2 RXDP6/AVS26 RXDN6/AVS25 SD6/AVD26
LINE_SIDE_CH_6
11 12 13 14 15 16
CHASS1 CHASS2 VEET
7
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R233 150 R235 150 150
49.9
R237
6
2
TXDN5 RXDP5 RXDN5 SD5
R239 1 1
158
0.1UF AB2 C255 AC2 AC1 AC3
TXDN5/NC RXDP5/TXDN2 RXDN5/TXDP2 SD5/AVS23
LINE_SIDE_CH_5
VEER
1
CHASS1 CHASS2 VEET
7
SB29 2 12 SB SB30 122 SB SB31 122 SB
F
3.3 V
1
1
3.3VA OC-12 OPTICS MODULE
10UF C227 C228 0.1UF
1
4X622 OPTION DO NOT ASSEMBLE OPTICS ASSEMBLE OC-12 OPTICS INSTALL R230 R231
VEER
1
SB63 122 SB
SB60 12 1 SB SB61 12 SB
R250 2SB62 2 12 SB 2
F 4X622 OPTION DO NOT ASSEMBLE OPTICS ASSEMBLE OC-12 OPTICS INSTALL R125 R142
100NH C233 0.1UF L29
4_TXDN2 4_TXDP2
0 R125 0 R142
E
+
100NH
1
E
C234 0.1UF L30
3.3VA
3.3VA
R83 100NH C248 0.1UF 0.1UF L33 10UF C243 C245
VCCRX VEERX SD RDP RDN
3 5 4 R213 150 R214 150 R217 150
+
U36
U9 SUNI16X155 PMC PART# 14 of 23 TXDP14 3.3VA
0.1UF 49.9 158 R251 0.1UF C256 A8
2
1
NU
4_SD2 4_RXDP2 4_RXDN2
6C3<
TXDP14/TXDP0
100NH C249 0.1UF L34
C251
D OPTICAL SIGNAL
220
R245
RX HFCT-5908E TX
TDP TDN TXDIS VCCTX VEETX
6 7 9 10 8
R240
D
3.3VA VBB_0
330 R246
3.3VA
13 14 15 16 11 12 R215 0.1UF 49.9
U37 GND GND GND GND
VCCT VCCR 3.3V HFBR5905
C237
63.4
R222
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R234 150 R238 150 R242 150
49.9
R241
4_TXDP2
10K R89 6 2
TXDN14 RXDP14 RXDN14 SD14
158 R252
0.1UF C257
B8 B7 A7 C7
TXDN14/TXDN0 RXDP14/RXDP0 RXDN14/RXDN0 SD14/SD0
LINE_SIDE_CH_14
CHASS1 CHASS2 VEET VEER
1
C
49.9
R216
C 4X622 OPTION REPLACE WITH OC-12 OPTICS REPLACE C256, C257, R251, R252 WITH 0 OHM REPLACE R245 WITH 63.4 OHM DO NOT INSTALL R246
3.3VA
100NH C229 0.1UF 0.1UF L25 10UF C223 C225
4_TXDN2 U9 SUNI16X155 PMC PART# 3 of 23 TXDP9 3.3VA
0.1UF 49.9 100NH C230 0.1UF L26 R207 158 R224 0.1UF C238 AK7
+
TXDP9/TXDP3
C235
220
R218
7
B
B
3.3VA
VBB_2
330 R219
13 14 15 16 11 12
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R203 150 R205 150 R211 150
NU
U34
49.9
R208
R82
6
2
TXDN9 RXDP9 RXDN9 SD9
158 R225
0.1UF AL7 C239 AL8 AK8 AJ8
TXDN9/TXDN3 RXDP9/RXDP3 RXDN9/RXDN3 SD9/SD3
LINE_SIDE_CH_9
CHASS1 CHASS2 VEET
7
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=SUNI_BLOCK ABBREV=SUNI_BLOCK LAST_MODIFIED=Thu Dec 14 10:38:22 2000 5 4 3 TITLE: S/UNI 16X155 REFERENCE DESIGN OPTICS BLOCK ENGINEER: BDV 2 ISSUE DATE: A
VEER
1
A
4X622 OPTION REPLACE WITH OC-12 OPTICS REPLACE R224, R225, C238, C239 WITH 0 OHM REPLACE R218 WITH 63.4 OHM DO NOT INSTALL R219
REVISION NUMBER: 1.0 PAGE:3 1 OF 17
10
9
8
7
6
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H U9 SUNI16X155 PMC PART# 4 of 23
158 R258 0.1UF C260 AK4
H U9 SUNI16X155 PMC PART# 2 of 23
158 R270 0.1UF C263 AK9
U9 SUNI16X155 PMC PART# 1 of 23
158 R277 0.1UF AJ11 C268
U9 SUNI16X155 PMC PART# 16 of 23
158 R279 0.1UF C270 B12
TXDP8/NC
TXDP10/C3[0]
TXDP11/NC
TXDP12/NC
4X622 OPTION DO NOT INSTALL AC COUPLING AND SERIES TERMINATIONS
0.047UF
C267
G
G
158
0.1UF AK5 C261 AK6 AL5 AJ6
TXDN8/AVS29 RXDP8/AVD31 RXDN8/AVS28 SD8/AVD30
LINE_SIDE_CH_8
1
158
0.1UF AL9 C266 AL10 AK10 AJ10
158
TXDN10/C3[1] RXDP10/AVS36 RXDN10/AVS34 SD10/AVD35
LINE_SIDE_CH_10
0.1UF AK11 C269 AK12 AL12 AJ12
TXDN11/NC RXDP11/NC RXDN11/NC SD11/NC
LINE_SIDE_CH_11
158 R280
0.1UF A12 C271 C11 B11 C12
TXDN12/NC RXDP12/NC RXDN12/NC SD12/NC
LINE_SIDE_CH_12
1
SB37R259 1 2 12 SB34 2 SB 12 SB38 1 2 SB 12 SB
3.3 V
SB40 122 SB SB42 2 12 SB SB45 2 12 SB SB46 2 12 SB
SB50 1 2 SB49 1 2 1 2 2 SB SB51 SB 1 2 12 SB
R272
R278
3.3 V
SB54 2 12 SB SB55 2 12 SB SB56 2 12 SB
F
1 1 1 1
4X622 OPTION INSTALL C267
F
1
1
J9 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 GND1 GND2 GND3 GND4
HISPD_HEADER20X2
E
D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
SUNI_TXDP8 SUNI_RXDP8 SUNI_TXDN8 SUNI_RXDN8 SUNI_TXDP10 SUNI_SD8 SUNI_TXDN10 SUNI_RXDP10 SUNI_SD10 SUNI_RXDN10 SUNI_TXDP11 SUNI_RXDP11 SUNI_TXDN11 SUNI_RXDN11 SUNI_TXDP12 SUNI_SD11 SUNI_TXDN12 SUNI_RXDP12 SUNI_SD12 SUNI_RXDN12 SUNI_TXDP13 SUNI_RXDP13 SUNI_TXDN13 SUNI_RXDN13 SUNI_TXDP15 SUNI_SD13 SUNI_TXDN15 SUNI_RXDP15 SUNI_SD15 SUNI_RXDN15 3.3VA
1
E
D
3.3 V
7C8>
4_CRU_AVD_0
SB43 2 12 SB SB57 2 12 SB
1
C
U9 SUNI16X155 PMC PART# 15 of 23 TXDP13/AVD37
158 R268 C262
U9 SUNI16X155 PMC PART# 13 of 23 TXDP15/AVD42
1
158 R255
0.1UF C258
A10
0.1UF
C
B6
158
B
0.1UF B10 B9 A9 C9
TXDN13/AVS37 RXDP13/AVD40 RXDN13/AVD39 SD13/AVS40
LINE_SIDE_CH_13
1 1
158
0.1UF C264
A5 B4 B5 C5
TXDN15/C0[0] RXDP15/AVS45 RXDN15/C1[0] SD15/AVD44
LINE_SIDE_CH_15
1
R256 1 SB35 C259 2 SB33 1 2 1 122 SB SB32 SB 2 12 SB 2 2 2 2
SB47 2 12 SB64 SB 1 1 2 2 SB48 SB 2 12 SB SB52 2 12 SB
R271
B
SB36 12 SB SB39 12 SB41 SB 12 SB SB44 12 SB
3.3 V
SB53 2 12 SB
3.3 V
0.047UF
1
1
1
1
1
1
C265
4X622 OPTION INSTALL C265
PMC-Sierra, Inc.
A DRAWING TITLE=SUNI_BLOCK ABBREV=SUNI_BLOCK LAST_MODIFIED=Thu Dec 14 10:38:26 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI 16X155 REFERENCE DESIGN OPTICS BLOCK MEZZANINE INTERFACE ENGINEER: BDV 2 ISSUE DATE: A
REVISION NUMBER: 1.0 PAGE:4 1 OF 17
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
U9 SUNI16X155 PMC PART# 18 of 23 TDAT31 TDAT30 TDAT29 TDAT28 TDAT27 TDAT26 TDAT25 TDAT24 TDAT23 TDAT22 TDAT21 TDAT20 TDAT19 TDAT18 TDAT17 TDAT16 TDAT15 TDAT14 TDAT13 TDAT12 TDAT11 TDAT10 TDAT9 TDAT8 TDAT7 TDAT6 TDAT5 TDAT4 TDAT3 TDAT2 TDAT1 TDAT0 TPRTY TMOD1 TMOD0 TSOC/TSOP TEOP TSX TERR TADR3 TADR2 TADR1 TADR0 SPTA TCA/DTPA TENB TFCLK RDAT31 RDAT30 RDAT29 RDAT28 RDAT27 RDAT26 RDAT25 RDAT24 RDAT23 RDAT22 RDAT21 RDAT20 RDAT19 RDAT18 RDAT17 RDAT16 RDAT15 RDAT14 RDAT13 RDAT12 RDAT11 RDAT10 RDAT9 RDAT8 RDAT7 RDAT6 RDAT5 RDAT4 RDAT3 RDAT2 RDAT1 RDAT0 RPRTY RMOD1 RMOD0 RSOC/RSOP REOP RSX RERR RADR3 RADR2 RADR1 RADR0 RCA/RVAL B RENB RFCLK POS_ATMB
SYSTEM_SIDE_UTOPIA_POS
G
F
D27 D30 E28 E29 E30 E31 F27 F28 F29 F30 G27 G28 G29 G30 G31 H28 H29 H30 H31 J27 J28 J29 J30 J31 K27 K28 K29 K30 K31 L28 L29 L30 M27 N31 N30 M30 M31 M29 M28 P28 P29 P30 P31 N28 N29 P27 R27 R28 R29 R30 R31 U31 U30 U29 U28 U27 V31 V30 V29 V28 V27 W31 W30 W29 W28 Y31 Y30 Y29 Y28 Y27 AA30 AA29 AA28 AB31 AB30 AB29 AB28 AB27 AC31 AC30 AD30 AD29 AC28 AC29 AD31 AC27
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0
SUNI_TDAT<31..0>\I
8G9> 9E3>
G
SYS_APSI<7..0>\I APSI3 APSI2 APSI1 APSI0 P/N P/N P/N P/N = = = = <7..6> <5..4> <3..2> <1..0>
0.1UF C155
15H5>
3.3 V
0.1UF
3.3 V
0.1UF
3.3 V
0.1UF
3.3 V
R103
R106
R109
C156
C157
63.4
63.4
63.4
C158
63.4
R113
PLACE TERMINATION/BIASING RESISTORS CLOSE TO U31
F
R102
R104
R105
R107
R108
R110
R111
49.9
49.9
49.9
49.9
49.9
49.9
49.9
7
A20 B20 A19 B19 A18 B18 A17 B17
SUNI16X155 PMC PART# 19 of 23 APSOP3 APSIP3 APSIN3 APSIP2 APSIN2 APSIP1 APSIN1 APSIP0 APSIN0 APSON3 APSOP2 APSON2 APSOP1 APSON1 APSOP0 APSON0 APECLV APSREF1 APSREF0 APS_SERIAL_DATA
49.9
R119
U9
AK20 AL20
2 3 4 5
D0P D0N D1P D1N D2P D2N D3P D3N VBB VEE
U31 Q0P Q0N Q1P Q1N Q2P Q2N Q3P Q3N VCC1 VCC2
19 18 17 16 15 14 13 12 1 20
7 6 5 4 3 2 1 0
SYS_APSO<7..0>\I
15E5<
SUNI_TPRTY\I SUNI_TMOD<1..0>\I SUNI_TSOC/TSOP\I SUNI_TEOP\I SUNI_TSX\I SUNI_TERR\I SUNI_TADR<3..0>\I
8E9> 8E9> 8F9> 8G9> 8E9> 8F9> 8F9> 8F9>
6 5 4 3 2 1 0
AK19 AL19 AK18 AL18 AK17 AL17 4.7K R130 AH18 2.00K AH17 R129 AJ18 6 7 8 9 10 11
E
3 2 1 0
7 150 R126 5 6
150 R132
E
RN83 RN84
4 1
5 8
33 33
SUNI_STPA\I SUNI_TCA/PTPA\I SUNI_TENB\I SUNI_TFCLK\I SUNI_RDAT<31..0>\I
MC100LVEL17DW
8F9< 8F9> 8F9> 11C3> 8F9<
3.3 V 3.3 V
0.1UF 150 R127 4
150 R133
D
C
RN724 RN731 RN732 RN733 RN734 RN741 RN742 RN743 RN744 RN761 RN762 RN763 RN764 RN771 RN772 RN773 RN774 RN781 RN782 RN783 RN784 RN791 RN792 RN793 RN794 RN801 RN802 RN803 RN804 RN811 RN812 RN813 RN814 RN821 RN822 RN823 RN824 RN831 RN832
5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
3 2 1 0 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C82
3 150 R128 1 150 0 2
150 R134
150 R135
100 OHM INTERNAL TERMINATION PROVIDED BY S/UNI CHIP
R131
D
C
SUNI_RPRTY\I SUNI_RMOD<1..0>\I SUNI_RSOC/RSOP\I SUNI_REOP\I SUNI_RSX\I SUNI_RERR\I SUNI_RADR<3..0>\I
8C9< 8C9< 8D9< 8D9< 8D9< 8C9< 8D9>
AE30 AE29 AE28 AE27 AD28RN833 AE31 AF30 AJ20
6
33
SUNI_RCA/RVAL\I SUNI_RENB\I SUNI_RFCLK\I SUNI_POS_ATMB\I
8D9< 8C9> 11C3> 8D3>
B
DRAWING TITLE=SUNI_BLOCK ABBREV=SUNI_BLOCK LAST_MODIFIED=Thu Dec 14 10:38:31 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI 16X155 REFERENCE DESIGN S/UNI UTOPIA AND APS INTERFACES ENGINEER: 10 9 8 7 6 5 4 3 BDV GR 2 ISSUE DATE: A
REVISION NUMBER: 1 PAGE:5 1 OF 17
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
4X622 OPTION DO NOT INSTALL RN?-RN? INSTALL R?--R? U9
9E3< 8C3<
3.3 V
1
4.7K RN86
SB68 2 12 SB SB69 2 12 SB
15 15 14 13 12 11 10 9 8 7 6 5 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
4.7K RN87
1 C21 D21 B21 D19 D20 14
SUNI_RALRM<15..0>\I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D12 D13 C13 B13 A13 E14 D14 C14 B14 A14 E15 D15 C15 B15 A15 D17
G
SUNI16X155 PMC PART# 21 of 23 RALRM15 RCLK RALRM14 RFPO RALRM13 TCLK RALRM12 TFPI RALRM11 TFPO RALRM10 RALRM9 RALRM8 RALRM7 RALRM6 RALRM5 RALRM4 RALRM3 RALRM2 RALRM1 RALRM0 CLOCKS_ALARMS
SUNI_RCLK\I
1
11F9<
4.7K RN90
TP27
G
RDCC<15..0>
1
4.7K RN91
SB65 2 12 SB
3 2 1 0
TP28
15
1
1
TP29
J14
1
TP30
J13 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 GND1 GND2 GND3 GND4
HISPD_HEADER20X2
TDCC<15..0>
1 0 2 1 3 2 4 3 5 4 6 5 15 7 6 14 8 7 13 9 8 12 10 9 11 11 10 10 12 9 11 13 8 12 14 7 13 15 6 14 16 5 15 17 4 18 3 19 2 20 1 21 0 22 RDCLK<15..0> 23 15 24 14 25 13 0 26 1 12 27 2 11 28 10 3 29 9 4 30 8 5 31 6 7 32 6 7 33 5 8 34 9 4 35 10 3 36 11 2 37 12 1 38 13 0 39 14 40 15 41 42 43 44
4.7K
F
U9 SUNI16X155 PMC PART# 22 of 23 RDCC15/AVS9 TDCC15/AVD21 RDCC14/NC TDCC14/AVS21 RDCC13/NC RDCC12/NC TDCC13/NC RDCC11/NC TDCC12/NC RDCC10/NC TDCC11/NC RDCC9/NC TDCC10/NC TDCC9/NC RDCC8/NC TDCC8/NC RDCC7/RACC3 TDCC7/TACC3 RDCC6/RACC2 TDCC6/TACC2 RDCC5/RACC1 TDCC5/TACC1 RDCC4/RACC0 TDCC4/TACC0 RDCC3 RDCC2 TDCC3 RDCC1 TDCC2 RDCC0 TDCC1 TDCC0 RDCLK15/AVD9 TDCLK15/NC RDCLK14/NC RDCLK13/NC TDCLK14/AVD19 TDCLK13/NC RDCLK12/NC TDCLK12/NC RDCLK11/NC TDCLK11/NC RDCLK10/NC TDCLK10/NC RDCLK9/NC TDCLK9/NC RDCLK8/NC TDCLK8/NC RDCLK7/RACLK3 RDCLK6/RACLK2 TDCLK7/TACLK3 RDCLK5/RACLK1 TDCLK6/TACLK2 RDCLK4/RACLK0 TDCLK5/TACLK1 RDCLK3 TDCLK4/TACLK0 TDCLK3 RDCLK2 TDCLK2 RDCLK1 TDCLK1 RDCLK0 TDCLK0
E
N3 AH12 AK13 AL14 AH15 AL15 AJ21 AL23 AG22 AJ24 AH24 AG25 AJ26 AH27 AG28 AF29 N4 AH13 AJ13 AK14 AJ15 AH19 AH21 AH22 AK23 AK24 AL25 AK26 AL27 AK28 AH30 AG31
W3 W4 AG14 AH14 AG15 AH20 AK21 AK22 AH23 AL24 AK25 AJ25 AK27 AG26 AF27 AG30 M4 Y4 AL13 AJ14 AK15 AG20 AL22 AJ22 AJ23 AG23 AG24 AH25 AH26 AJ27 AG29 AF28
LD<31..0>\I U9 SUNI16X155 PMC PART# 20 of 23 A13/NC A12/NC A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 ALE A0 CSB WRB RDB TDO TDI RSTB INTB TMS TCK TRSTB D7 D6 D5 D4 D3 D2 D1 D0 MICRO_JTAG LA<31..2>\I
D24 E24 A25 B25 C25 D25 B26 C26 D26 E26 A27 B27 C27 B28 C19 E19 C20 D18 C17 4.7K R136 15 14 13 12 11 10 9 8 7 6 5 4 3 2
8G4<>
12H4<> 8F3<
12D4>
RN85 4.7K
4.7K
R143
7 6 5 4 3 2 1 0
B22 C22 D22 E22 A23 B23 C23 D23
3.3 V
3.3 V
1
TP21
1 2 3 4 5 6 7 8 15 9 14 10 13 11 12 12 11 13 10 14 9 15 8 16 7 17 6 18 5 19 4 20 3 21 2 22 1 23 0 24 TDCLK<15..0> 25 15 0 26 14 1 27 13 2 28 12 3 29 11 4 30 10 5 31 9 6 32 8 7 33 8 7 34 9 6 35 10 5 36 11 4 37 12 3 38 13 2 39 14 1 40 0 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 41 42 43 44
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 GND1 GND2 GND3 GND4
HISPD_HEADER20X2
F
R51
E
8 7 6 5
1
1 2 3 4
D
A24 C24 E23 B24 C18 A22
TP22
SECTION_LINE_STATUS
3.3 V
15 1
D
1
TP23
3.3 V
1
1
TP24
SB66 2 12 SB
SB67 2 12 SB
14
1
TP26
3.3 V SUNI_RSTB\I
8D3>
3.3 V
R144
8D3< 8F3> 8E3> 8F3>
4.7K
SUNI_INTB\I RDB\I WRB\I SUNI_CSB\I
R283
C
U9 SUNI16X155 PMC PART# 17 of 23 NC/SD2 REFCLKP REFCLKN SDTTL SPECLV
SERIAL_LINE_SIDE_INTERFACE
C 3.3V PECL I/O
NU
AC5 V2 V1 AJ17 AJ19
4_SD2 SUNI_REFCLKP\I SUNI_REFCLKN\I
3D7> 11G3> 11G3>
4.7K
R284
PECL SIGNAL DETECT B
NU
R145
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=SUNI_BLOCK ABBREV=SUNI_BLOCK LAST_MODIFIED=Thu Dec 14 10:38:36 2000 10 9 8 7 6 5 4 3 TITLE: S/UNI 16X155 REFERENCE DESIGN S/UNI ALARM, COMMS & HOST CONTROL ENGINEER: BDV GR 2 ISSUE DATE: A
REVISION NUMBER: 1 PAGE:6 1 OF 17
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H OPTIONAL LINEAR REGULATOR FOR SENSITIVE +3.3 VOLT POWER PINS
5V
H PLACE TANT CAPACITORS NEAR REGULATOR BODY 3.3 V
2 4.7K 10UF C161 C162 2 0.1UF 10UF C272 R151 1
U27
10 0.1UF R137 10UF C159 5 C160 4
0.1UF
C279 0.1UF
C280 0.1UF
C281 0.1UF
0.1UF
0.1UF
C94 0.1UF
0.1UF
C100 0.1UF
0.1UF
C106 0.1UF
C282
C283
C103
C109
GND TAB/ GND
C277
+
6
10UF
SHDN
SENSE
C112
1
REG_3V +
5
C97
0.1UF
3.3V LT1129CQ VIN VOUT
PLACE CAPACITORS NEAR REGULATOR BODY
CONNECT 'SENSE' LEAD AT S/UNI CHIP
LP3966ES-2.5 VOUT VIN SENSE SD GND TAB
3 4
U9 SUNI16X155 PMC PART# 23 of 23 VDDI23/NC VSS55 VDDI21 VDDI20/NC VSS54 VDDI19/NC VSS53 VSS52 VDDI18 VDDI17/NC VSS51 VSS50 VDDI16/NC VDDI15/NC VSS49 VDDI14 VSS48 VDDI13 VSS47 VDDI12 VSS46 VDDI11 VSS45 VDDI10 VSS44 VDDI9 VSS43 VDDI8 VSS42 VDDI7 VSS41 VDDI6 VSS40 VDDI5 VSS39 VSS38 VDDI4 VSS37 VDDI3 VSS36 VDDI2 VSS35 VDDI1 VSS34 VDDI0 VSS33 VSS32 VDD47 VSS31 VSS30 VDD46 VDD45 VSS29 VDD44 VSS28 VDD43 VSS27 VDD42 VSS26 VDD41 VSS25 VDD40 VSS24 VDD39 VSS23 VDD38 VSS22 VDD37 VSS21 VDD36 VSS20 VDD35 VSS19 VDD34 VSS18 VDD33 VSS17 VDD32 VSS16 VDD31 VSS15 VDD30 VSS14 VDD29 VSS13 VSS12 VDD28 VDD27 VSS11 VSS10 VDD26 VDD25 VSS9 VSS8 VDD24 VSS7 VDD23 VDD22 VSS6 VDD21 VSS5 VDD20 VSS4 VDD19 VSS3 VDD18 VSS2 VDD17 VSS1 VSS0 VDD16 VDD15 NC/QAVS2 VDD14 NC/QAVS1 QAVS0 VDD13 NC/AVS44 VDD12 NC/AVS43 VDD11 NC/AVS42 VDD10 NC/AVS41 VDD9 NC/AVS39 VDD8 NC/AVS38 VDD7 VDD6 NC/AVS35 NC/AVS33 VDD5 NC/AVS32 VDD4 VDD3 NC/AVS31 NC/AVS30 VDD2 NC/AVS27 VDD1 NC/AVS24 VDD0 NC/AVS19 AVS8 NC/QAVD2 AVS7 NC/QAVD1 QAVD0 AVS6 AVS5 NC/AVD45 AVS4 AVS3 NC/AVD43 NC/AVD41 AVS2 NC/AVD38 AVS1 NC/AVD36 AVS0 NC/AVD34 NC/AVS5 NC/AVD33 NC/AVS4 NC/AVD32 NC/AVS3 NC/AVD29 NC/AVS2 NC/AVD28 NC/AVS1 NC/AVD25 NC/AVS0 ATP1 NC/AVD24 ATP0 NC/AVD23 NC/AVD22 AVD8 AVD7 AVD6 AVD5 AVD4 AVD3 AVD2 AVD1 AVD0 NC/AVD7 NC/AVD5 NC/AVD0 POWER
10 R138
U33
PLACE DECOUPLING CAPACITORS NEAR THE DIGITAL POWER PINS G
10 R139
5V
16X155 OPTION: AG12, AG19, W27, AD27, N27, H27, E20, E13, G5, M5, AB5, AF5 4X622 OPTION: AG12, AG19, W27, N27, H27, E20, E13 3.3 V
U26
4 5 3 0.1UF C163 C164 0.1UF
10 R140
VCC5 VCC3
RST
1
VCCA GND LTC1728ES5-5
2
PLACE DECOUPLING CAPACITORS NEAR THE DIGITAL POWER PINS 16X155 OPTION: C3, AJ3, AG5, AG11, AG16, AG21, AK30, AA27, L27, B30, E21, E16, E11, E5, K5, T5, AA5 4X622 OPTION: C3, AJ3, AG11, AG16, AG21, AK30, AA27, L27, B30, E21, E16, E11 3.3 V
AB5 AE5 AF5 AG9 E7 E9 G5 K5 M5 AG12 AG13 AG17 AG18 AG19 AD27 W27 N27 H27 E25 E20 E18 E17 E13 AL31 AL1 AK30 AK2 AJ29 AJ28 AJ16 AJ4 AJ3 AH29 AH28 AH16 AH4 AH3 AG27 AG21 AG16 AG11 AG5 AA27 AA5 T29 T28 T27 T5 T4 T3 L27 L5 E27 E21 E16 E11 E5 D29 D28 D16 D4 D3 C29 C28 C16 C4 C3 B30 B2 A31 A1 E4 AG4 U5 D5 D6 D9 C10 AH11 AG10 AJ9 AJ7 AG6 AH6 AD5 AD4 AB4 W5 W1 V4 U4 U1 R1 R2 P1 P3 N2 L4 J3 E3
C88
C92
3.3 V REG_3V
15 R59 10UF C121 NU R141
3.3 V REG_3V AVD0
0.1UF C127 4.7 R58 C118 C123 0.1UF 10UF 10UF C129 NU R150
AVD7
E
C98
F
3.3 V REG_3V
15 R56 0.1UF 10UF C115 C124 NU R147
3.3 V REG_3V AVD1
15 R57 C119 0.1UF 10UF C126 NU R153
AVD2 3.3 V
100 0.1UF
D
PLACE DECOUPLING CAPACITORS NEAR THE ANALOG POWER PINS 4X622 OPTION ONLY: N4, U1, U4, D9, B6, G3, J3, AB4, AD4, AJ7, AJ9 3.3 V
0.1UF C87 0.1UF 0.1UF C91 0.1UF 0.1UF C96 0.1UF 0.1UF C102 0.1UF 0.1UF C108 0.1UF 0.1UF
R152
C89
C93
REG_3V
4.7 R55
NU R148
REG_3V 4_CRU_AVD_0
0.1UF
NU R154
4C9<
4.7 R61
4_CRU_AVD_2
0.1UF
C99
3.3 V
3.3 V
4_CRU_AVD_0
10UF
47UF
47UF
C122
C128
C130
10UF
C133
C135
C
4_CRU_AVD_3 4_CRU_AVD_2 AVD7 4X622 OPTION ONLY DO NOT INSTALL CRU FILTER CIRCUITS ON 16X155 BOARD AVD2 AVD1 AVD0 4_CRU_AVD_1 4_CRU_AVD_3
AL30 AL29 AL28 AL26 AL21 AL16 AL11 AL6 AL4 AL3 AL2 AK31 AK29 AK16 AK3 AK1 AJ31 AJ30 AJ2 AJ1 AH31 AH1 AF31 AF1 AA31 AA1 T31 T30 T2 T1 L31 L1 F31 F1 D31 D1 C31 C30 C2 C1 B31 B29 B16 B3 B1 A30 A29 A28 A26 A21 A16 A11 A6 A4 A3 A2 E8 AG8 V3 E6 C6 D7 C8 E10 D10 AH10 AH9 AH8 AH7 AG7 AE4 AD3 Y5 W2 V5 U3 U2 R3 R4 P2 P4 N1 J4 H4 G4 F3 F4 F5 R5 P5
3 6
G
0.1UF
C273 0.1UF
0.1UF
C275 0.1UF
0.1UF
0.1UF
C86 0.1UF
0.1UF
C90 0.1UF
0.1UF
C95 0.1UF
0.1UF
C101 0.1UF
0.1UF
C107 0.1UF
0.1UF
C113 0.1UF
C274
C276
C278
C104
C110
C116
F
E
D
C105
C111
C136
C117
C
+
3.3 V REG_3V
4.7 R54 47UF 10UF C114 C120 NU R149
C80
3.3 V REG_3V 4_CRU_AVD_1
0.1UF C125 4.7 R60 0.1UF 47UF C131 10UF C132 C134 NU R155
+
B
B
+
+
USE 10V X5R CERAMIC 1210 SIZE CAPACITORS FOR ALL 10UF COMPONENTS USE TANTALUM CAPS FOR ALL 47UF COMPONENTS A PLACE EACH 0U1 CAPACITOR CLOSE TO THE ASSOCIATED POWER PIN THE 10UF CAPACIT AND RESISTORS DO NOT NEED TO BE PLACED CLOSE TO THE POWER PINS, AS THEY ARE FILTERING THE SUPPLY, NOT DECOUPLING IT.
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=SUNI_BLOCK ABBREV=SUNI_BLOCK LAST_MODIFIED=Thu Dec 14 10:38:42 2000 TITLE: S/UNI 16X155 REFERENCE DESIGN S/UNI SUPPLY FILTERING & REG ENGINEER: 3 BDV GR 2 ISSUE DATE: A
REVISION NUMBER: 1 PAGE:7 1 OF 17
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G U5 XCV200E-6BG352C 1 of 4
5G7< 9E3> 5E7< 5E7< 5E7< 5E7< 5E7< 5D7>
G
11B5>
FPGA_TFCLK1
LD<31..0>\I IO_2_10 IO_2_9 IO_2_8 IO_2_7 IO_2_6 IO_2_5 IO_2_4 IO_2_3 IO_2_2 IO_2_1 IO_L32P IO_L31P IO_L29P IO_L28P IO_L25P IO_L23P
C2 E3 F4 D1 G3 H3 G2 K3 K2 N3 N4 M2 L3 J1 F1 G4 M1 L2 L4 J2 J4 F2 F3 C1 M4 H2 E2 D2 E4 J3 D3 M3 G1 N2 P3 T3 V2 W3 W4 AA1 AA3 AB3 AD1 AB4 AA4 AC1 AA2 Y1 U3 T4 T2 R1 AB2 Y2 V1 U2 R2 P1 AC3 V3 R3 AD2 U4 AC2 Y3 V4 R4 6 0 7 5 6 1 1 5 9 2 12 11 15 1 1
6E7<>
12H4<> 8F3< 12D4>
SUNI_TDAT<31..0>\I SUNI_TSOC/TSOP\I SUNI_TADR<3..0>\I SUNI_TSX\I SUNI_TMOD<0>\I SUNI_TENB\I SUNI_RDAT<31..0>\I
LA<23..2>\I
3 2 0 0 30 25 21 20 22 24 29 31 1
RN50 RN50 RN75 RN75 RN39 RN66 RN66 RN66
3 4 3 4 2 1 2 3
6 5 6 5 7 8 7 6
33 33 33 33 33 33 33 33
F
D14 D22 C23 B24 C22 A24 B21 C20 D18 B18 D16 C15 B15 D15 C16 A18 C18 B19 A21 B22 D20 B23 B17 C17 D17 B20 A23 A16 C19 C21 D21 A15
GCK3 IO_0_12 IO_0_11 IO_0_10 IO_0_9 IO_0_8 IO_0_7 IO_0_6 IO_0_5 IO_0_4 IO_0_3 IO_0_2 IO_0_1 IO_L8P IO_L7P IO_L6P IO_L5P IO_L4P IO_L3P IO_L2P IO_L1P IO_L0P IO_L7N IO_L6N IO_L5N IO_L3N IO_L1N IO_VREF_0_L8N IO_VREF_0_L4N IO_VREF_0_L2N IO_VREF_0_L0N IO_LVDS_DLL_L9N
LOGIC ANALYZER/PROBE HEADER
12H4<> 8G4<>
12 13
6E7<>
LD<15..0>\I J2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
TP6 TP12
LA<23..2>\I
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 2 3 4 5 6 7 8 9 10 11 12 13
12D4>
1 1
TP31 TP32
6 13
SUNI_CSB\I
6C7< 8E1<
5E7> 5E7< 5E7>
SUNI_TCA/PTPA\I SUNI_TERR\I SUNI_STPA\I
1 26 27 28 3
RN66 RN67 RN67 RN67
4 1 2 3
5 8 7 6
33 33 33 33
5E7<
SUNI_TEOP\I
23 2
RN67 RN69 RN69 RN69 RN69
4 1 2 3 4
5 8 7 6 5
33 33 33 33 33
E
5E7< 5E7<
SUNI_TMOD<1>\I SUNI_TPRTY\I
19
IO_L31N IO_L29N IO_L28N IO_L27N IO_L25N IO_L24N IO_L23N IO_L22N IO_VREF_2_L30P IO_VREF_2_L26P IO_VREF_2_L24P IO_VREF_2_L22P IO_DOUT_BUSY_L21P IO_D2_L27P IO_DIN_D0_L21N IO_D3_L30N IO_D1_L26N IO_IRDY_L32N
1 1 1
TP33 TP34 TP35
7 8 0 10 14 4 3
RDB\I L_READYB\I
6C7< 8E1< 8F1< 12F2<
P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15 P_17 P_19 P_21 P_23 P_25 P_27 P_29 P_31
P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16 P_18 P_20 P_22 P_24 P_26 P_28 P_30 P_32
F
L_READYB\I RDB\I WRB\I SUNI_CSB\I
8E3> 8F3> 8E3> 8F3>
HEADER 16X2
1
TP4
WRB\I DIN
9 10 11
6C7< 8E1<
0.1UF
3.3 V
E
10D8>
C22
4
11B5>
FPGA_RFCLK1
B14 B13 B10 A9 B7 C8 D8 B5 B4 C5 A3 A4 A7 C10 D11 B11 A12 C6 C7 A6 D9 B8 B9 C11 A11 B12 C13 D6 B6 C9 C12 A13 D5 C4
U6
17 7 3
5C7> 5B7> 9F8< 5B7< 12D9<
SUNI_REOP\I
1 2
D
SUNI_RCA/RVAL\I SUNI_RADR<3..0>\I FPGA_CONFIG\I SUNI_RSOC/RSOP\I
8 12 10 13
2 0 1
3 RN41 1 RN31 2 RN31
6 8 7
33 33 33
GCK2 IO_1_10 IO_1_9 IO_1_8 IO_1_7 IO_1_6 IO_1_5 IO_1_4 IO_1_3 IO_1_2 IO_1_1 IO_L18P IO_L16P IO_L14P IO_L13P IO_L12P IO_L10P IO_L19N IO_L18N IO_L17N IO_L16N IO_L15N IO_L14N IO_L13N IO_L12N IO_L11N IO_L10N IO_VREF_1_L19P IO_VREF_1_L17P IO_VREF_1_L15P IO_VREF_1_L11P IO_LVDS_DLL_L9P IO_WRITE_L20N IO_CS_L20P
IO_3_10 IO_3_9 IO_3_8 IO_3_7 IO_3_6 IO_3_5 IO_3_4 IO_3_3 IO_3_2 IO_3_1 IO_L42P IO_L41P IO_L40P IO_L39P IO_L37P IO_L36P IO_L35P IO_L33P IO_L41N IO_L39N IO_L36N IO_L35N IO_L33N IO_TRDY_1 IO_D7_L43P IO_D6_L38P IO_D4_L34P IO_INIT_L43N IO_D5_L37N IO_VREF_3_L42N IO_VREF_3_L40N IO_VREF_3_L38N IO_VREF_3_L34N
L_WRB\I LHOLDA\I REF_SEL<1> RESET_PB FPGA_RFCLK2
2 0 4
12F2> 12F2< 11H9<
2
VCC
MAX811T
SW1 RESET
3 2
PBNO
11B5>
RESET MR GND
1
1
FPGA_TFCLK2
5
11B5>
D SUNI_RSTB\I L_USERI\I
6C7< 12E2< 5B7< 8B7< 6C7> 12E2< 12F2> 12F2>
5C7>
4 3 3
5B7> 5C7> 5C7>
SUNI_RSX\I SUNI_RPRTY\I SUNI_RMOD<0>\I
6 0 4 11 9 14 18
SUNI_POS_ATMB\I LED<6..0> SUNI_INTB\I L_CLK\I LHOLD\I L_ADSB\I
REF_SEL<0>
1
11H9< 10E8< 12E2> 12E2< 12E2>
C
5B7> 5C7>
SUNI_RERR\I SUNI_RMOD<1>\I
5 15 16
INIT L_USERO\I L_INTB\I L_RSTOB\I
2
C
5B7<
SUNI_RENB\I
3
1 RN41 RN41 2
8 7
33 33
VIRTEX_ONE SUNI_RALRM<15..0>\I
6G9>
B
8D3> 10C9>
LED<6..0> DONE
6 5 4 A1 A2 A3 A4
B GREEN D3
K1 K2 K3 K4
RN6 200
2 3 4 5 16 7 8 9 10
RSIP9
LED SSF-LXH5147
3 2 1 0 A1 A2 A3 A4
GREEN D4
K1 K2 K3 K4
TP11
1
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1.0 TITLE: S/UNI-16X155 REFERENCE DESIGN FPGA PL3 I/F ENGINEER: BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:8 1 OF 17 A
LED SSF-LXH5147
A DRAWING: FPGA_BLOCK FPGA_BLOCK Thu Dec 14 10:37:32 2000
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
U5
15E10<
SYS_RDAT<31..0>\I
15G10> 15C10< 15C10< 15C10< 15C10>
0
XCV200E-6BG352C 2 of 4 SYS_TFCLK\I SYS_RMOD<1>\I SYS_REOP\I SYS_RSX\I SYS_RENB\I SYS_RPRTY\I RN7 RN12 RN7 RN7 RN68 RN12 RN11 RN23 RN13 RN8 RN10 RN11 RN10
1 2 3 2 1 3 3 1 2 1 3 1 4 3 3 4 1 4 2 4 2 1 4 2 4 2 1 8 7 6 7 8 6 6 8 7 8 6 8 5 6 6 5 8 5 7 5 7 8 5 7 5 7 8
SYS_TDAT<31..0>\I IO_6_10 IO_6_9 IO_6_8 IO_6_7 IO_6_6 IO_6_5 IO_6_4 IO_6_3 IO_6_2 IO_6_1 IO_L75P IO_L74P IO_L73P IO_L72P IO_L71P IO_L70P IO_L69P IO_L68P IO_L67P IO_L66P IO_L65P
AB24 AA23 AC25 Y23 Y25 AA26 W25 V26 T24 P23 P24 R25 T26 U25 U24 U23 W24 Y24 AB25 AC26 AD25 R26 T25 T23 V25 V23 AA24 AC24 N26 R24 Y26 AA25 AD26 M26 L23 K24 H23 F26 F25 F23 C26 E23 D24 C25 F24 H24 H25 J25 L24 M24 N24 D25 E25 G24 G25 J23 K23 J26 K25 M23 M25 L26 E24 D26 G26 N25 12 16 9 20 18 13 21 23 31
15H10>
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
15D10<
3 9 8 17 14 11 4 6
F
AE13 AE3 AD5 AC6 AF4 AD7 AE7 AD8 AD10 AE10 AD13 AE12 AD11 AF9 AD9 AF6 AC7 AC5 AF12 AD12 AE11 AC11 AE9 AF7 AC9 AE6 AD6 AF3 AD4 AC12 AE8 AE5 AE4 AC13
GCK0 IO_4_10 IO_4_9 IO_4_8 IO_4_7 IO_4_6 IO_4_5 IO_4_4 IO_4_3 IO_4_2 IO_4_1 IO_L54P IO_L52P IO_L51P IO_L50P IO_L48P IO_L46P IO_L44P IO_L54N IO_L53N IO_L52N IO_L51N IO_L50N IO_L49N IO_L48N IO_L47N IO_L46N IO_L45N IO_L44N IO_VREF_4_L53P IO_VREF_4_L49P IO_VREF_4_L47P IO_VREF_4_L45P IO_LVDS_DLL_L55P
RN39 RN39 RN72
4 3 2
5 6 7
33 33 33
29 26 27 28 22 19 11 8 7
SUNI_F_RFCLK SUNI_F_TFCLK SYS_TCA/PTPA\I
11C5< 11C5< 15G10<
F
8D9>
1
SUNI_RADR<0>\I RN68 SYS_TADR<3>\I RN23 RN11 RN10 RN23 RN10 RN7 RN23 RN12 RN68 RN11 RN12 SYS_RADR<2>\I SYS_RCA/RVAL\I RN68 RN13
15H10>
13 15 10 12 5
SUNI_RALRM<15..0>\I 6G9>
15
15C10<
7
SYS_RERR\I SYS_RADR<1>\I SYS_RSOC/RSOP\I SYS_RMOD<0>\I SYS_RADR<3>\I
E
16 2
15D10> 15D10< 15C10< 15D10> 15D10> 15D10<
18
IO_L75N IO_L73N IO_L72N IO_L71N IO_L69N IO_L67N IO_L65N IO_TRDY_2 IO_VREF_6_L74N IO_VREF_6_L70N IO_VREF_6_L68N IO_VREF_6_L66N IO_7_11 IO_7_10 IO_7_9 IO_7_8 IO_7_7 IO_7_6 IO_7_5 IO_7_4 IO_7_3 IO_7_2 IO_7_1 IO_L85P IO_L83P IO_L81P IO_L80P IO_L79P IO_L77P IO_L76P IO_L86N IO_L85N IO_L84N IO_L83N IO_L82N IO_L81N IO_L80N IO_L79N IO_L78N IO_L77N IO_VREF_7_L78P IO_VREF_7_L86P IO_VREF_7_L84P IO_VREF_7_L82P IO_IRDY_L76N
30
RN72
3
6
33
24 25 15 10 13 14 17 14 6 10
SYS_STPA\I
15G10<
E
15H10>
SYS_TDAT<31..0>\I
15C10>
20 21 25 31
SYS_RFCLK\I RN8 RN8 RN14 RN14 SYS_TADR<2>\I SYS_TPRTY\I SYS_TSX\I SYS_TSOC/TSOP\I
3 2 3 4 6 7 6 5
33 33 33 33
15H10> 15G10> 15G10> 15H10>
D
1 5 2
AF14 AF15 AE15 AD16 AE18 AD19 AC19 AF21 AD21 AD22 AF24 AC22 AC21 AF23 AE21 AF20 AD18 AD17 AC16 AE16 AD15 AE22 AE20 AC17 AF18 AE17 AE23 AD20 AC18 AC15 AD14
GCK1 IO_5_11 IO_5_10 IO_5_9 IO_5_8 IO_5_7 IO_5_6 IO_5_5 IO_5_4 IO_5_3 IO_5_2 IO_5_1 IO_L64P IO_L63P IO_L62P IO_L61P IO_L60P IO_L59P IO_L58P IO_L57P IO_L56P IO_L63N IO_L61N IO_L59N IO_L58N IO_L57N IO_VREF_5_L64N IO_VREF_5_L62N IO_VREF_5_L60N IO_VREF_5_L56N IO_LVDS_DLL_L55N
RN39 RN32 RN29 RN28 RN28 RN29 RN29 RN50 RN33 RN41 RN33 RN31 RN30 RN30 RN32 RN71 RN29 RN33 RN31 RN28 RN30 RN30 RN32 RN32 RN72 RN50 RN33 RN28
1 3 2 2 1 1 3 1 1 4 2 5 1 2 4 4 4 4 6 3 3 4 1 2 1 2 3 4
8 6 7 7 8 8 6 8 8 5 7 4 8 7 5 5 5 5 3 6 6 5 8 7 8 7 6 5
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
SUNI_TDAT<31..0>\I 28
26 19 15 14 12 5 9 6 4 13 20 21 23 29 31 11 7 11 16 17 22 25 24 27 8 9 30 10 8 18 12
8G9> 5G7<
D
15G10>
3
SYS_TERR\I SYS_TEOP\I SYS_TADR<0>\I SYS_TADR<1>\I RN15 RN14 RN14 RN13 SYS_TMOD<0>\I RN15 RN15 RN15 SYS_TMOD<1>\I SYS_TENB\I RN13 RN8
3 4 6 5 4 1 2 5 8 7 3 1 2 4 6 8 7 5
15G10> 15H10> 15H10>
28 26 24 22 0
33 33 33 33 33 33 33
15H10>
29 30 27 4
15H10> 15G10>
C
23 19
33 33
C
VIRTEX_TWO
B
B
PMC-Sierra, Inc.
A DRAWING: FPGA_BLOCK FPGA_BLOCK Thu Dec 14 10:37:38 2000 DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1.0 TITLE: SUNI-16X155 REFERENCE DESIGN FPGA PL3 I/F ENGINEER: 10 9 8 7 6 5 4 3 BDV 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:9 1 OF 17 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H 1.8V REGULATOR FOR FPGA VDDI 1.8 V 3.3 V
LP3966ES-1.8 VOUT 2 VIN SENSE 1 SD GND TAB U12
3 4 5 0.1UF 6 C72 10UF C73
H
PLACE NEAR EACH CORNER OF FPGA 3.3 V
1.8 V
0.1UF C27 0.1UF 0.1UF 0.1UF C33 0.1UF C35 0.1UF 0.1UF C39 0.1UF C41 0.1UF C43 0.1UF C29 C31 C37 C45 47UF C56 47UF C59 47UF C62 47UF
+
+
+
0.1UF
C66 10UF
C71
10K
R33
C74
+
G
PLACE CAPS NEAR PINS A20,C14,D10,K4,P2,T1,AC10,AF16,R23,L25 PLACE BULK DECOUPLING CAPS NEAR EACH I/O BANK OF FPGA 3.3 V
G
10UF
10UF
C60 10UF
C63 10UF
C75 10UF
C76 10UF
C78 10UF
C81 10UF
+
+
+
+
+
+
+
C58
1.8 V F
A20 B16 C14 D12 D10 K4 L1 P2 T1 W2 AC10 AF11 AE14 AF16 AE19 V24 R23 P25 L25 J24 N23 K26 G23 AE25 W23 U26 AF17 AC20 AC14 AF10 AE2 AC8 Y4 U1 P4 K1 H4 B2 D13 D7 A10 D19 B25 A17
U5 XCV200E-6BG352C 4 of 4 VCCINT_20 VCCINT_19 VCCINT_18 VCCINT_17 VCCINT_16 VCCINT_15 VCCINT_14 VCCINT_13 VCCINT_12 VCCINT_11 VCCINT_10 VCCINT_9 VCCINT_8 VCCINT_7 VCCINT_6 VCCINT_5 VCCINT_4 VCCINT_3 VCCINT_2 VCCINT_1 VCCO_24 VCCO_23 VCCO_22 VCCO_21 VCCO_20 VCCO_19 VCCO_18 VCCO_17 VCCO_16 VCCO_15 VCCO_14 VCCO_13 VCCO_12 VCCO_11 VCCO_10 VCCO_9 VCCO_8 VCCO_7 VCCO_6 VCCO_5 VCCO_4 VCCO_3 VCCO_2 VCCO_1 POWER GND_32 GND_31 GND_30 GND_29 GND_28 GND_27 GND_26 GND_25 GND_24 GND_23 GND_22 GND_21 GND_20 GND_19 GND_18 GND_17 GND_16 GND_15 GND_14 GND_13 GND_12 GND_11 GND_10 GND_9 GND_8 GND_7 GND_6 GND_5 GND_4 GND_3 GND_2 GND_1
A26 A25 A22 A19 A14 A8 A5 A2 A1 B26 B1 E26 E1 H26 H1 N1 P26 W26 W1 AB26 AB1 AE26 AE1 AF26 AF25 AF22 AF19 AF13 AF8 AF5 AF2 AF1
C84
+
F
E 3.3 V CONFIGURATION EPROM
8C3>
3.3 V
E
3.3 V 3.3 V
4.7K R25 4.7K R26
2
3
4.7K 4.7K
44
JTAG CONFIG AND READBACK U5
7
C23
GND
GND
D
0.1UF
27
CEO
CCLK INIT
RN51 RN51
41
VCC
U7 VPP
XC1702L-PC44 DATA 2 CLK 5 OE 19 CE 21
8E3< DIN
C3 AD3 AC4 AC23 AB23 AD24
XCV200E-6BG352C 3 of 4 CCLK DONE PROGRAM M2 M1 M0 CONTROL TCK TDI TDO TMS DXP DXN
C24 B3 D4 D23
3.3 VFPGA_JTAG
1 2 3 4 5 6
6
3
24
TCK TDI TDO TMS 4.7K
8
J5 P_1 P_2 P_3 P_4 P_5 P_6
3.3V TCK TDI TDO TMS GND
D
AE24 AD23
3.3 V
0.1UF
C
J3 XCHECKER 3.3V 1 1 GND 2 2 33 CCLK 4 4 DONE 5 5 DIN 6 6 PROGRAMB 7 7 INIT 8 8 8B7< DONE 9 9
HEADER9
C24
RN51
1
C
3.3 V DONE
0.1UF C25 0.1UF C26 0.1UF 0.1UF C30 0.1UF C32 0.1UF 0.1UF 0.1UF C38 0.1UF C40 0.1UF 0.1UF C44 0.1UF
C28
C34
C36
C42
3.3 V B
1 3 5
P_MODE PLACE DECOUPLING CAPS NEAR PINS J4
P_1 P_3 P_5 P_2 P_4 P_6
2 4 6
C46
B
B2,K1,U1,AE2,AF10,AF17,AE25,U26,K26,B25,A17,A10
HEADER 3X2
4
3
2
4.7K 4.7K 4.7K
INSTALL JUMPERS FOR SLAVE SERIAL (XCHECKER) MODE UNINSTALL JUMPERS FOR MASTER SERIAL (EPROM) DEFAULT MODE
PMC-Sierra, Inc.
5 6
RN34 RN34 RN34
7
A
DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1.0 DRAWING: FPGA_BLOCK FPGA_BLOCK Thu Dec 14 10:37:43 2000 TITLE: S/UNI-16X155 REFERENCE DESIGN FPGA POWER & CONFIGURATION ENGINEER: BDV 2
ISSUE DATE: YY/MM/DD REVISION NUMBER: 1.0 PAGE:10 1 OF 17
A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
PLACE TERM RESISTORS AT END OF TRACE U28 H
8E3> 8C3>
ZONE
REV
DESCRIPTION
DATE
APPR
REF_SEL<1..0>
17 06 5
LVTTL
LVPECL
D0 D1
Q0P Q0N Q1P Q1N
11 2 03 4 8
PREF_SEL<1..0>
H
MC100LVELT22
3.3 V
1 0
J6
3 1 4 0.1UF C65 2 10 R65
GND VCC 3.3 V
0.1UF
330
R91
C68
SMB
3.3 V
1
5
330
R114
U29
15G5> 15G5>
16
G SYS_REF_INP\I SYS_REF_INN\I Y1 3.3 V
14 0.1UF 10UF C77 100 R120 49.9 R62
TP17
G
1 1 2 3 4 5 6 7 8 R38
VCC
TP20
D0P D0N D1P D1N
SEL1 SEL0 QP QN
14 15 13 12
1 0
PLACE TEST POINTS INLINE WITH TRACE SUNI_REFCLKP\I SUNI_REFCLKN\I
R36 150 R40 150
OSC_PECL PWR OUTP GND OUTN
SY100EL57L
6C3< 6C3<
8 1
D2P D2N VEE D3P D3N VBB2 VBB1
10 11 0.01UF C70
+
7 C64
77.76MHZ
20 PPM R18
150 150
1 9
3.3 V
R17 10 R90 0.1UF C67
F
F
J7
6G6>
SUNI_RCLK\I
124 R116
1 4 82.5 R115
3
2
SMB
5
E
3.3 V
100LVEL16
U13
E
100 R121
8 2 3 5
VCC D DB VEE Q QB VBB
7 6 4 150 R50 R42 150
SYS_REF_OUTP\I SYS_REF_OUTN\I
15F5< 15F5<
3.3 V
10 R66 0.1UF C69
D
D
SUNI_O_TFCLK 3.3 V
9F3>
0.1UF 4 8 15 20 C61 0.1UF C153
1 1
SUNI_F_TFCLK SUNI_F_RFCLK SUNI_O_RFCLK
SB1 12 SB SB2 12 SB SB3 12 SB SB4 12 SB
2 2
SUNI_TFCLK\I
5E7<
9F3>
1
2
SUNI_RFCLK\I
5B7<
C
C
2
VCC VCC VCC VCC
1
U10 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
1 3 2 5 3 7 9 RN88 4 11 1 12 2 14 3 16 RN89 4 18 19 8 7 6 5 33 8 7 6 5 33 33 R32 33 R112 1 1
1
A
3.3 V
HCMOS 100.000MHZ 3.3V 100PPM U20
8
PI49FCT3807
0.1UF
VDD
OUT
5 1
SYS_RSYSCLK\I SYS_TSYSCLK\I FPGA_RFCLK2 FPGA_RFCLK1 FPGA_TFCLK2 FPGA_TFCLK1
TP14 TP15
15C10< 15G10< 8D3< 8E9< 8D3< 8G9<
4 C57
GND NC/TS
GND GND GND GND GND
B PLACE BUFFER LESS THAN 2CM FROM OSCILLATOR
2 6 10 13 17
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=FPGA_BLOCK ABBREV=FPGA_BLOCK LAST_MODIFIED=Thu Dec 14 10:37:47 2000 10 9 8 7 6 5 4 3 TITLE: S/UNI-16X155 REFERENCE DESIGN REFCLK AND UL3/PL3 CLOCK ENGINEER: BDV GR 2 ISSUE DATE: A
REVISION NUMBER: 1 PAGE:11 TRUE 1 OF 17
10
9
8
7
6
5
4
3
2
1
REVISIONS
CPCI BRIDGE
3.3 V H 3.3 V
4.7K R7
ZONE
REV
DESCRIPTION
DATE
APPR
H 3.3 V 3.3 V 3.3 V 3.3 V LD<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6E7<> 8G4<> 8F3<
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
6 8 7 7
95 96 97 98 100 101 102 103 104 105 106 107 110 111 112 113 114 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131
13H8<>
AD<31..0>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0
3.3 V
162 147 141 133 116 109 99 89 70 62 45 35 28 20 1 139 138 137 136 134 163 144 143 148 90 149 135 146 145 91 92 153 151 150 160 142 53 154 152 159 158 157 156 155 176 161 140 132 115 108 88 69 61 44 27 19
LD<31> LD<30> LD<29> LD<28> LD<27> LD<26> LD<25> LD<24> LD<23> LD<22> LD<21> LD<20> LD<19> LD<18> LD<17> LD<16> LD<15> LD<14> LD<13> LD<12> LD<11> LD<10> LD<9> LD<8> LD<7> LD<6> LD<5> LD<4> LD<3> LD<2> LD<1> LD<0>
7 6 5 8
6 8 6 7
7 5 8 5
RN2 RN2 RN2 RN1
RN1 RN5 RN3 RN3
RN1 RN3 RN2 RN1
RN4 RN3 RN5 RN4
PART#PCI9054-AB50PI
DP<3> DP<2> DP<1> DP<0> BTERM* BIGEND* LHOLDA LHOLD BLAST* LW/R* BREQO READY* LSERR* ADS*
RN4 RN5 RN5 RN4
G
F
13H8<>
C/BE<3..0>
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> C/BE<3> C/BE<2> C/BE<1> C/BE<0> P_ENUMB P_PAR P_DEVSELB P_STOPB P_SERRB P_PERRB P_LOCKB P_FRAMEB P_TRDYB P_IRDYB P_IDSEL P_REQB P_RSTB P_GNTB P_CLK P_INTAB VIO_PCI\I
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
39.2
2 1 1 1 3 3 2 4 4 2 4 3 4 3 2 1 1 1 4 3 2 2 1 4 3 2 2 4 4 3 1 3 4 1 1 2 1 2 4 3 3 3 2 4 4 3 2 4
7 8 8 8 6 6 7 5 5 7 5 6 5 6 7 8 8 8 5 6 7 7 8 5 6 7 7 5 5 6 8 6 5 8 8 7 8 7 5 6 6 6 7 5 5 6 7 5
RN42 RN52 RN57 RN37 RN42 RN52 RN57 RN52 RN57 RN37 RN42 RN55 RN62 RN37 RN48 RN48 RN55 RN62 RN37 RN48 RN55 RN62 RN38 RN48 RN62 RN38 RN49 RN55 RN63 RN38 RN49 RN56 RN38 RN56 RN40 RN56 RN63 RN63 RN56 RN63 RN57 RN49 RN40 RN64 RN49 RN40 RN52
R16
ADX31 ADX30 ADX29 ADX28 ADX27 ADX26 ADX25 ADX24 ADX23 ADX22 ADX21 ADX20 ADX19 ADX18 ADX17 ADX16 ADX15 ADX14 ADX13 ADX12 ADX11 ADX10 ADX9 ADX8 ADX7 ADX6 ADX5 ADX4 ADX3 ADX2 ADX1 ADX0 CBEX3 CBEX2 CBEX1 CBEX0 ENUMX PARX DEVSELX STOPX SERRX PERRX LOCKX FRAMEX TRDYX IRDYX IDSELX REQX
173 174 175 2 3 4 5 8 9 10 11 12 13 14 15 31 32 33 34 36 37 38 39 40 42 43 46 47 48 49 50 51 6 16 30 41 167 52 29 22 23 26 25 24 17 21 18 7 172 169 171 170 168
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0>
VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1
5 6 5 8 4 3 4 1
RES_ARRAY_4
2 3 4 1
3 1 3 2
2 4 1 4
3 1 2 2
4.7K 4.7K 4.7K 4.7K
G
U11
LHOLDA\I LHOLD\I L_WRB\I L_READYB\I L_ADSB\I
8E3> 8C3< 8E3<
F
8E3> 8C3<
PCI9054 C-MODE
C/BE<3>* C/BE<2>* C/BE<1>* C/BE<0>* PME* ENUM* PAR DEVSEL* STOP* SERR* PERR* LOCK* FRAME* TRDY* IRDY* IDSEL REQ* RST* GNT* PCLK INTA* EEDI/O EESK EECS
13C5< 13C5<> 13F5<> 13C5<> 13F5< 13A5<>
LBE2* LBE3* DMPAF/EOT* WAIT* BREQI CCS* LCLK LEDON/LEDIN LINT* LRESETO* USERI/DACK0/LLOCKI* USERO/DREQ0/LLOCKO* MODE<1> MODE<0> TEST VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1
L_CLK\I L_INTB\I L_RSTOB\I L_USERI\I L_USERO\I
8D3> 8C3> 8C3< 8D3> 8C3<
E
1 1K 3 1K 3 1K 2 1K
13B5> 13C5> 13G5< 13H7>
10
1
8
RN42
INTAX
5
LBE0* LBE1* LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LA<28> LA<29> LA<30> LA<31>
8 6 6 7
RSTX
2 1
LBE0 94 LBE1 93
8D9>
FPGA_CONFIG\I
2.2K R73
OUT A GND
3
1.2K
D
R21
166 165 164
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 68 67 66 65 64 63 60 59 58 57 56 55 54
B
VCC
4
RN44 RN44 RN59 RN59
U4
RN44 RN44 RN59 RN59
7 5 8 5
2 1K 4 1K 1 1K 4 1K
13B5<> 13E5<> 13B5<> 13D5<> 13E5> 13G5< 13D5>
10
RN40
LBE0 LBE1
E
3.3 V D
0.1UF C16 0.1UF C17 0.1UF C15 0.1UF 0.1UF C14 0.1UF C19 0.1UF C2 0.1UF C3 10UF C48 10UF
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+
C13
6E7< 8F1< 8G3<
3.3 V
3.3 V
C47 0.1UF
10UF
4.7K
+
C21
R19
U1
NM93CS66LEN
PLACE AROUND U2
1 2 3 4 2.2K R22
8 7 6 5 4.7K R20
VCC PRE PE GND
CS SK DI DO
C PLACE NEAR U1
C49
LA<31..2>\I
+
C
PRECHARGE
D5
DL4148
ADJ U3
LT1117CST
1V_PRECHG 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
1
2
2 4 R24 130
VOUT VIN TAB ADJ
3
3_3V_LONG
13H7>
VIO_LONG
13H7>
0.1UF
1
5
8
8
R27
7
10K 10K 10K 10K
24
R23
C4
6
7
8
5
6
8
7
5
6
6
5
8
5
5
8
7
7
8
8
7
5
6
7
6
6
5
8
5
6
8
7
7
5
5
6
8
7
7
8
8
6
6
6
5
5
7
100K
56
R28
3
2
1
4
3
1
2
4
3
3
4
1
4
4
1
2
2
1
1
2
4
3
2
3
3
4
1
4
3
1
2
2
4
4
3
1
2
2
1
1
3
3
3
4
4
2
B
B
4
1
1
RN27 RN45 RN35 RN27 RN53 RN45 RN35 RN58 RN45 RN35 RN60 RN53 RN45 RN35 RN60 RN53 RN46 RN46 RN36 RN60 RN53 RN46 RN36 RN60 RN54 RN61 RN54 RN46 RN36 RN61 RN54 RN47
RN54 RN36 RN58 RN43 RN61 RN43 RN47 RN58 RN61 RN47 RN43 RN65 RN47 RN58
2
CBEX0 CBEX1 CBEX2 CBEX3 FRAMEX IRDYX TRDYX DEVSELX STOPX IDSELX LOCKX PARX PERRX SERRX
DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Thu Dec 14 10:38:05 2000 P_GNTB
ADX0 ADX1 ADX2 ADX3 ADX4 ADX5 ADX6 ADX7 ADX8 ADX9 ADX10 ADX11 ADX12 ADX13 ADX14 ADX15 ADX16 ADX17 ADX18 ADX19 ADX20 ADX21 ADX22 ADX23 ADX24 ADX25 ADX26 ADX27 ADX28 ADX29 ADX30 ADX31
RSTX ENUMX INTAX REQX
RN43 RN65 RN27 RN27
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991413 DOCUMENT ISSUE NUMBER: 1 TITLE: SUNI-16X155 REFERENCE DESIGN CPCI_BLOCK ENGINEER: PMC 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2 PAGE:12 1 OF 17 A
A
NOTES: 1. 2. 3. 4. 5.
ALL 10 OHM STUBS WITHIN 0.6" ALL PCI SIGNAL TRACES < 1.5" P_CLK TRACE MUST BE 2.5" +/CPCI BUS TRACES ARE 65 OHM. 39 OHM STUB RESISTOR ON REQB
OF J1 EXCEPT P_CLK 0.1" PLACED NEAR BRIDGE PIN
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
AD<31..0>
12H10<>
ZONE
REV
DESCRIPTION
DATE
APPR
H
12D9< 14F8<
H C/BE<3..0>
12F10<>
3.3 V
14G8<
12C5<
14F8<
12C3<
1 2 3 4
4.7K 4.7K 4.7K 4.7K
3_3V_PCI\I
5V_PCI\I
PLACE DECOUPLING CAPS CLOSE TO CONNECTOR 3_3V_LONG VIO_PCI\I VIO_LONG RN16 8 RN16 7 RN16 6 RN16 5 5V_PCI\I
0.1UF
CPCI J1
G
J1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 ZPACK5X22A CPCI
A1 A2 A3 A4 A5 A6 A7 AD<30> A8 AD<26> A9 C/BE<3> A10 AD<21> A11 AD<18> A15 A16 A17 A18 A19 A20 AD<12> A21 A22 AD<7> A23 A24 AD<1> A25 B1 B2 B3 B4 B5 B6 B7 AD<29> B8 B9 B10 B11 AD<17> B15 B16 B17 B18 B19 AD<15> B20 B21 AD<9> B22 B23 AD<4> B24 B25 C1 C2 C3 C4 C5 C6 C7 AD<28> C8 C9 AD<23> C10 C11 AD<16> C15 C16 C17 C18 C19 AD<14> C20 C21 AD<8> C22 C23 AD<3> C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 AD<25> D9 D10 AD<20> D11 D15 D16 D17 D18 D19 D20 AD<11> D21 D22 AD<6> D23 D24 AD<0> D25 E1 E2 E3 E4 E5 E6 AD<31> E7 AD<27> E8 AD<24> E9 AD<22> E10 AD<19> E11 C/BE<2> E15 E16 E17 E18 C/BE<1> E19 AD<13> E20 AD<10> E21 C/BE<0> E22 AD<5> E23 AD<2> E24 E25
3_3V_PCI\I
0.1UF C52 0.1UF
VIO_PCI\I
0.1UF
C10 10UF
C12 10UF
C20 10UF
C11 10UF
+
+
C50
C54
+
+
P_INTAB P_REQB
30 26 3 21 18
12E9> 12E9>
10 R29 0.1UF C1 10UF 0.1UF
12V_PCI\I P_DEVSELB P_SERRB
12E9<> 12E9>
VEE_PCI\I
10UF
C51
C18
F
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
12 7 1
+
C53
+
C55
G
F
VEE_PCI\I HEALTHYB\I
29
14E8< 14E8>
P_IDSEL
17
12E9< 12E9<>
P_FRAMEB
E
15 9 4
E
P_RSTB
28 23 16
P1
12E9<
STRIP3
3
1
10M 2 R30
HOLE_SIZE= 150 MIL
MOUNTING HOLE
D
P_IRDYB
STRIP2
12E9<>
ESD STRIP
10M R31
TP2 T CHASSIS D TP1 T CHASSIS
14 8 3
STRIP1
CPCI ESD STRIP
1
10M
P_ENUMB 12V_PCI\I
12E9> 14F8<
P_CLK
25 20
12E9<
C
R1
C
BD_SELB\I P_STOPB P_PAR
11 6 0
14E8< 12E9<> 12E9<>
B
B P_GNTB
31 27 24 22 19 2
12E9<
P_TRDYB P_LOCKB P_PERRB
1 13 10 0 5 2
12E9<> 12E9<> 12E9<>
DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Thu Dec 14 10:38:10 2000
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991413 DOCUMENT ISSUE NUMBER: 1 TITLE: SUNI-16X155 REFERENCE DESIGN CPCI_BLOCK ENGINEER: PMC 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2 PAGE:13 1 OF 17 A
A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
HOT SWAP CONTROLLER
G
5V
G
3.3 V
13H7>
5V_PCI\I
8IRF7413 3 2 5 4 1
0.01 R15 7 6
7 6
8 IRF7413 3 2 5 4 1
+5V
13H8>
3_3V_PCI\I
0.01 R5 0.01 R14
+3.3V
220UF
R8
R6
10
10
C9
+
F
10 11 13 12 14
100 R9 C8 0.047UF
+12V F
13H7>
VIO_PCI\I
9 1.2K 2.0K 2.0K
U2
R4
R2
R3
3V_IN
GATE
3
3V_OUT
5V_IN
3V_SENSE
13C5> 13F5> 13C5>
12V_PCI\I VEE_PCI\I BD_SELB\I
5V_SENSE
5V_OUT
1 2 5 6
12V_IN VEE_IN ONB FAULTB
12V_OUT VEE_OUT
16 15
12V_OUT VEE_OUT
LTC1643LCGN
5V
E
13F5<
7 0.1UF 2
+12V
R10 63.4
3.3 V
PWRGDB
GND
HEALTHYB\I
0.1UF
TIMER
E
R13
560
560
R12
150
R11 A1 A2 A3 A4
D1
C5
C6
0.01UF
GREEN D2
K1 K2 K3 K4
8
4
1
VEE
C7
LED SSF-LXH5147
GND VEE
D
D
3.3V SWITCHING REGULATOR FOR OPTICS MODULES C
5V
C 3.3VA
U21
6 2 5 0.1UF 1 C176 10UF
VIN ON/OFF IN_RETURN GND
VOUT OUT_RETURN
3 4 C177 0.1UF 10UF C178
C175
+
UNR3V5 8-D5
+
B
B
DRAWING: TITLE=POWER_BLOCK ABBREV=POWER_BLOCK LAST_MODIFIED=Thu Dec 14 10:37:58 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-1991414 DOCUMENT ISSUE NUMBER: 1 TITLE: SUNI-16X155 REFERENCE DESIGN POWER_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 PMC 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 3 PAGE:14 1 OF 17 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
9G3< 9E10< 9C8< 9F8< 9D8<
H SYS_TDAT<31..0>\I SYS_TMOD<1..0>\I SYS_TADR<3..0>\I
9D8<
SYS_TSOC/TSOP\I
J10
0
5G1< 11G9<
B1 B2 1 B3 B4 B5 B6 B7 B8 B9 B10 3 1 6 11 16 21 26 30
SYS_APSI<7..0>\I SYS_REF_INP\I
J12
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
G
9D8< 9D8< 9E3> 9C8< 9D8< 11C5> 9G8< 9F3> 9D8<
SYS_TSX\I SYS_TPRTY\I SYS_STPA\I SYS_TENB\I SYS_TEOP\I SYS_TSYSCLK\I SYS_TFCLK\I SYS_TCA/PTPA\I SYS_TERR\I
2
2 7 12 17 22 27 31
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
ROUTE THE FOLLOWING AS PAIRS
7 5 3 1
SYS_APSI<7> SYS_APSI<5> SYS_APSI<3> SYS_APSI<1> SYS_APSO<7> SYS_APSO<5> SYS_APSO<3> SYS_APSO<1>
SYS_APSI<6> SYS_APSI<4> SYS_APSI<2> SYS_APSI<0> SYS_APSO<6> SYS_APSO<4> SYS_APSO<2> SYS_APSO<0>
G
J10
11G9<
C1 C2 C3 C4 0 C5 5 10 C6 15 C7 20 C8 25 C9 C10
SYS_REF_INN\I
J12
6 4 2 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
J10
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
J10
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
J10
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
F
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
1
4 9 14 19 24 29
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
7 5 3 1
F
J10
0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
11E3> 11E3>
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
SYS_REF_OUTP\I SYS_REF_OUTN\I
J12
6 4 2 0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
3 8 13 18 23 28
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10
E
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
E
5F1> 9G9>
SYS_APSO<7..0>\I
J12 J12
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
SYS_RDAT<31..0>\I
J12
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
9E8< 9E8>
SYS_RADR<3..0>\I SYS_RCA/RVAL\I
J11
0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
9F8>
SYS_RPRTY\I
1 6 11 16 21 26 31
D
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10
B1 B2 1 B3 B4 B5 B6 B7 B8 B9 B10
0 5 10 15 20 25 30
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10
D
1
TP18
1
TP5
9E8> 9F8> 9E8> 11C5> 9E8> 9E8<
SYS_RSOC/RSOP\I SYS_RMOD<1..0>\I
J11
SYS_RSYSCLK\I
2 0
SYS_RERR\I SYS_RFCLK\I SYS_RENB\I SYS_RSX\I SYS_REOP\I
C
9F8< 9F8> 9F8>
C1 C2 C3 C4 C5 4 C6 9 14 C7 19 C8 24 C9 29 C10
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10
D1 D2 3 D3 D4 D5 D6 D7 D8 D9 D10
1 1 3 8 13 18 23 28
TP19
1
TP41
1
TP10
1
TP25
C
1
TP9
1
TP13
J11
E1 E2 E3 E4 E5 2 E6 7 12 E7 17 E8 22 E9 27 E10
J11
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
J11
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
J11
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
B
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 F6 E6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
1
TP8
1
TP16
1
TP7
1
TP3
PLACE HEADERS THROUGHOUT BOARD
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=SYS_INTERFACE ABBREV=SYS_INTERFACE LAST_MODIFIED=Thu Dec 14 10:38:47 2000 10 9 8 7 6 5 4 3 TITLE: S/UNI-16X155 REFERENCE DESIGN SYSTEM INTERFACE ENGINEER: BDV GR 2 ISSUE DATE: A
REVISION NUMBER: 1 PAGE:15 1 OF 17
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
3.3VD 3.3VD
100NH
G
C138 0.1UF L1 10UF 0.1UF 10UF
100NH C148 0.1UF 0.1UF L5 C144 C146
G
C79 C85
+
A A A
49.9 R41 100NH C139 0.1UF L2 0.1UF
A_TXDP8 3.3VD
17C7>
+
A_TXDP10 A
17C7>
A
C142 R48
A
49.9 L6 R64 100NH
220
C149
VBB_A
330 R49
0.1UF
VBB_A
C152 0.1UF
A
49.9 6 2 R43
A
49.9 6 2
U16 A_TXDN8 A_RXDP8 A_RXDN8 A_SD8 A
17C7> 17C5< 17C5< 17C5<
13 14 15 16 11 12
A
13 14 15 16 11 12
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R34 150 R37 150 R46 150
A
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R52 150 R53 150 150 R68
R67
F
U14
F A_TXDN10 A_RXDP10 A_RXDN10 A_SD10
A
17C7> 17C5< 17C5< 17C7<
CHASS1 CHASS2 VEET VEER
1
CHASS1 CHASS2 VEET VEER
1
GND1
GND1
7
A A E
7
A A E
D 3.3VD
100NH C140 0.1UF 0.1UF L3 10UF C83 C137
D 3.3VD
100NH C150 0.1UF 0.1UF L7 10UF C145 C147
+
A_TXDP11 A
17C7>
+
A
A
49.9 R44 100NH C141 0.1UF L4
A A A
49.9 R70 100NH C151 0.1UF L8 0.1UF
A_TXDP12 3.3VD
17C7>
C154
C A
49.9 6 2 R45
VBB_A
C143 0.1UF
220
R75
C
VBB_B
330 R76
A
49.9 6 2
U15
13 14 15 16 11 12
A
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R35 150 R39 150 150 R47
U17 A A_TXDN11 A_RXDP11 A_RXDN11 A_SD11
17C7> 17C5< 17C5< 17C5<
13 14 15 16 11 12
A
CHASS1 CHASS2 VEET VEER
1
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R63 150 R69 150 150 R72
R71
A_TXDN12 A_RXDP12 A_RXDN12 A_SD12
A
17C7> 17C5< 17B5< 17B7<
CHASS1 CHASS2 VEET VEER
1
GND1
7
GND1
7
B A A
B A
A
PMC-Sierra, Inc.
A DRAWING TITLE=OPTICS_CARD ABBREV=OPTICS_CARD LAST_MODIFIED=Thu Dec 14 10:37:51 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI 16X155 REFERENCE DESIGN OPTICS DAUGHTER CARD ENGINEER: BDV 2 ISSUE DATE: A
REVISION NUMBER: 1.0 PAGE:16 1 OF 17
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
10UF
3.3VD
100NH C167 10UF 0.1UF L9 C165 C166 0.1UF
3.3VD
100NH C172 0.1UF 0.1UF L11 C170 C171
G
+
+
A_TXDP13 A
17B7>
A_TXDP15 A
17B7>
A
A
49.9 R79 100NH C168 0.1UF L10
A
A
49.9 L12 R86 100NH C173 0.1UF
VBB_B
C169 0.1UF
VBB_B
C174 0.1UF
A
49.9 6 2
A
49.9 6 2
U18
13 14 15 16 11 12
R80
U19 A_TXDN13 A_RXDP13 A_RXDN13 A_SD13
13 14 15 16 11 12
A
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R77 150 R78 150 150 R81
A
17B7>
A
17B5< 17B5< 17B5<
GND GND GND GND
VCCT VCCR 3.3V HFBR5905
TXDP TXDN RXDP RXDN SD TDIS
9 10 5 4 3 8 R84 150 R85 150 150 R88
R87
F
F
A
A_TXDN15 A_RXDP15 A_RXDN15 A_SD15
17B7> 17B5< 17B5< 17B7<
CHASS1 CHASS2 VEET VEER
1
CHASS1 CHASS2 VEET VEER
1
GND1
GND1
7
7
A E A
A A E
D
D
J8 C PLACE MOUNTING HOLES ON CORNERS OF ADD ON BOARD TO MOUNT TO MAIN BOARD
16G6< 16F6< 16G2< 16F2< 16F2> 16D6< 16C6< 16C2< 16C2< 16B2> 17G7< 17F7< 17G2< 17F2< 17F2>
C A_TXDP8 A_TXDN8 A_TXDP10 A_TXDN10 A_SD10 A_TXDP11 A_TXDN11 A_TXDP12 A_TXDN12 A_SD12 A_TXDP13 A_TXDN13 A_TXDP15 A_TXDN15 A_SD15 3.3VD
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
B
P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 P33 P35 P37 P39
P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38 P40
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
A_RXDP8 A_RXDN8 A_SD8 A_RXDP10 A_RXDN10 A_RXDP11 A_RXDN11 A_SD11 A_RXDP12 A_RXDN12 A_RXDP13 A_RXDN13 A_SD13 A_RXDP15 A_RXDN15 3.3VD
16F6> 16F6> 16F6> 16F2> 16F2> 16C6> 16B6> 16B6> 16B2> 16B2> 17F7> 17F7> 17F7> 17F2> 17F2>
B
GND1 GND2 GND3 GND4
HISPD_RECEPTACLE20X2
A
A
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000506 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=OPTICS_CARD ABBREV=OPTICS_CARD LAST_MODIFIED=Thu Dec 14 10:37:54 2000 10 9 8 7 6 5 4 3 TITLE: S/UNI 16X155 REFERENCE DESIGN OPTICS DAUGHTER CARD ENGINEER: BDV 2 ISSUE DATE: A
REVISION NUMBER: 1.0 PAGE:17 1 OF 17
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
10
PCB LAYOUT REVISION 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
65
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
11
BILL OF MATERIALS (BOM) REVISION 1
Manufacturer Ref Des PANASONIC C70 Description Qty Part Name - Value CAP CERAMIC X7R 0603 50V 0.01UF CAP CERAMIC X7R 0603 16V 0.1UF Value Build
NO Part Number . 1 ECUV1H103KBV
1 CAPS-0.01UF, 50V, 0.01UF 16x155 X7R_603
2 ECJ1VB1C104K
PANASONIC C61, C65, C85, C86, C88, C90, C92, C94, C95, C97, C98, C100, C101, C103, C104, C106, C107, C109, C110, C112, C113, C116, C137C143, C146C154, C166C169, C171C174, C182C199, C205, C206, C209C212, C214C217, C219C222, C226, C231, C232, C236, C238C241, C244, C246,
116 CAPS-0.1UF, 16V, X7R_603
0.1UF 16x155
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
66
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
3 ECST0JY106R
4 HFBR-5905
C247, C250, C254C264, C266, C268C271, C273C276, C278C283 PANASONIC C79, C83, C144, C145, C165, C170, C179C181, C202, C203, C224, C242 HEWLETT U8, U14PACKARD U19, U22U25, U30, U32, U34, U35, U37 J9
CAP TANCAPA 6.3V 20% 10UF
13 CAPS_POL-10UF, 6.3V, TANCAPA
10UF
16x155
5 QSE-020-01- SAMTEC F-D
6 QTE-020-03- SAMTEC F-D
J8
7 DIGI-KEY -- PANASONIC L1-L18, L21-L24, PCD1172CTL27, L28, ND L31, L32 8 ERJPANASONIC R89 RES 0603 3GSYJ103V 1/16W 5% 10K OHM 9 ERJPANASONIC R116 RES 0603
3.3V ATM TRANSCEI VER SONET OC-3/SDH STM-1 CONNECT OR, SMD 2ROW, 20 POSITION/ ROW, WITH GND RECEPTA CLE FOR QSE HISPD CONNECT OR, SMD 2ROW, 20 POSITION/ ROW, WITH GND 1.81
16 HFBR5905-3.3V
3.3V
16x155
1 HISPD_HEADER20 ? X2_QSE -BASE
16x155
1 HISPD_RECEPTAC ? LE20X2 _QTEBASE
16x155
26 INDUCTOR-100NH, 100NH 16x155 , PANASONIC 1 RES-10K, 5%, 603 1 RES-124, 1%, 603 10K 16x155
124 16x155
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
67
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
3EKF1240V 10 ERJ3EKF1500V PANASONIC
11 ERJ3GSYJ221V 12 ERJ3GSYJ331V 13 ERJ3EKF49R9V
PANASONIC
PANASONIC
PANASONIC
14 ERJ-
PANASONIC
1/16W 1% 124 OHM R34, R35, RES 0603 R37, R39, 1/16W 1% R46, R47, 150 OHM R52, R53, R63, R68, R69, R72, R77, R78, R81, R84, R85, R88, R92-R96, R101, R117, R118, R124, R173, R175, R178, R180, R185, R186, R204, R206, R212, R233, R235, R239 R48, R75, RES 0603 1/16W 5% R187, 220 OHM R218, R245 R49, R76, RES 0603 R188, 1/16W 5% R219, 330 OHM R246 R41, R43- RES 0603 R45, R64, 1/16W 1% R67, R70, 49.9 OHM R71, R79, R80, R86, R87, R97R100, R122, R123, R181R184, R209, R210, R236, R237 R115 RES 0603
39 RES-150, 1%, 603
150 16x155
5 RES-220, 5%, 603
220 16x155
5 RES-330, 5%, 603
330 16x155
26 RES-49.9, 1%, 603
49.9 16x155
1 RES-82.5, 1%, 603
82.5 16x155
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
68
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
1/16W 1% 82.5 OHM 15 NU NU R74, R82 RES NOT USED ON BOARD 0603 PACKAGE 16 NU NU R141, RES NOT R147, USED ON R150, BOARD R153 0805 PACKAGE ? R15717 DIGI-KEY -- ? R160, PC R163, CT-ND R164, R193R198, R224R227, R249R252, R255, R256, R258, R259, R268, R270R272, R277R280 ? 18 PANASONIC ? RN86, -- EXBRN87, V8V472JV RN90, RN91 19 131-3701-341 JOHNSON J6, J7 50 OHM COMPONEN RIGHT TS ANGLE BULKHEA D JACK RECEPTA CLE 20 PM5382 PMC U9 IC S/UNI 15X155 SIERRA SATURN USER NETWORK INTERFAC E(16X155) 21 08055C473JA AVX C200, CAP TN C218, CERAMIC C265, X7R 0850 C267 50V
3EKF82R5V
2 RES-NU, NU, NU_603
NU
16x155
4 RES-NU, NU, NU_805
NU
16x155
32 RESISTOR-158, 1%, 805
158 16x155
4 RES_ARRAY_4_S MD-4.7K
4.7K
16x155
2 SMB_RIGHT_ANGL ? E-BASE
16x155
1 SUNI16X155_SBG ? A-BASE
16x155
4 CAPS-0.047UF, 50V, X7R_805
0.047U 4X622 F
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
69
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
22 ECJ1VB1C104K
PANASONIC
23 GRM42MURATA 2X5R106K10 24 ECST0JY106R 25 ECSH0JD476R PANASONIC
PANASONIC
26 HFCT-5908E HP
27 DIGI-KEY -- PANASONIC PCD1172CTND 28 ERJPANASONIC R125, 6GEY0R00V R142, R230, R231 29 ERJPANASONIC R213, 3EKF1500V R214, R217 30 ERJPANASONIC R199 3EKF2001V 31 ERJ3GSYJ4R7V
0.047UF C87, C89, CAP C91, C93, CERAMIC C96, C99, X7R 0603 16V 0.1UF C102, C105, C108, C111, C125, C128, C134C136, C228, C233, C234, C237 CAP C120, CERAMIC C122, X5R 1210 C132, 10V 10UF C133 C227 CAP TANCAPA 6.3V 20% 10UF CAP C80, TANCAPD C114, 6.3V 20% C130, 47UF C131 U36 ATM FIBER TRANSCEI VERS FOR SONET OC12/SDH STM-4 2X5 PACKGE L29, L30 1.81
19 CAPS-0.1UF, 16V, X7R_603
0.1UF 4X622
4 CAPS-10UF, 10V, X5R_1210 1 CAPS_POL-10UF, 6.3V, TANCAPA 4 CAPS_POL-47UF, 6.3V, TANCAPD
10UF
4X622
10UF
4X622
47UF
4X622
1 HFCT5908E_THRU HFCT- 4X622 -BASE 5908E
2 INDUCTOR-100NH, 100NH 4X622 , PANASONIC 4 RES-0, 5%, 805 0 4X622
RES 0805 1/10W 5% ZERO OHM RES 0603 1/16W 1% 150 OHM RES 0603 1/16W 5% 2.00K OHM PANASONIC R54, R55, RES 0603 R60, R61 1/16W 5%
3 RES-150, 1%, 603 1 RES-2.00K, 1%, 603 4 RES-4.7, 5%, 603
150 4X622 2.00K 4X622
4.7 4X622
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
70
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
32 ERJ3EKF49R9V 33 ERJ3EKF63R4V 34 NU
PANASONIC R215, R216 PANASONIC R222 NU R83
35 NU
NU
R148, R149, R154, R155
36 MC100LVEL1 MOTOROLA U13 6D
37 PI49FCT3807 PERICOM CQ
U10
38 SN74AHC1G TI 08DCKR 39 120673-1 AMP
U4
J10-J12
40 ECUV1H103KBV
PANASONIC C7
41 ECUPANASONIC C8 V1H473KBW
42 ECJ-
PANASONIC C1-C6,
4.7 OHM RES 0603 1/16W 1% 49.9 OHM RES 0603 1/16W 1% 63.4 OHM RES NOT USED ON BOARD 0603 PACKAGE RES NOT USED ON BOARD 0805 PACKAGE IC DIFFEREN TIAL RECEIVER SOIC 8 IC 3.3V 1:10 CMOS CLOCK DRIVER QSOP20 C GRADE IC SINGLE 2-INPUT POSITIVE AND GATE Z-PACK 6 ROW HS3 BACKPLA NE CONNECT OR, RIGHT ANGLE RECEPTA CLE CAP CERAMIC X7R 0603 50V 0.01UF CAP CERAMIC X7R 1206 50V 0.047UF CAP
2 RES-49.9, 1%, 603 1 RES-63.4, 1%, 603 1 RES-NU, NU, NU_603
49.9 4X622 63.4 4X622 NU 4X622
4 RES-NU, NU, NU_805
NU
4X622
1 100LVEL16_SOIC- ? BASE
BOTH
1 49FCT3807_QSOP ? 20_C-B ASE
BOTH
1 74AHC1G08_DCK- ? BASE 3 AMP_HS3_6X10_F ? EMALE_ RA
BOTH
BOTH
1 CAPS-0.01UF, 50V, 0.01UF BOTH X7R_603
1 CAPS-0.047UF, 50V, X7R_1206
0.047U BOTH F
78 CAPS-0.1UF, 16V,
0.1UF BOTH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
71
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
C10-C46, C57, C64, C66-C69, C72, C82, C117, C124, C126, C127, C129, C155C158, C160, C161, C163, C164, C176, C178, C204, C207, C208, C213, C225, C229, C230, C235, C245, C248, C249, C251 43 GRM42MURATA C71, C73, 2X5R106K10 C115, C118, C119, C121, C123, C159, C162 44 ECSPANASONIC C47-C55 H1CC106R 45 ECST0JY106R
1VB1C104K
CERAMIC X7R 0603 16V 0.1UF
X7R_603
CAP CERAMIC X5R 1210 10V 10UF
9 CAPS-10UF, 10V, X5R_1210
10UF
BOTH
CAP TANCAPC 16V 20% 10UF PANASONIC C58, C60, CAP C63, C75- TANCAPA C78, C81, 6.3V 20% 10UF C84, C175, C177, C201, C223, C243, C272, C277
9 CAPS_POL-10UF, 16V, TANCAPC 16 CAPS_POL-10UF, 6.3V, TANCAPA
10UF
BOTH
10UF
BOTH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
72
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
CAP ELECTRO VA SMD 10V 20% 220UF 47 ECSPANASONIC C56, C59, CAP H0JD476R C62, C74 TANCAPD 6.3V 20% 47UF 48 DL4148MS MICROSEMI D5 DIODE RECT 150MA 75V SMT MINIMELF J5 CONN 49 PZC36SAAN SULLINS HEADER ELECTRONI STRAIGHT CS 36POS MALE .1" SINGLE ROW 50 PZC36DAAN SULLINS J2 CONN HEADER 2 ROW 0.1"X0.1" 2X16 J4 CONN 51 PZC36DAAN SULLINS HEADER ELECTRONI STRAIGHT CS 6POS MALE .1" DUAL ROW 3X2 52 DIGI-KEY ? J3 100 MIL S1011-36-ND SPACING HEADER 53 QSE-020-01- SAMTEC J13, J14 CONNECT F-D OR, SMD 2ROW, 20 POSITION/ ROW, WITH GND 54 DIGI-KEY -- PANASONIC L19, L20, 1.81 PCD1172CTL25, L26, ND L33, L34 IC POWER 55 IRF7413 INTERNATIO Q1, Q2 MOSFET NA L RECTIFIER 56 LP3966ESNATIONAL U12 3A FAST 1.8 SEMI ULTRA LOW DROPOUT
46 ECEV1AA221P
PANASONIC C9
1 CAPS_POL-220UF, 220UF BOTH 10V, ELECTRO VA A 4 CAPS_POL-47UF, 6.3V, TANCAPD 1 DL4148_SOD80CBASE 47UF BOTH
?
BOTH
1 HEADER6_100MIL- ? BASE
BOTH
1 HEADER_16X2_CO ? NN_MAL E-BASE
BOTH
1 HEADER_3X2_100 HEAD BOTH MIL-BA SE ER 3X2
1 HEADER_9_100 MIL-BASE
?
BOTH BOTH
2 HISPD_HEADER20 ? X2_QSE -BASE
6 INDUCTOR-100NH, 100NH BOTH , PANASONIC 2 IRF7413_SOICBASE 1 LP3966ES1_8_SMT_REG BASE ? ? BOTH BOTH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
73
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
57 LP3966ES2.5
NATIONAL SEMI
U33
58 LT1117CST
U3 LINEAR TECHNOLO GIES
59 LT1129CQ3.3
U27 LINEAR TECHNOLO GIES
U2 60 LTC1643L1C LINEAR GN TECHNOLO GY
61 LTC1728ES5- LINEAR U26 5 TECHNOLO GY
62 MAX811TEU MAXIM S-T
U6
63 MC100LVEL1 MOTOROLA U31 7DW
LINEAR REGULAT OR 1.8V TO263-5 3A FAST ULTRA LOW DROPOUT LINEAR REGULAT OR 2.5V TO263-5 REGULAT OR ADJUSTAB LE SOT223 800MA OUTPUT REGULAT OR 3.3V FIXED MICROPO WER LOW DROPOUT IC CPCI HOT SWAP CONTROL LER W/ 12V POWERGD DISABLED DISCRETE MICROPO WER PRECISIO N TRIPLE SUPPLY MONITOR S SOT23-5 IC 4 PIN UP VOLTAGE MONITOR WITH MANUAL RESET INPUT 3.08V SOT143 QUAD LV PECL
1 LP3966ES2_5_SMT_REG BASE
?
BOTH
1 LT1117CST_SOTADJ
ADJ
BOTH
1 LT1129CQ3_TO263-3.3 V
3.3V
BOTH
1 LTC1643L_SSOP1-BASE
?
BOTH
1 LTC1728ES5_5_SO ? IC-BA SE
BOTH
1 MAX811T_SOT143- ? BASE
BOTH
1 MC100LVEL17DW_ ? SOIC20 -BASE
BOTH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
74
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
64 MC100LVELT 22D
65 614-93-30831-012
66 MMD MB3100HH100.000M HZ
67 CONNOR WINFIELD -EE14-541 68 DIGIKEY -CKN4002-ND
69 PCI9054AB50PI 70 WSL2512R01-1 71 ERJ3GSYJ1R0V 72 ERJ3GSYJ122V 73 ERJ3GSYJ100V 74 ERJ3EKF1000V
DIFFEREN TIAL LINE RECEIVER IC DUAL MOTOROLA U28 DIFFEREN SEMICONDU TIAL CTO R LVTTL/LVC MOS TO LVPECL TRANSLAT OR SOIC8 MILL MAX U1 SOCKET FOR PART# NM93CS66 LEN ? U20 ? Y1 77.76 MHZ, LVPECL OSCILLAT OR, 20 PPM, 3.3V ? SW1 RIGHT ANGLE PCB MOUNT SPST PUSH BUTTOM U11 IC PCI-TOPLX LOCAL TECHNOLO BUS GY VISHAY R5, R14, RES 2512 R15 1W 1% 0.01 OHM PANASONIC R17 RES 0603 1/16W 5% 1 OHM PANASONIC R2, R21 RES 0603 1/16W 5% 1.2K OHM RES 0603 PANASONIC R6, R8, R29, R65, 1/16W 5% R66, R90 10 OHM PANASONIC R9, R120, RES 0603 1/16W 1% R121, 100 OHM R152
1 MC100LVELT22D_ ? SOIC8- BASE
BOTH
1 NM93CS66LEN_DI ? P8_SOC KETBASE
BOTH
1 OSC_CMOS_8PIN_ 100.00 BOTH DUAL-H CMOS, 0MHZ 100.0A
1 OSC_PECL_3.3V- 77.76 77.76M HZ, 20 PPM MHZ
BOTH
1 PBNO_RIGHT_AN GLE-BAS E
?
BOTH
1 PCI9054_PQFPBASE 3 RES-0.01, 1%, 2512 1 RES-1, 5%, 603
?
BOTH 0.01 BOTH 1 BOTH BOTH 10 BOTH 100 BOTH
2 RES-1.2K, 5%, 603 1.2K 6 RES-10, 5%, 603 4 RES-100, 1%, 603
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
75
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
75 ERJ3GSYJ104V 76 ERJ3GSYJ103V 77 ERJ8GEYJ106V 78 ERJ3GSYJ131V 79 ERJ3GSYJ150V 80 ERJ3EKF1500V
PANASONIC R28 PANASONIC R33 PANASONIC R1, R30, R31 PANASONIC R24 PANASONIC R56, R57, R59
81 ERJ3EKF2001V 82 ERJ3GSYJ202V 83 ERJ3GSYJ222V 84 ERJ6GEYJ240V 85 ERJ3GSYJ330V 86 ERJ3GSYJ331V 87 ERJ3EKF39R2V
PANASONIC R10, R18, R36, R38, R40, R42, R50, R126R128, R131R135, R172, R174, R179, R203, R205, R211, R234, R238, R242 PANASONIC R129 RES 0603 1/16W 5% 2.00K OHM PANASONIC R3, R4 RES 0603 1/16W 5% 2.0K OHM PANASONIC R22, R73 RES 0603 1/16W 5% 2.2K OHM PANASONIC R23 RES 0805 1/10W 5% 24 OHM PANASONIC R32, RES 0603 R112 1/16W 5% 33 OHM PANASONIC R91, RES 0603 R114 1/16W 5% 330 OHM PANASONIC R16 RES 0603 1/16W 1%
RES 0603 1/16W 5% 100K OHM RES 0603 1/16W 5% 10K OHM RES 1206 1/8W 5% 10M OHM RES 0603 1/16W 5% 130 OHM RES 0603 1/16W 5% 15 OHM RES 0603 1/16W 1% 150 OHM
1 RES-100K, 5%, 603 100K 1 RES-10K, 5%, 603 10K
BOTH BOTH BOTH
3 RES-10M, 5%, 1206 10M 1 RES-130, 5%, 603 3 RES-15, 5%, 603 24 RES-150, 1%, 603
130 BOTH 15 BOTH 150 BOTH
1 RES-2.00K, 1%, 603
2.00K
BOTH BOTH BOTH
2 RES-2.0K, 5%, 603 2.0K 2 RES-2.2K, 5%, 603 2.2K 1 RES-24, 5%, 805 2 RES-33, 5%, 603 2 RES-330, 5%, 603 1 RES-39.2, 1%, 603
24 BOTH 33 BOTH 330 BOTH 39.2 BOTH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
76
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
88 ERJ3GSYJ4R7V 89 ERJ3GSYJ472V
PANASONIC PANASONIC
90 ERJ3EKF49R9V
PANASONIC
91 ERJ3GSYJ560V 92 ERJ3GSYJ561V 93 ERJ3EKF63R4V
PANASONIC PANASONIC PANASONIC
94 NU
NU
95 DIGI-KEY -- ? PE CT-ND 96 PANASONIC ? -- EXBV8V100JV
39.2 OHM R58 RES 0603 1/16W 5% 4.7 OHM R7, R19, RES 0603 R20, R25, 1/16W 5% R26, R51, 4.7K OHM R130, R136, R143, R151, R283, R284 RES 0603 R62, 1/16W 1% R102, 49.9 OHM R104, R105, R107, R108, R110, R111, R119, R176, R177, R207, R208, R240, R241 R27 RES 0603 1/16W 5% 56 OHM R12, R13 RES 0603 1/16W 5% 560 OHM RES 0603 R11, 1/16W 1% R103, 63.4 OHM R106, R109, R113 R144, RES NOT R145 USED ON BOARD 0603 PACKAGE R137? R140 RN37, RN38, RN40, RN42, RN48, ?
1 RES-4.7, 5%, 603
4.7 BOTH BOTH
12 RES-4.7K, 5%, 603 4.7K
15 RES-49.9, 1%, 603
49.9 BOTH
1 RES-56, 5%, 603 2 RES-560, 5%, 603 5 RES-63.4, 1%, 603
56 BOTH 560 BOTH 63.4 BOTH
2 RES-NU, NU, NU_603
NU
BOTH
4 RESISTOR-10, 5%, 1206 13 RES_ARRAY_4_S MD-10
10 BOTH BOTH RES ARRA Y_4 5% 10 OHM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
77
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
97 PANASONIC ? -- EXBV8V103JV
98 PANASONIC ? -- EXBV8V102JV 99 PANASONIC ? -- EXBV8V330JV
RN49, RN52, RN55RN57, RN62RN64 RN27, RN35, RN36, RN43, RN45RN47, RN53, RN54, RN58, RN60, RN61, RN65 RN44, RN59
?
13 RES_ARRAY_4_S MD-10K
BOTH RES ARRA Y_4 5% 10K OHM
?
2 RES_ARRAY_4_S MD-1K
10 PANASONIC ? 0 -- EXBV8V472JV 10 750101R200 1 CTS
10 SSFLUMEX 2 LXH5147LGD
? RN7, RN8, RN10RN15, RN23, RN28RN33, RN39, RN41, RN50, RN66RN69, RN71RN84, RN88, RN89 RN1-RN5, ? RN16, RN34, RN51, RN85 RN6 BUSSED RESISTOR NETWORK 200 OHM SIP10 D2-D4 LED QUAD GREEN HORIZONT
38 RES_ARRAY_4_S MD-33
BOTH RES ARRA Y_4 5% 1K OHM BOTH RES ARRA Y_4 5% 33 OHM
9 RES_ARRAY_4_S MD-4.7K
4.7K
BOTH
1 RSIP9-200
200 BOTH
3 SSF_LXH5147GREEN
GREE BOTH N
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
78
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
10 SY100EL57L SYNERGY 3 ZC
U29
10 UNR-3.3/8-D5 DATEL 4
U21
10 540-99-0445 17-400 000
U7 MILL MAX MANUFACT URIN G
10 XCV200E6 6BG352C
XILINX
U5
10 ZM4742A 7
DIODES INC D1
10 352068-1 8
AMP
J1
AL 4:1 DIFFEREN TIAL MULTIPLE XER DC/DC CONVERT ER, 5V TO 3.3V, 26W, 8 AMP IC CONFIGU RABLE OTP EPROM PLCC44 SOCKETE D IC HIGH DENSITY 1.8V VIRTEX FPGA (352BGA PACKAGE) ZENER DIODE 12.0V 5% 1.0W SURFACE MOUNT CONNECT OR ZPACK CPCI 2MM HM 110 POS. TYPE A WITH GND SHIELD
1 SY100EL57L_SOIC ? -BASE
BOTH
1 UNR3V5-8-D5
8-D5
BOTH
1 XC1702L_PC44C_ ? SOCKET -BASE
BOTH
1 XCV200E6BG352C_BGABASE
?
BOTH
1 ZENERDIODE12.0V_1W
12.0V_ BOTH 1W
1 ZPACK5X22FH_AS ? CPCI_2 MM
BOTH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
79
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
80
PRELIMINARY REFERENCE DESIGN PMC-2000506 ISSUE 1
PM5382 - S/UNI 16X155
S/UNI-16X155 REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2000506(P1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 81

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