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| a FEATURES Low Cost Low Power 2.0 W @ 2.5 V (Outputs Enabled) <100 mW @ 2.5 V (Outputs Disabled) 34 34, Fully Differential, Nonblocking Array 3.2 Gbps per Port NRZ Data Rate Wide Power Supply Range: 2.5 V to 3.3 V LVTTL or LVCMOS Level Control Inputs: @ 2.5 V to 3.3 V Low Jitter: 45 ps Drives a Backplane Directly Programmable Output Swing 100 mV to 1.6 V Differential 50 On-Chip I/O Termination User Controlled Voltage at the Load Minimizes Power Dissipation Dual Rank Latches Available in 256-Ball Grid Array 34 34, 3.2 Gbps Asynchronous Digital Crosspoint Switch AD8152* FUNCTIONAL BLOCK DIAGRAM VCC 34 INP VTTI 34 INN 34 OUTP 34 34 DIFFERENTIAL SWITCH MATRIX OUTPUT LEVEL DACs VTTO 34 OUTN D[5:0] MATRIX CONNECTION LATCHES CONNECTION DECODE OUTPUT LEVEL LATCHES RESET CS A[6:0] RE WE UPDATE VEE CONTROL LOGIC AD8152 APPLICATIONS Fiber Optic Network Switching High Speed Serial Backplane Routing to OC-48 with FEC Gigabit Ethernet Digital Video (HDTV) Data Storage Networks GENERAL DESCRIPTION AD8152 is a member of the Xstream line of products and is a breakthrough in digital switching, offering a large switch array (34 x 34) on very little power, typically 2.0 W. Additionally, it operates at data rates up to 3.2 Gbps per port, making it suitable for Sonet/SDH OC-48 with Forward Error Correction (FEC). The AD8152's useful supply voltage range allows the user to operate at LVPECL/CML data levels down to 2.5 V. The control interface is LVTTL or LVCMOS compatible on 2.5 V to 3.3 V. The AD8152's fully differential signal path reduces jitter and crosstalk while allowing the use of smaller single-ended voltage swings. It is offered in a 256-ball SBGA package that operates over the industrial temperature range of 0C to 85C. 100mV/DIV 80ps/DIV Figure 1. Eye Pattern, 3.2 Gbps, PRBS 23 *Patent Pending REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD8152 ELECTRICAL CHARACTERISTICS unless otherwise noted.) Parameter DYNAMIC PERFORMANCE Max Data Rate/Channel (NRZ) Channel Jitter RMS Channel Jitter Propagation Delay Propagation Delay Match Output Rise/Fall Time INPUT CHARACTERISTICS Input Voltage Swing Input Voltage Range Input Bias Current Input Capacitance OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Range Output Current Output Capacitance TERMINATION CHARACTERISTICS Resistance Temperature Coefficient POWER SUPPLY Operating Range VCC Quiescent Current VCC VEE Condition (@ 25 C, VCC = 2.5 V to 3.3 V, VEE = 0 V, RL = 50 , Differential Output Swing = 800 mV p-p, Min 3.2 Typ Max Unit Gbps ps p-p ps ps ps ps mV p-p V mA pF mV p-p V mA pF W W/C Data Rate 3.2 Gbps; PRBS 223 - 1 Input to Output 20% to 80% Single-Ended (See TPC 14) Common-Mode (See TPC 15) 45 <10 660 50 100 50 VEE + 0.8 2 2 800 120 1000 VCC + 0.2 Differential (See TPC 18) 100 800 VCC - 1.2 2 2 43 50 0.05 1600 VCC + 0.2 32 57 VEE = 0 V All Outputs Disabled All Outputs Enabled All Outputs Disabled All Outputs Enabled TMIN to TMAX, All Outputs Enabled VCC = 3.3 V VCC = 3.3 V VCC = 2.5 V VCC = 2.5 V VCC = 3.3 V, IOH = -2 mA VCC = 3.3 V, IOL = +2 mA VCC = 2.5 V, IOH = -100 uA VCC = 2.5 V, IOL = +100 uA 2.25 32 190 32 770 800 2 3.63 45 45 V mA mA mA mA mA V V V V V V V V C C/W C/W C/W LOGIC INPUT CHARACTERISTICS Input High (VIH) Input Low (VIL) Input High (VIH) Input Low (VIL) LOGIC OUTPUT CHARACTERISTICS Output High (VOH) Output Low (VOL) Output High (VOH) Output Low (VOL) THERMAL CHARACTERISTICS Operating Temperature Range JA 0.8 1.7 0.7 2.4 0.4 2.1 0.2 0 85 15 12 11 Still Air 200 lfpm 400 lfpm Specifications subject to change without notice. -2- REV. A AD8152 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION - W 16 Tj = 150 C 14 12 400 lfpm 10 200 lfpm 8 STILL AIR 6 4 2 0 VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 V VTTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V VTTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V Internal Power Dissipation2 AD8152 256-Ball SBGA (BP) . . . . . . . . . . . . . . . . . . 8.33 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.6 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.7 V Logic Input Voltage . . . . . . VEE - 0.3 V < VIN < VCC + 0.6 V Storage Temperature Range . . . . . . . . . . . . . -65C to +125C Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . 300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for the device in free air (T A = 25C): JA = 15C/W @ still air. 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C 80 90 Figure 2. Maximum Power Dissipation vs. Temperature MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8152 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 2. ORDERING GUIDE Model AD8152JBP AD8152-EVAL Temperature Range 0C to 85C Package Description 256-Ball SBGA (27 mm x 27 mm) Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8152 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A -3- AD8152 BALL GRID ARRAY 20 A VEE 19 VEE 18 VEE 17 VEE 16 VCC 15 VTTO 14 O14P 13 VTTO 12 O11P 11 VCC 10 O08P 9 VTTO 8 O05P 7 VTTO 6 O02P 5 VTTO 4 VCC 3 VEE 2 VEE 1 VEE A B VEE VEE VEE VEE VCC VTTO O14N VTTO O11N VCC O08N VTTO O05N VTTO O02N VTTO VCC VEE VEE VEE B C VEE VEE D4 D5 O16N O15P O13N O12P O10N O09P O07N O06P O04N O03P O01N O00P A6 A5 VEE VEE C D D0 D1 D2 D3 O16P O15N O13P O12N O10P O09N O07P O06N O04P O03N O01P O00N A4 A3 A2 A1 D E CS RESET N/C N/C N/C N/C UPDATE A0 E F VCC RE I17P I17N I00N I00P WE VCC F G I19P I19N I18N I18P I01P I01N I02N I02P G H VTTI VTTI I20P I20N I03N I03P VTTI VTTI H J I22P I22N I21N I21P I04P I04N I05N I05P J K VTTI VTTI I23P I23N I06N I06P VTTI VTTI K L I25P I25N I24N I24P I07P I07N I08N I08P L M VCC VCC I26P I26N I09N I09P VCC VCC M N I28P I28N I27N I27P I10P I10N I11N I11P N P VTTI VTTI I29P I29N I12N I12P VTTI VTTI P R I31P I31N I30N I30P I13P I13N I14N I14P R T VTTI VTTI I32P I32N I15N I15P VTTI VTTI T U VCC VCC I33N I33P O33P O32N O30P O29N O27P O26N O24P O23N O21P O20N O18P O17N I16P I16N VCC VCC U V VEE VEE VEE VEE O33N O32P O30N O29P O27N O26P O24N O23P O21N O20P O18N O17P VEE VEE VEE VEE V W VEE VEE VEE VEE VCC VTTO O31N VTTO O28N VCC O25N VTTO O22N VTTO O19N VTTO VCC VEE VEE VEE W Y VEE VEE VEE VEE VCC VTTO O31P VTTO O28P VCC O25P VTTO O22P VTTO O19P VTTO VCC VEE VEE VEE Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Ball Diagram, View from the Bottom -4- REV. A AD8152 BALL GRID DESCRIPTIONS Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 Mnemonic VEE VEE VEE VCC VTTO OUT02P VTTO OUT05P VTTO OUT08P VCC OUT11P VTTO OUT14P VTTO VCC VEE VEE VEE VEE VEE VEE VEE VCC VTTO OUT02N VTTO OUT05N VTTO OUT08N VCC OUT11N VTTO OUT14N VTTO VCC VEE VEE VEE VEE VEE VEE A5 A6 OUT00P OUT01N OUT03P OUT04N OUT06P OUT07N OUT09P Type Power Power Power Power Power I/O Power I/O Power I/O Power I/O Power I/O Power Power Power Power Power Power Power Power Power Power Power I/O Power I/O Power I/O Power I/O Power I/O Power Power Power Power Power Power Power Power Control Control I/O I/O I/O I/O I/O I/O I/O Description Negative Supply Negative Supply Negative Supply Positive Supply Output Termination Supply High Speed Output Output Termination Supply High Speed Output Output Termination Supply High Speed Output Positive Supply High Speed Output Output Termination Supply High Speed Output Output Termination Supply Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Positive Supply Output Termination Supply High Speed Output Complement Output Termination Supply High Speed Output Complement Output Termination Supply High Speed Output Complement Positive Supply High Speed Output Complement Output Termination Supply High Speed Output Complement Output Termination Supply Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Output Address Pin (MSB) Output Address Pin (Bank Des.) High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output -5- Ball C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 Mnemonic OUT10N OUT12P OUT13N OUT15P OUT16N D5 D4 VEE VEE A1 A2 A3 A4 OUT00N OUT01P OUT03N OUT04P OUT06N OUT07P OUT09N OUT10P OUT12N OUT13P OUT15N OUT16P D3 D2 D1 D0 A0 UPDATE N/C Reserved N/C Reserved N/C Reserved N/C Reserved RESET CS VCC WE IN00P IN00N IN17N IN17P RE VCC IN02P IN02N IN01N IN01P IN18P IN18N Type I/O I/O I/O I/O I/O Control Control Power Power Control Control Control Control I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Control Control Control Control Control Control Control Control Power Control I/O I/O I/O I/O Control Power I/O I/O I/O I/O I/O I/O Description High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement Input Address Pin (MSB) Input Address Pin Negative Supply Negative Supply Output Address Pin Output Address Pin Output Address Pin Output Address Pin High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output Input Address Pin Input Address Pin Input Address Pin Input Address Pin (LSB) Output Address Pin (LSB) Second Rank Write Enable Do Not Connect Do Not Connect Do Not Connect Do Not Connect Reset/Disable Outputs Chip Select Enable Positive Supply First Rank Write Enable High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Readback Enable Positive Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input High Speed Input High Speed Input Complement REV. A AD8152 BALL GRID DESCRIPTIONS (continued) Ball G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 Mnemonic IN19N IN19P VTTI VTTI IN03P IN03N IN20N IN20P VTTI VTTI IN05P IN05N IN04N IN04P IN21P IN21N IN22N IN22P VTTI VTTI IN06P IN06N IN23N IN23P VTTI VTTI IN08P IN08N IN07N IN07P IN24P IN24N IN25N IN25P VCC VCC IN09P IN09N IN26N IN26P VCC VCC IN11P IN11N IN10N IN10P IN27P IN27N IN28N IN28P VTTI Type I/O I/O Power Power I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O Power Description High Speed Input Complement High Speed Input Input Termination Supply Input Termination Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Input Termination Supply Input Termination Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Input Termination Supply Input Termination Supply High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input Input Termination Supply Input Termination Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Positive Supply Positive Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Positive Supply Positive Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Input Termination Supply -6- Ball P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 Mnemonic VTTI IN12P IN12N IN29N IN29P VTTI VTTI IN14P IN14N IN13N IN13P IN30P IN30N IN31N IN31P VTTI VTTI IN15P IN15N IN32N IN32P VTTI VTTI VCC VCC IN16N IN16P OUT17N OUT18P OUT20N OUT21P OUT23N OUT24P OUT26N OUT27P OUT29N OUT30P OUT32N OUT33P IN33P IN33N VCC VCC VEE VEE VEE VEE OUT17P OUT18N OUT20P OUT21N Type Power I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O Power Power Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Power Power Power Power Power I/O I/O I/O I/O Description Input Termination Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Input Termination Supply Input Termination Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Input Termination Supply Input Termination Supply High Speed Input High Speed Input Complement High Speed Input Complement High Speed Input Input Termination Supply Input Termination Supply Positive Supply Positive Supply High Speed Input Complement High Speed Input High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output High Speed Output High Speed Output Complement High Speed Output High Speed Input High Speed Input Complement Positive Supply Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement REV. A AD8152 BALL GRID DESCRIPTIONS (continued) Ball V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 Mnemonic OUT23P OUT24N OUT26P OUT27N OUT29P OUT30N OUT32P OUT33N VEE VEE VEE VEE VEE VEE VEE VCC VTTO OUT19N VTTO OUT22N VTTO OUT25N VCC OUT28N VTTO OUT31N Type I/O I/O I/O I/O I/O I/O I/O I/O Power Power Power Power Power Power Power Power Power I/O Power I/O Power I/O Power I/O Power I/O Description High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement High Speed Output High Speed Output Complement Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Positive Supply Output Termination Supply High Speed Output Complement Output Termination Supply High Speed Output Complement Output Termination Supply High Speed Output Complement Positive Supply High Speed Output Complement Output Termination Supply High Speed Output Complement Ball W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Mnemonic VTTO VCC VEE VEE VEE VEE VEE VEE VEE VCC VTTO OUT19P VTTO OUT22P VTTO OUT25P VCC OUT28P VTTO OUT31P VTTO VCC VEE VEE VEE VEE Type Power Power Power Power Power Power Power Power Power Power Power I/O Power I/O Power I/O Power I/O Power I/O Power Power Power Power Power Power Description Output Termination Supply Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Negative Supply Positive Supply Output Termination Supply High Speed Output Output Termination Supply High Speed Output Output Termination Supply High Speed Output Positive Supply High Speed Output Output Termination Supply High Speed Output Output Termination Supply Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply REV. A -7- AD8152-Typical Performance Characteristics (2.5 V Supply, VCC = VTTI = VTTO, Data Rate = 3.2 Gbps; PRBS 223-1; Differential Output Swing = 800 mV p-p; RL = 50 ; Input Amplitude = 0.4 V p-p Single-Ended; unless otherwise noted.) 100mV/DIV 80ps/DIV 100mV/DIV 200ps/DIV TPC 1. Eye Pattern 3.2 Gbps TPC 4. Eye Pattern 1.5 Gbps 100mV/DIV 100mV/DIV PEAK-PEAK JITTER = 35ps STD DEV = 5.1ps 20ps/DIV PEAK-PEAK JITTER = 35ps STD DEV = 5.2ps 20ps/DIV TPC 2. Jitter @ 3.2 Gbps TPC 5. Jitter @ 1.5 Gbps 100mV/DIV 1.2ns/DIV 100mV/DIV 2.5ns/DIV TPC 3. Response, 3.2 Gbps, 32-Bit Pattern 1111 1111 0000 0000 1010 1010 1100 1100 TPC 6. Response, 1.5 Gbps, 32-Bit Pattern 1111 1111 0000 0000 1010 1010 1100 1100 -8- REV. A AD8152 1400 BIN WIDTH = 5ps 1200 1000 1.E+00 1.E-01 1.E-02 1.E-03 BIT ERROR RATE 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 FREQUENCY 800 600 400 200 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 1.E-12 -0.5 -0.4 -0.3 -0.2 DUTY CYCLE DISTORTION - ps -0.1 0 0.1 UNIT INTERVAL 0.2 0.3 0.4 0.5 TPC 7. Duty Cycle Distortion Distribution TPC 10. Bit Error Rate vs. Unit Interval 100 90 80 70 EYE HEIGHT - % 60 50 40 30 20 10 0 0.5 1.0 1.5 2.0 2.5 DATA RATE - Gbps 3.0 3.5 4.0 %EYE HEIGHT = VOUT @ DATA RATE VOUT @ 0.5Gbps 100 100mV/DIV PEAK-PEAK JITTER = 35ps STD DEV = 5.6ps TPC 8. Eye Height vs. Data Rate 80ps/DIV TPC 11. Crosstalk, 3.2 Gbps, Attack Signal OFF (See TPC 25) 50 45 40 PEAK-PEAK JITTER 35 JITTER - ps 30 25 20 15 STANDARD DEVIATION 10 5 0 1.0 1.5 2.0 2.5 3.0 DATA RATE - Gbps 3.5 4.0 100mV/DIV TPC 9. Jitter vs. Data Rate PEAK-PEAK JITTER = 46ps STD DEV = 6.5ps 80ps/DIV TPC 12. Crosstalk, 3.2 Gbps, Attack Signal ON (See TPC 25) REV. A -9- AD8152 55 80 70 60 50 PEAK-PEAK JITTER - ps 45 JITTER - ps 1.5 Gbps 40 3.2 Gbps 35 50 PEAK-PEAK JITTER 40 30 20 30 10 STANDARD DEVIATION 25 0 10 20 30 40 50 60 70 80 90 TEMPERATURE - C 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 SUPPLY VOLTAGE - V TPC 13. Single Point Jitter vs. Temperature TPC 16. Jitter vs. Supply 120 160 140 PEAK-PEAK JITTER - ps 100 120 IOUT = 16mA 100 IOUT = 24mA 80 IOUT = 32mA 60 40 20 0 -1.4 80 JITTER - ps 60 PEAK-PEAK JITTER 40 20 STANDARD DEVIATION 0 0 10 100 INPUT AMPLITUDE - mV 1000 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 VOL - V TPC 14. Jitter vs. Single-Ended Input Amplitude TPC 17. Jitter vs. VOL (Relative to VCC) 180 INPUT AMPLITUDE = 50mV p-p 160 140 50 45 40 PEAK-PEAK JITTER PEAK-PEAK JITTER - ps 35 JITTER - ps 120 100 @2.5V 80 60 10 40 20 0.5 STANDARD DEVIATION 5 0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 3.5 3.8 0 0 5 10 15 20 25 30 35 @3.3V 30 25 20 15 INPUT CML - V IOUT - mA TPC 15. Jitter vs. Input Common-Mode Level TPC 18. Jitter vs. Programmed IOUT -10- REV. A AD8152 160 BIN WIDTH = 5ps 140 120 750 725 PROPAGATION DELAY - ps 700 FREQUENCY 100 80 60 40 20 0 600 675 650 625 625 650 675 700 PROPAGATION DELAY - ps 725 750 600 2.0 2.2 2.4 2.6 2.8 3.0 3.2 SUPPLY VOLTAGE - V 3.4 3.6 3.8 TPC 19. Variation in Propagation Delay TPC 21. Propagation Delay vs. Supply 800 780 760 PROPAGATION DELAY - ps 740 IOUT - mA 720 700 680 660 640 620 600 0 10 20 30 40 50 60 TEMPERATURE - C 70 80 90 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 MEASURED IDEAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IOUT CODE TPC 20. Propagation Delay vs. Temperature TPC 22. IOUT vs. IOUT Code REV. A -11- AD8152 VCC PATTERN GENERATOR DATA OUT VTTI VTTO HIGH SPEED SAMPLING OSCILLOSCOPE -6dB 50 -6dB IN##P OUT##P AD8152 DATA OUT TRIGGER OUT VEE = -2.5V -6dB IN##N OUT##N -6dB 50 TRIGGER IN IOUT = 16mA, VOUT HI = 0V, V OUT LO = -0.4V VIN AMPLITUDE = 400mV p-p SINGLE-ENDED, VIN HI = -0.2V PRBS 223 - 1 TPC 23. Negative Supply Test Circuit 2.5V PATTERN GENERATOR DATA OUT VTTI 0.1 F -6dB IN##P OUT##P VCC VTTO 0.1 F -6dB 50 HIGH SPEED SAMPLING OSCILLOSCOPE AD8152 DATA OUT TRIGGER OUT -6dB 0.1 F VEE IOUT = 16mA, VOUT HI = 2.5V, V OUT LO = 2.1V VIN AMPLITUDE = 400mV p-p SINGLE-ENDED, VIN HI = 2.7V PRBS 223- 1, INPUTS AND OUTPUTS ARE AC-COUPLED IN##N OUT##N 0.1 F -6dB 50 TRIGGER IN TPC 24. Positive Supply Test Circuit PATTERN GENERATOR #1 ATTACK SIGNAL DATA OUT -6dB VTTI VCC VTTO IN25P OUT00P...OUT26P OUT28P...OUT33P 50 DATA OUT -6dB IN25N OUT00N...OUT26N OUT28N...OUT33N 50 HIGH SPEED SAMPLING OSCILLOSCOPE PATTERN GENERATOR #2 DATA OUT -6dB AD8152 IN24P OUT27P -6dB 50 DATA OUT TRIGGER OUT VEE = -2.5V TRIGGER IN -6dB IN24N OUT27N -6dB 50 ATTACK SIGNAL APPLIED TO IN25. IN25 BROADCAST TO ALL OUTPUTS EXCEPT OUT27. TWO SEPARATE PATTERN GENERATORS USED TO PROVIDE INPUT PATTERN TO AD8152. OUTPUTS NOT CONNECTED TO OSCILLOSCOPE ARE TERMINATED WITH EXTERNAL 50 TO GND. TPC 25. Crosstalk Test Circuit -12- REV. A AD8152 Table I. Address and Data Buses Connection/Current Bit A6 0 = CONNECTION LATCHES 1 = OUTPUT CURRENT LEVEL Output Address Pins A5 MSB A4 A3 A2 A1 A0 LSB Data Pins D5 MSB D4 D3 D2 D1 D0 LSB Table II. Connection Data and Address Programming Examples Connection/ Current Bit 0 = CONNECTION A6 0 0 0 0 0 0 0 Output Address Pins MSB A5 A4 00 00 10 11 00 10 11 A3 0 0 0 1 0 0 1 A2 0 0 0 1 0 0 1 A1 0 0 0 1 0 0 1 LSB A0 0 0 1 1 0 1 1 Data Pins (Used to Select Inputs) MSB D5 D4 00 10 01 00 11 11 11 D3 0 0 1 0 1 1 1 D2 0 0 1 0 1 1 1 D1 0 0 1 0 1 1 1 LSB D0 0 1 1 0 1 1 1 Comments Program IN00 to OUT00 Program IN33 to OUT00 Program IN31 to OUT33 Broadcast IN00 to All Outputs Disable OUT00 Disable OUT33 Disable All Outputs (Broadcast) Table III. Output-Current Level Data and Address Programming Examples Connection/ Current Bit 1 = CURRENT LEVEL A6 1 1 1 1 Output Address Pins MSB A5 A4 00 00 10 11 LSB A3 A2 A1 A0 0000 0000 0001 1111 Data Pins (Used to Select Inputs) MSB D5 X X X X LSB D4 D3 D2 D1 D0 X0 000 X1 111 X0 111 X1 000 Comments Program OUT00 to Current--Code 00 (2 mA) Program OUT00 to Current--Code 15 (32 mA) Program OUT33 to Current--Code 07 (16 mA) Broadcast Current--Code 08 to All Outputs (18 mA) Table IV. Basic Control Strobe Functions RESET CS 0 1 1 1 1 1 X 1 0 0 0 0 WE X X 0 X X 0 RE X X 1 0 X 1 UPD Function X X X X 0 0 Global Reset. Disables all outputs and resets all output current to code 0111 (16 mA). Disable All Control Signals. Signal matrix/currents remain the same. D5:D0 are high impedance. Write Enable. Write D5:D0 data into first rank register addressed by A6:A0. Single-Output Readback. Second rank register data for output A6:A0 appears on D5:D0. Global Update. Copy all first rank data into second rank registers. Transparent Write and Update. D5:D0 immediately control programming. Use RE as gating signal. REV. A -13- AD8152 CS WE A[6:0]INPUTS D[5:0]INPUTS tCSW tASW tWP tDSW tAHW tAHW CHW tDHW Figure 3a. First Rank Write Cycle Table V. First Rank Write Cycle Symbol tCSW tASW tDSW tCHW tAHW tDHW tWP Setup Time Parameter Chip Select to Write Enable Address to Write Enable Data to Write Enable Chip Select from Write Enable Address from Write Enable Data from Write Enable Conditions TA = 25 C VCC = 3.3 V Min 0 0 1 0 0 0 10 Typ Max Unit ns ns ns ns ns ns ns Hold Time Width of Write Enable Pulse CS UPDATE ENABLING OUT[0:33][N:P] OUTPUTS TOGGLE OUT[0:33][N:P] OUTPUTS DISABLING OUT[0:33][N:P] OUTPUTS DATA FROM RANK 1 PREVIOUS RANK 2 DATA DATA FROM RANK 1 DATA FROM RANK 2 tCSU tUOE tUOD tUOT tUW tCHU Figure 3b. Second Rank Update Cycle Table VI. Second Rank Update Cycle Symbol tCSU tCHU tUOE tUOT tUOD tUW Parameter Setup Time Hold Time Output Enable Times Output Toggle Times Output Disable Times Width of Update Pulse Chip Select to Update Chip Select from Update Update to Output Enable Update to Output Reprogram Update to Output Disabled Conditions TA = 25 C VCC = 3.3 V Min 0 0 Typ Max Unit ns ns ns ns ns ns 25 25 25 10 45 45 45 -14- REV. A AD8152 CS UPDATE WE ENABLING OUT[0:33][N:P] OUTPUTS DISABLING OUT[0:33][N:P] OUTPUTS INPUT {DATA 0} INPUT {DATA 1} INPUT {DATA 2} INPUT {DATA 1} tCSU tUOT tUOE tUW tWOT tWOD tWHU tCHU Figure 4a. Transparent Write and Update Cycle Table VII. Transparent Update Cycle Symbol tCSU tCHU tUOE tWOE* tUOT tWOT tUOD* tWOD tWHU tUW *Not shown Parameter Setup Time Hold Time Output Enable Times Output Toggle Times Output Disable Times Setup Time Width of Update Pulse Chip Select to Update Chip Select from Update Update to Output Enable Write Enable to Output Enable Update to Output Reprogram Write Enable to Output Reprogram Update to Output Disabled Write Enable to Output Disabled Write Enable to Update Conditions TA = 25 C VCC = 3.3 V Min 0 0 Typ Max Unit ns ns 35 35 25 25 25 25 0 10 50 50 45 45 45 45 ns ns ns ns ns ns ns ns CS RE D[5:0] INPUT A[5:0] OUTPUTS ADDR 1 ADDR 2 DATA {ADDR 1} DATA {ADDR 2} tCSR tRDE tAA tRHA tCHR tRDD Figure 4b. Second Rank Readback Cycle Table VIII. Second Rank Readback Cycle Symbol tCSR tCHR tRHA tRDE tAA Setup Time Hold Time Enable Time Access Time Parameter Chip Select to Read Enable Chip Select from Read Enable Address from Read Enable Data from Read Enable Data from Address Conditions TA = 25 C VCC = 3.3 V Min 0 0 5 Typ Max Unit ns ns ns 15 15 30 ns ns REV. A -15- AD8152 RESET DISABLING OUT[0:33][N:P] OUTPUTS tTOD tTW Figure 5. Asynchronous Reset Table IX. Asynchronous Reset Symbol tTOD tTW Disable Time Width of Reset Pulse Parameter Output Disable from Reset Conditions TA = 25 C VCC = 3.3 V Min Typ 10 Max 25 Unit ns ns 10 CONTROL INTERFACE The AD8152 control interface receives and stores the desired connection matrix and output levels for the 34 input and 34 output signal pairs. The interface consists of 34 rows of double-rank 6-bit latches, one for each output. The 6-bit data-word stored in these latches indicates to which (if any) of the 34 inputs the output will be connected, as well as the full-scale output current. One output at a time can be preprogrammed by addressing the output and writing the desired connection data or output current into the first rank of latches. This process can be repeated until each of the desired output changes has been preprogrammed. All output connections can then be programmed at once by passing the data from the first rank of latches into the second rank. The output connections always reflect the data programmed into the second rank of latches and do not change until the first rank of data is passed into the second rank. If necessary for system verification, the data in the second rank of latches can be read back from the control interface. At any time, a reset pulse can be applied to the control interface to globally reset the appropriate second rank data bits, disabling all 34 signal output pairs and resetting the output currents. To facilitate multiple chip address decoding, there is a chip select pin. All logic signals except the reset pulse are ignored unless the chip select pin is active. The chip select pin disables only the control logic interface and does not change the operation of the signal matrix. The chip select pin does not power down any of the latches, so any data programmed in the latches is preserved. All control pins are level-sensitive, not edge-triggered. CONTROL PIN DESCRIPTION A[6:0] Inputs connected to the output specified with the A[5:0] pins. The most significant bit is D5, and the least significant bit is D0. To disable an output completely, the input address D[5:0] = "111111" should be written into the input configuration bank at the desired output address. In write mode, when the bank selection bit A6 is HIGH, the binary encoded data applied to pins D[3:0] indicate the output current level to be used for the output specified with the A[5:0] pins. The reset default is "0111" for 16 mA. Each LSB is 2 mA. In readback mode, pins D[5:0] are low impedance outputs indicating the data-word stored in the second rank for the output specified with the A[5:0] pins and the bank specified with the A6 bit. The readback drivers were designed to drive high impedances only, so external drivers connected to the D[5:0] should be disabled during readback mode. WE Input First rank write enable. Forcing this pin to logic low allows the data on pins D[5:0] to be stored in the first rank latch for the output specified by pins A[6:0]. The WE pin must be returned to a logic high state after a write cycle to avoid overwriting the first rank data. UPDATE Input Second rank write enable. Forcing this pin to logic low allows the data stored in all 34 first rank latches (in both banks) to be transferred to the second rank latches. The signal connection matrix will be reprogrammed when the second rank data and levels are changed. This is a global pin, transferring all 34 rows of data at once. It is not necessary to program the address pins. It should be noted that after initial power-up of the device, the first rank data is undefined. It is desirable to preprogram all 17 outputs before performing the first update cycle. RE Input Output address pins. The binary encoded address applied to the lower A[5:0] input pins determines which of the 34 outputs is being programmed (or being read back). The most significant bit, A6, determines whether the data pins contain information for the connection register bank or the output level register bank. Using the broadcast address, A[5:0] = "111111" will simultaneously program data into all outputs at once. D[5:0] Inputs/Outputs Input configuration or output level data pins. In write mode, when the bank selection bit A6 is LOW, the binary encoded data applied to pins D[5:0] determine which of the 34 inputs is to be Second rank read enable. Forcing this pin to logic low enables the output drivers on the bidirectional D[5:0] pins, entering the readback mode of operation. By selecting an output address with the A[6:0] pins and forcing RE to logic low, the 6-bit data stored in the second rank latch for that output address will be written to D[5:0] pins. Data should not be written to the D[5:0] pins externally while in readback mode. The RE is a higher priority pin than the WE pin, so first rank programming is not possible while in readback mode. -16- REV. A AD8152 CS Input Chip select. This pin must be forced to logic low to program or receive data from the logic interface, with the exception of the RESET pin, described below. This pin has no effect on the signal pairs and does not alter any of the stored control data. RESET Input If it is desired to program all outputs to the same current level, then the broadcast Code 63 can be placed on the address bus (A5:A0), along with A6 = 1. (D3:D0) will then program all output currents to the same level. When the current code is set to 0000, a minimum current level of 2 mA is obtained. For any other code, the current can be calculated by (current code) 2 mA + 2 mA. Refer to Table III. For example, 16 mA can be programmed by Code 0111. This is 7 2 mA + 2 mA = 16 mA. Register-Control Signals Global output disable pin. Forcing the RESET pin to logic low will disable all outputs, setting both ranks of all 34 input connection latches, regardless of the state of any other pins. This has the effect of immediately disabling the 34 output signal pairs in the matrix. The output level information is also changed. It is necessary to momentarily hold RESET at a logic low state when powering up the AD8152 in order to avoid random internal contention where multiple inputs may be connected to one output. The RESET pin is not gated by the state of the chip select pin, CS. Control Interface Levels Several single-ended logic input pins control the register loading associated with the address and data buses described in the previous section. The control functions are tabulated in Table IV. There are dual ranks of registers for the data that programs the AD8152. The first rank registers accumulate the data for the various outputs as they are being programmed one by one. The second rank registers actually control the functions of the device. The RESET signal is used to reset the connection matrix, disable all outputs, and set all of the output currents to a default condition at Code 0111. This action sets the output current to a nominal value of 16 mA. The data in the first rank latches is also reset by the assertion of RESET. The CS signal is used to enable the control interface. If several devices are used in a system with the other control signals bussed, the CS signal can be used to select an individual device to change its programming. The WE signal is used to enable writing data to the first rank registers. This data will not immediately affect the features of the AD8152. The UPDATE signal transfers the data from the first rank registers to the second rank registers. After assertion of UPDATE, the data actively controls the AD8152 functions. The second rank registers can be read back through the data bus. The output is addressed on A5:A0 and the connection/current is selected via A6. Asserting RE will cause the second rank data to appear on the data bus. The RE function will dominate over WE if both are asserted at the same time. Broadcast readback is not permitted. Some typical programming waveforms for the control signals are provided in Figure 6. A[6:0] VALID ADDRESS INPUT VALID ADDRESS INPUT The AD8152 control interface shares the data path supply pins, VCC and VEE. The potential between the positive logic supply VCC and the negative supply VEE must be at least 2.25 V and no more than 3.63 V. Regardless of supply, the logic threshold is approximately one-half the supply range, allowing the interface to be used with most LVCMOS and LVTTL logic drivers. Output Addressing The AD8152 is programmed using a memory interface module, with parallel address and data buses. Six bits (A5:A0) are used to address the outputs. By setting the decimal value of these address bits to a value from 0 to 33 inclusive, then one of the 34 outputs is uniquely addressed. One additional code, 63 (all 1s), is used for the broadcast mode. If this address is selected, then all outputs will receive the same programming. The remaining addresses in the space are not valid and are reserved, Codes 34 to 66 inclusive. (See Table I.) Connection and Output Current Programming A seventh address bit (A6) determines which of two types of programming is selected. If A6 = 0, connection matrix programming is selected. If A6 = 1, output current programming is selected. Using the Data Bus Once it is determined which output is to be programmed (or broadcast to all outputs) and which type of programming (connection/ output-current), then the data bits (D5:D0) further define the programming action. If the selection is connection programming (A6 = 0), then the data bits select the input that is to be connected to the addressed output. If the broadcast address is selected, then the data bits select the input that will be connected to all 34 outputs. (See Table II.) A disable code (D5:D0 = 63, or all 1s) is used to disable (and power down) the particular output that is addressed. A broadcast disable can be effected by setting Code 63 on both the address bus and the data bus along with A6 = 0. Output-Current Programming D[5:0] VALID DATA INPUT VALID DATA INPUT WE UPDATE Figure 6. Programming Waveforms Input/Output Coupling A current source in each output can be digitally programmed to any one of 16 different current levels. Changing these current levels will change the amplitude of the output swing that is developed across the internal 50 W termination resistors. To program the current for a particular output, its address is set on A5:A0 (00-33), while A6 is set to 1. The four LSBs of the data address (D3:D0) are then used to select one of the 16 output current levels. D4 and D5 are "don't cares" for output current programming. (See Table III.) REV. A The AD8152 has internal 50 W termination resistors for each single-ended input and output. This can also provide a 100 W termination for a 100 W differential transmission line. All of the input termination resistors connect to one common point called VTTI. Similarly, each of the output termination resistors connects to one common point called VTTO. The voltage can be set independently at VTTI and VTTO to accommodate various interface architectures. -17- AD8152 Input Coupling One way to simplify the input circuit and make it compatible with a wide variety of driving devices is to use ac coupling. This has the effect of isolating the dc common-mode levels of the driver and the AD8152 input circuitry. For example, the XAUI interconnect specification for 10 Gbps Ethernet requires ac coupling in order to ensure that there are no interactions of dc levels between the transmitting and receiving devices. AC coupling requires that the signal patterns have no long-term dc component, which may occur in any random data stream. Codes such as 8b/10b, called for in the XAUI specification, are used in many data communications systems to ensure that the data pattern is benign in an ac-coupled link. This is accomplished by run-length limiting (RLL), which sets a maximum for the number of 1s or 0s that can occur consecutively. In addition, residual dc components are monitored and modified by keeping track of the running disparity, excess of 1s versus 0s or vice versa. For the AD8152 inputs, ac coupling requires a capacitor in series with each single-ended input signal, as shown in Figure 7. This should be done in a manner that does not interfere with the high speed signal integrity of the PC board. The details of this are covered in the section on board layout guidelines. The two critical variables are setting the proper voltage for VTTI and selecting the correct value of coupling capacitors. VTTI VCC If VTTI is set equal to VCC, then the single-ended signal will just meet the specifications where its highest excursion will be 0.2 V higher than VCC. The lowest level to set VTTI is 0.8 V above VEE. This will cause the negative signal excursions to stay within the operating range. With ac-coupled inputs, there is no power consumption advantage associated with varying VTTI. As a practical matter, it might be desirable to set VTTI at the same voltage as VTTO so that only one supply is necessary. Refer to the VTTO section for more information. Output Coupling Each single-ended output of the AD8152 has a termination resistor that ties to a common point called VTTO. When VTTO is varied, it will change the common-mode levels of the outputs and the power dissipation of the output stages when they are enabled. The individual output currents are programmable. Varying this current will change the lower level of the output voltage (and thus the peak-to-peak swing) and also change the power dissipation in the output stages. To obtain a standard 800 mV p-p differential output (single-ended = 400 mV p-p), the output current should be programmed to 16 mA. With an effective termination resistance of 25 W, this will generate the proper differential voltage. If the AD8152 drives another device that is ac-coupled, there is no interaction of the dc levels on each side of the coupling capacitors (see Figure 8). The dc levels for the AD8152 can be calculated independent of the levels of the device that is driven. The upper allowable setting for VTTO is 0.2 V higher than VCC. The signals will be pulled up to this level at their highest excursion. However at this setting, the power dissipation will be a maximum. To save power, VTTO can be lowered. The lowest level for VTTO will be determined by the lowest output level allowable (VOL) by the AD8152 output when it is logically low. The output at any time should not go lower than 1.0 V below VCC. If the single-ended swing of an output is 400 mV p-p, then the lowest that VTTO can go is 0.6 V below VCC. For more information on VOL, see TPC 17. VCC VTTO VTT VCC CINP 50 INXXP INXXN 50 CINN VEE Figure 7. AC-Coupling Input Signal from AD8152 On the AD8152 side of the input coupling capacitor, the average value of the single-ended input voltage will be at the voltage set at VTTI. The range of allowable voltages is a function of the acceptable input voltages of the active circuitry of the AD8152 inputs and the amplitude of the input signal. The operating input range of the AD8152 extends from VCC + 0.2 V to 0.8 V above VEE. The total range that will be occupied by the input signal will be its average value (as established by the voltage applied to VTTI) plus or minus one half the single-ended swing of the signal. For a standard 800 mV p-p differential signal, the single-ended swing is 400 mV p-p. Thus, the signal will swing 200 mV about the average value equal to VTTI. AD8152 50 50 OUTXXP OUTXXN DRIVEN DEVICE I = 2mA (CODE) + 2mA VEE VEE VEE Figure 8. AC-Coupling Output Signal from AD8152 -18- REV. A AD8152 AD8152 POWER CONSUMPTION There are several sections of the AD8152 that draw varying power depending on the supply voltages, the type of I/O coupling used, and the status of the AD8152 operation. Figure 9 shows a block diagram of these sections. These are described briefly below and then in detail later in the data sheet. Table X summarizes the power consumption of each section and is a useful guide as the following sections are reviewed. The first section is the input termination resistors. The power dissipated in the termination resistors is the result of their being driven by the respective driving stage. Also, there might be dc power dissipated in the input termination resistors if the inputs are dc-coupled and the driving source reference is a dc voltage that is not equal to VTTI. In the next section, the active part of the input stages, each input is powered only when it is selected. If an input is not selected, it VCC VTTI is powered down. Thus, the total number of active inputs will affect the total power consumption. The core of the device performs the crosspoint switching function. It draws a fixed quiescent current whenever the AD8152 is powered from VCC to VEE. An output predriver section draws a current that is proportional to the programmed output current, IOUT. This current always flows from VCC to VEE. It is treated separately from the output current, which flows from VTTO, and might not be the same voltage as VCC. The final section is the outputs. For an individual output, the programmed output current will flow through two separate paths. One is the on-chip termination resistor, and the other is the transmission line and the destination termination resistor. The nominal parallel impedance of these two paths is 25 W. The sum VTT VTTO OUTPUT TERMINATIONS IOUT 50 P= 50 2 50 INP INN INPUT TERMINATIONS INPUTS I = 2mA PER ACTIVE INPUT SWITCH MATRIX OUTPUT PREDRIVER OUTPUTS I = 32mA I = .25 IOUT IOUT 50 50 50 OUTP OUTN 50 DRIVEN DEVICE TERMINATIONS OPTIONAL COUPLING CAPACITORS P = (VOL) (IOUT) VOL = VTTO - (IOUT 25 ) P= (Vindiffrms)2 100 VEE Figure 9. Power Consumption Block Diagram Table X. Power Consumption Input Termination Resistors Quiescent Current Current per Active Channel Current per Active Channel for Differential VIN = 800 mV p-p Sine VOUT = 800 mV p-p Per Channel Power Power for All Channels Active Percentage of Total Power Per Channel Power Power for All Channels Active Percentage of Total Power REV. A Input Stage Core 32 mA Output Predriver 0.25 IOUT Output Termination Resistors 0.5 IOUT Output Switch + Current Source Total Power VIN /(RTERMINATION) 2 mA IOUT 566 mV rms/100 = 5.66 mA 3.2 mW 108.8 mW 5% 3.2 mW 108.8 mW 4% 2 mA 5 mW 170 mW 8% 6.6 mW 224 mW 9% 4 mA 4 mA 10 mW 340 mW 17% 13.2 mW 449 mW 17% 8 mA 8 mW 272 mW 13.6% 8 mW 272 mW 10% 16 mA 33.6 mW 1.03 W 51% 46.4 mW 1.47 W 56% 2.5 V Operation (VCC - VEE = 2.5 V, VTTO = 2.5 V, IOUT = 16 mA) 80 mW 4% 2.0 W 3.3 V Operation (VCC - VEE = 3.3 V, VTTO = 3.3 V, IOUT = 16 mA) 106 mW 4% -19- 2.63 W AD8152 of these two currents will flow through the switches and the current source of the AD8152 output circuit and out through VEE. The power dissipated in the transmission line and the destination resistor will not be dissipated in the AD8152, but will have to be supplied from the power supply, and is a factor in the overall system power. The current in the on-chip termination resistors and the output current source will dissipate power in the AD8152 itself. Input Termination Resistors OUTPUTS The output current is forced by a current source that is programmed to a variable amount of current from 2 mA to 32 mA in 2 mA steps. For the two logic switch states, this current flows through an on-chip termination resistor and a parallel path to the destination device and its termination resistor. The power in this parallel path is not dissipated by the AD8152. The nominal programmed output current is 16 mA. With the two parallel 50 W resistors at each collector (25 W equivalent), this current will create a 400 mV p-p swing in each half of the circuit. The differential output voltage will be 800 mV p-p. Under steady state conditions and with a data pattern that is run-length limited so that its low frequency content is significantly higher than the RC pole formed by the coupling capacitor and the termination resistors, the common-mode level at the AD8152 outputs will be 400 mV lower than VTTO. Each output will then swing 200 mV from this level, which is a 400 mV p-p singleended output swing. At the high level, there will be 200 mV across the termination resistor. This will dissipate a power of 0.8 mW. At the low level, the 600 mV across the termination resistor will dissipate a power of 7.2 mW. Since the output signal is basically 50% duty cycle, the average power dissipated will be the average of these two values or 4 mW. By symmetry, the other differential output will dissipate the same power. This yields an on-chip termination-resistor power dissipation of 8 mW per channel for each output, or 272 mW for all 34 outputs. The full output current (from both on- and off-chip termination resistors) will flow in the lower part of each output. This current flows only in the side that is "on," or in its low state (VOL). This voltage is 600 mV below the dc level at VTTO. Thus, for VTTO = 2.5 V, VOL = 1.9 V, and the power dissipation for IOUT = 16 mA is 30.4 mA. For all 34 channels, the power is 1.03 W. If VTTO = 3.3 V, then VOL = 2.7 V. The single power is 43.2 mW and the power for all 34 channels is 1.47 W. If VTTO = 2.5 V, then the additional power is given by 16 mA [(2.5 V - (16 mA 25 W)] = 33.6 mW. Thus, the total AD8152 power dissipation for this output is 37.6 mW. If all 34 outputs are enabled with the same IOUT, the total power dissipation is 1.28 W. Thus it can be seen that the outputs are the major contributor to the power dissipation. Power Saving Considerations The power dissipated in the input termination resistors is delivered by the driving source. First, assume the driving waveform for an individual input is a differential square wave with an amplitude of Vinpp. Then the power dissipated in this input is (Vinpp)2/2Rterm. However, this result is quite pessimistic, because at high frequencies, the wave shape is usually more sinusoidal than square. If instead, a differential sine wave of amplitude Vinpp is assumed, then its rms amplitude is 0.7 times that of a square wave. This will yield a power that is one half of the square wave case. The assumed wave shape is not too critical because the fraction of the power dissipated in the input termination resistors is not very large. A further effect is that the input signal might travel over a path that attenuates the signal. This will usually be a function of frequency. Thus, for such a case, some of the signal power will be dissipated in the signal path. This will reduce the amount of power dissipated in the AD8152 input terminations. If dc coupling is used, a dc current will flow from VTTI through the termination resistors if the dc voltage of the drive circuit is not equal to VTTI. The additional power in each input termination resistor will be the current that flows multiplied by the 50 W value of the input terminations. For a point of reference, assume a channel has a sinusoidal input of 800 mV p-p differential. The power dissipated for a single input will be 3.2 mW. If all 34 input channels are driven the same, then the power in the input terminations will be 109 mW. Input Stage The input stages are powered down when not in use. There is about 2 mA that flows through an enabled input from VCC to VEE. Thus, the power dissipated by an enabled input is 5 mW for a supply of 2.5 V and 6.6 mW for a 3.3 V supply. For all 34 inputs enabled, the respective figures are 170 mW for a 2.5 V supply and 224 mW for a 3.3 V supply. Switch Matrix The switch matrix draws a fixed 32 mA when the AD8152 is powered. This current flows from VCC to VEE. The power dissipation from this current is 80 mW at 2.5 V and 106 mW at 3.3 V. Output Predrivers The output predrivers draw additional current when each of the outputs is enabled. This extra current is proportional to the programmed output current. The extra predriver current for a channel will be 25 percent of the programmed output current for that channel. This current will also flow from VCC to VEE. When an output is enabled and programmed to 16 mA, an additional 4 mA will flow in the predriver section. This will dissipate 10 mW at 2.5 V or 13.2 mW at 3.3 V for an individual output. For all 34 outputs enabled and programmed to 16 mA, the predriver power will be 340 mW at 2.5 V or 449 mW at 3.3 V. While the AD8152 power consumption is very low compared to similar devices, careful control of its operating conditions can yield further power savings. Significant power reduction can be realized by operating the part at a lower voltage. Compared to 3.3 V operation, a supply voltage of 2.5 V can result in power savings of about 25 percent. There is virtually no performance penalty when operating at lower voltage. A second measure is to disable outputs when they are not being used. This can be done on a static basis if the output is not used, or on a dynamic basis if the output does not have a constant stream of traffic. Since the majority of the power dissipated is in the output stage, some of its flexibility can be used to lower the power consumption. -20- REV. A AD8152 First, the output current can be programmed to the smallest amount required to maintain BER performance. If an output circuit always has a short length and the receiver has good sensitivity, then a lower output current can be used. It is also possible to lower the voltage on VTTO to lower the power dissipation. The amount that VTTO can be lowered is dependent on the lowest of all the output's VOL. This will be determined by the output that is operating at the highest programmed output current since VOL = VTTO - (IOUT 25 W). EVALUATION BOARD AND PCB LAYOUT HINTS ALL TOP-MOUNT SMAs SIT ON PCB TOP LEVEL SMA CENTER PIN PLANE RELIEF MICROSTRIP DRILL HOLES (7 EACH) TOP VIEW OF TOP LEVEL TRACE BOTTOM VIEW OF BOTTOM LEVEL TRACE Figure 10. Top-Mount SMA PCB Layout, Two Views The AD8152 evaluation board was designed to allow the user to analyze signal integrity in many configurations, as controlled by a standard PC. The FR4 board comes equipped with a full complement of 136 SMA connectors to support the complete 34 34 matrix of points. Each differential pair of microstrip is connected to either top mount or side-launch SMA connectors. The mounting area of the short center pin top-mount SMA connectors are drilled (seven holes) and stubbed for greatly improved performance. In the area surrounding SMA top-mount center pin and drill holes, all internal planes are relieved or cleared out (see Figure 10 for layout). The FR4 PC board is eight layers with a thickness of 62 mils (1.57 mm). The two outer most metal layers hold the high speed microstrip routing lines. The two outer most dielectric layers are 5 mils thick and must be controlled impedance (50 W) layers. These are the only two layers that require controlled impedance. The next two inner metal layers are ground (reference) planes for the microstrip and are the shell for the SMA connectors. The remaining four inner metal layers are for the four AD8152 supply and digital control signal routing. From top to bottom the four supply layers are VTTO, VCC, VEE, and VTTI. Because all four supply PCB metal layers float, positive, negative, and even dual-supply configurations are possible. The variety of supply configurations ease the connection of test equipment. The four inner supply layers also provide an interlayer capacitance, which has better impedance versus frequency than standard chip capacitors. DIELECTRIC THICKNESS 0.5mils SILKSCREEN COPPER LAYER NUMBER THICKNESS/DESIGNATION (IN OUNCES) 1. 5.0mils 2. 4.0mils 3. 16.0mils 4. 4.0mils 5. 16.0mils 6. 4.0mils 7. 5.0mils 8. 1.50/ TOP MICROSTRIP WIDTH = 8.0mils 0.50/GND 0.50/VTTO 0.50/VCC 0.50/VEE 0.50/VTTI 0.50/GND 1.50/BOTTOM MICROSTRIP WIDTH = 8.0mils 0.5mils SILKSCREEN Figure 11. Evaluation Board Stack-Up REV. A -21- AD8152 Figure 12. Cross-Sectional Layout and Dimensioning (To Scale) of Differential The variety of supply configurations cause the need for a supply agile digital control circuitry. This is done by a programmable logic device (PLD), which provides instructions to the AD8152. The PLD supply is typically tied with jumpers across the AD8152's VCC and VEE supplies (Jumpers J3 and J4). The PLD is addressed from the PC by way of digital isolators. These couplers isolate PC levels from the PLD and allow for any level shifting. If desired, the user can drive the PLD supply separately as long as the VEE of the AD8152 and the PLD are tied together (remove Jumper J3 and leave J4 installed). This allows one to measure the AD8152 only supply current, for example. Board Construction or Stack-Up During the layout of the differential microstrip, a software tool snaps the distance between the two traces to be a constant. If the distance is not kept constant, impedance variations will result. These fluctuations can be measured by time domain reflectometry (TDR). EXTRA ADDED INDUCTANCE Figure 11 is a picture of AD8152 evaluation board stack-up from top to bottom. The layer stack-up has been made symmetrical to avoid board warpage during manufacture. The microstrip layout and dimensions are shown in Figure 12. The microstrip trace width was chosen to be 8 mils. This allows relative ease in routing through the BGA rows that are 50 mils (1.27 mm) apart. The outer two out of four rows of high speed signals are routed on top of the PCB, while the inner two rows are via holed to the board's opposite side and then routed outward. Wider microstrip is desirable for reducing eye height loss versus long traces; however, the routing will be more difficult as the AD8152 is approached. The wide microstrip would have to be necked down in width in order to be routed into the BGA. The necking will increase trace impedance and therefore induce more signal reflection problems. BGA CORNER OUTLINE Figure 14. Poor Capacitor Layout Bypass Capacitor Layout The AD8152 8-layer PCB takes advantage of buried interlayer capacitance. The VEE to VCC planes are placed in the very middle of the board to make the highest value capacitor. The 4 mil (0.102 mm) dielectric spacing between VCC/VEE yields 26 nF of capacitance. Each AD8152 supply pin is directly connected to its supply plane through a via hole beneath the BGA ball. The via hole size for a BGA supply pin is slightly bigger than a signal via. This is to reduce the inductance of the connection, and it also happens to be a compact layout. For the chip capacitors, the via holes are placed directly in the middle of the mounting area and made as large as possible, i.e., greater than or equal to 35 mils (0.89 mm). This is to minimize inductance as much as possible. By minimizing inductance, the performance of the capacitor or impedance versus frequency response is not greatly diminished. Note that chip capacitors will work up to only about 300 MHz. Figure 14 is an example of a bypass capacitor layout that should be avoided in any high speed printed circuit board. This layout connects the chip capacitor mounting pads to small via holes through a skinny PCB trace. This amounts to four extra inductors added to the capacitor, two largely from the skinny surface traces and two from small via holes. Inductance is also variable with copper thickness and attachment method to power plane. Thermal relief for soldering purposes also adds unwanted inductance and should be avoided. VIA HOLE (GRAY) CHIP CAPACITOR (805) SIZE MICROSTRIP TRACES Figure 13. BGA Corner Capacitor Layout -22- REV. A AD8152 VCC VTTO AD8152 P ECL DRIVER IN N P OUT N TO 50 SCOPE INPUTS This would require VTTI to be attached to ground, causing excessive power to be dissipated in the internal 50 W input termination resistors. Secondly, when the AD8152 output tries to drive its own input with VTTI = 0 V and VTTO = 2.5 V, the input will pull the output stage levels down enough to shut off any signal toggling. All ac coupling shown is actually done with a set of bias tees. If desired, the bias tee can be used to monitor average dc voltage levels at an input or output (depending on direction installed), and it can also serve to change input dc levels. Make sure the bias tees used in the setup have enough low frequency bandwidth to pass long patterns and keep edge rates intact. The longer the pattern, the more low frequency bandwidth is needed. If ac coupling is desired on a user board, 0402 or 0603 sized capacitors can be installed on microstrip lines. The biggest 0402 size, XR7 type usable is 0.01 mF, which will work fine for short patterns (PRBS 27-1) and data rates down to 1.0 Gbps. For long patterns a 0603 sized, XR7 type, 0.1 mF should be used. To decrease capacitive loading from the mounting area, clear out planes underneath the coupling capacitor. In Figure 16, 6 dB attenuators are placed before the AD8152 input ac-coupling or bias tees. This is because many generators won't go below 500 mV single-ended. The output pair of 6 dB attenuators is present to protect the scope inputs and allow for higher scale voltages per division. The eye diagram is usually viewed differentially by using a simple P - N math function. Cabling used in this setup must be matched. Mismatched cables cause either a P or N signal to be falsely delayed. This delay can show up as a change in the crossing point, from 50 percent in the eye diagram. To accurately check cable matches, a TDR setup is recommended. VTTI = -2V VEE = -2.5V Figure 15. Evaluation Board ECL Driver Test Setup Connections for Testing The AD8152 evaluation board can be used under a variety of positive or negative supply configurations. Negative supply configurations, as shown in Figure 15, allow the easiest hookup to test equipment because inputs and outputs can be direct coupled. In a real world application however, the negative supply configuration would be difficult because control logic levels must be shifted negative. Figure 16 is an example of a loop-through test setup using a positive supply. In this case, the test signal goes through the AD8152 twice. It is possible to loop through multiple times if desired, but jitter will increase with number of loop-throughs. The first input from the generator and the last output to a scope must be ac-coupled. However, an AD8152 output driving its own input can be direct-coupled. Direct coupling to the first AD8152 input is not effective since generators usually want to see 50 W to ground. 2.5V VCC VTTI PATTERN GENERATOR DATA OUT P IN01 DATA OUT TRIGGER OUT -6dB N P IN02 N VEE VTTO HIGH SPEED SAMPLING OSCILLOSCOPE P OUT01 N P OUT02 N TRIGGER IN -6dB 50 -6dB 50 AD8152 -6dB VCC = VTTI = VTTO = 2.5V, VEE = 0V, I OUT SET = 16mA RTI (REFERRED TO INPUT) A MPLITUDE = 400mV SINGLE-ENDED, VIN HI = 2.7V (IN01), PRBS 223 -1, VOH = 2.5V, VOL = 2.1V, AC-COUPLED IS FROM BIAS TEES, PROGRAMMING: IN01 TO OUT02, IN02 TO OUT01. Figure 16. Positive Supply Loop-Through Test Setup REV. A -23- AD8152 EVALUATION BOARD CONTROL SOFTWARE The AD8152 evaluation board can be controlled by using a PC and a custom software program. The hardware interface uses a PC parallel (or printer) port. A standard printer cable is used to connect from the PC DB-25 connector to the Centronics-type connector on the evaluation board. Figure 17 shows an evaluation board control panel from a PC display. A single screen allows control of all the programmable functions of the AD8152. The programming modes are listed in the Mode box. Select either I/O Programming or Current Programming by selecting the appropriate radio button. These will allow either programming the switch matrix or the output currents one at a time. An alternative is to use the Broadcast mode. This will either simultaneously program all of the outputs to one selected input or program all outputs to the same current. Next, select the desired output from the Output Select box by doubleclicking the appropriate output channel number. Finally, the Program button is clicked and the data is immediately sent to the evaluation board for programming the part to the selected I/O combination. If an additional output(s) is desired to be programmed to the same input, double-click the desired output channel number and click the Program button. The Programmed Output table indicates which outputs are programmed to the input that is indicated in the Active Input Selection window. If it is desired to disable an individual output, its radio button in the Programmed Output table can be clicked, and it will change from black to white to indicate that it is not enabled. Note: It is not possible to program outputs by selecting their radio buttons. To observe the set of outputs that are connected to any input, double-click the desired input channel number from the Input Select box. The selected channel number will show up in the Active Input Selection window and the programmed outputs will have a black dot in their radio button in the Programmed Output table. To program an output current, select the Current Programming button in the Mode box. Then double-click the desired output channel number from the Output Select table. Next double-click the desired entry for the Output Current. Finally, click the Program button. If the Broadcast button is selected from the Mode box, all outputs will be treated the same. If I/O Programming is selected, doubleclick the input channel number from the Input Select table and click the Program button. This will cause all outputs to be programmed to the selected output, and all of the buttons will have a black dot in the Programmed Output table. For broadcast current programming, double-click the desired Output Current. Then click the Program button. All of the outputs will be programmed to the selected output current. The Reset button will disable all outputs. In addition, all output currents will be programmed to the nominal value of 16 mA. Figure 17. Evaluation Board Control Panel In the I/O Programming mode (nonbroadcast), the desired input is selected from the Input Select box by double-clicking on the appropriate input channel number. This will cause the same channel to appear in the Active Input Selection indicator window. -24- REV. A AD8152 Figure 18. Evaluation Board Top Side Signals REV. A -25- AD8152 Figure 19. Evaluation Board Bottom Side Signals, View from Top -26- REV. A AD8152 Figure 20. Evaluation Board VCC Layer, View from Top REV. A -27- AD8152 Figure 21. Evaluation Board VEE Layer, View from Top -28- REV. A AD8152 Figure 22. Evaluation Board VTTI Layer, View from Top REV. A -29- AD8152 Figure 23. Evaluation Board VTTO Layer, View from Top -30- REV. A AD8152 OUTLINE DIMENSIONS 256-Ball Grid Array [SBGA] (BP-256) Dimensions shown in millimeters 27.00 BSC A1 CORNER 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y A1 1.27 27.00 BSC 24.13 REF TOP 24.13 REF BOTTOM 1.27 1.00 0.80 0.70 0.60 0.60 0.50 0.90 0.75 0.60 BALL DIAMETER 0.20 MIN 0.20 COPLANARITY SEATING PLANE SEATING PLANE 0.25 MIN COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2 REV. A -31- AD8152 Revision History Location 1/03--Data Sheet changed from REV. 0 to REV. A. Page Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 C02984-0-1/03(A) -32- REV. A PRINTED IN U.S.A. |
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