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CYM1846
512K x 32 Static RAM Module
Features
* High-density 16-megabit SRAM module * 32-bit standard footprint supports from 16Kx32 through 1Mx32 * High-speed SRAMs -- Access time of 12 ns * Low active power -- 4.4W (max.) at 12 ns * Compatible with CYM1821, CYM1831, CYM1836, CYM1841, and CYM1851 JEDEC modules * Available in 72-pin ZIP or SIMM/Angled SIMM constructed from four 512K x 8 SRAMs in SOJ packages mounted on an epoxy laminate substrate. Four chip selects are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of the chip selects. The CYM1846 is designed for use with standard 72-pin SIMM socket and ZIP footprint. The pinout is compatible with the 64-pin JEDEC ZIP/SIMM module family (CYM1821, CYM1831, CYM1836, and CYM1841) and the 72-pin CYM1851. Thus, a single motherboard design can be used to accommodate memory depth ranging from 16K words (CYM1821) to 1024K words (CYM1851). The standard SIMM can be used in Angled SIMM sockets and is available with either tin-lead or 10 micro-inches of gold flash on the edge contacts. Presence detect pins (PD0 - PD3) are used to identify module memory density in applications where modules with alternate word depths can be interchanged.
Functional Description
The CYM1846 is a high-performance 16-megabit static RAM module organized as 512K words by 32 bits. This module is
Logic Block Diagram
PD0 - PD1 - PD2 - PD3 - A0 - A18 OE WE 512Kx8 SRAM CS1 512Kx8 SRAM CS2 512Kx8 SRAM CS3 512Kx8 SRAM CS4 I/O24 - I/O31 I/O16 - I/O23 I/O8 - I/O15 I/O0 - I/O7
19
Pin Configuration
OPEN OPEN GND OPEN
ZIP/SIMM Top View
NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND NC NC
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
8
8
NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 NC
8
8
1846-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 December 1994 - Revised October 10, 1997
CYM1846
Selection Guide
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA)
Shaded area contains preliminary information.
1846-12 12 800 240
1846-15 15 800 240
1846-20 20 800 240
1846-25 25 800 240
1846-35 35 800 240
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied ............................................... -10C to +85C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ................................................ -0.5V to +VCC DC Input Voltage ............................................-0.5V to +7.0V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current[1] Automatic CS Power-Down Current[1] GND VI VCC GND VO VCC, Output Disabled VCC = Max., IOUT = 0 mA, CSN VIL Max. VCC, CS VIH, Min. Duty Cycle = 100% Max. VCC, CS VCC - 0.2V, VIN VCC - 0.2V, or VIN 0.2V -20, -25, 35 -12, -15 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -10 -10 Min. 2.4 0.4 VCC + 0.3 0.8 +10 +10 800 240 40 120 Max. Unit V V V V A A mA mA mA mA
Capacitance[2]
Parameter CINA CINB COUT Description Input Capacitance (WE, OE, A0-18) Input Capacitance (CS) Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 40 20 20 Unit pF pF pF
Note: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis.
2
CYM1846
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 481 R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R1 481 R2 255 ALL INPUT PULSES 3.0V GND 5 ns
1846-2
90% 10%
90% 10% 5 ns
(a)
Equivalent to: OUTPUT THEVENIN EQUIVALENT 167 1.73V
(b)
1846-3
Switching Characteristics Over the Operating Range[3]
1846-12 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPD WRITE CYCLE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
[6]
1846-15 Min. Max. Unit
Description
Min.
Max.
Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z
[4] [4, 5]
12 12 3 12 7 0 7 3 7 12
15 15 3 15 8 0 8 3 8 15
ns ns ns ns ns ns ns ns ns ns
CS HIGH to High Z
CS HIGH to Power-Down
Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[5]
12 9 9 0 1 10 7 1 3 0 7
15 10 10 0 1 12 8 1 3 0 8
ns ns ns ns ns ns ns ns ns ns
Shaded area contains preliminary information.
3
CYM1846
Switching Characteristics Over the Operating Range[3] (continued)
1846-20 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPD WRITE CYCLE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z
[4] [4, 5]
1846-25 Min. Max.
1846-35 Min. Max. Unit
Description
Min.
Max.
20 20 3 20 10 0 10 3 10 20
25 25 3 25 15 0 12 3 12 25
35 35 3 35 25 0 12 3 12 35
ns ns ns ns ns ns ns ns ns ns
CS HIGH to High Z
[6]
CS HIGH to Power-Down
Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[6]
20 15 15 0 1 15 10 1 3 0 10
25 20 20 0 2 20 15 2 4 0 12
35 30 30 0 2 30 20 2 5 0 12
ns ns ns ns ns ns ns ns ns ns
Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/I OH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested. 5. tHZCS and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
4
CYM1846
Switching Waveforms
Read Cycle No. 1 [7, 8]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1846-4
Read Cycle No. 2 [7, 9]
tRC CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS tPU V CC SUPPLY CURRENT 50% DATA VALID tPD ICC 50% ISB
1846-5
tHZOE tHZCS HIGH IMPEDANCE
Write Cycle No. 1 (WE Controlled)
[6]
tWC ADDRESS tSCS CS tAW tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
1846-6
tHA tPWE
tHD
tLZWE HIGH IMPEDANCE
Notes: 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL, and OE= VIL. 9. Address valid prior to or coincident with CS transition LOW.
5
CYM1846
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled) [6, 10]
tWC ADDRESS tSCS CS tAW tSA WE tSD DATAIN DATA VALID tHZWE DATAOUT DATA UNDEFINED tLZWE HIGH IMPEDANCE tHD tPWE tHA
Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CS H L L L WE X H L H OE X L X H Inputs/Output High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
Ordering Information
Speed (ns) 12 Ordering Code CYM1846PM-12C CYM1846P8-12C CYM1846PZ-12C 15 CYM1846PM-15C CYM1846P8-15C CYM1846PZ-15C 20 CYM1846PM-20C CYM1846P8-20C CYM1846PZ-20C 25 CYM1846PM-25C CYM1846P8-25C CYM1846PZ-25C 35 CYM1846PM-35C CYM1846P8-35C CYM1846PZ-35C
Shaded area contains preliminary information.
Package Type PM21 PM21 PZ11 PM21 PM21 PZ11 PM21 PM21 PZ11 PM21 PM21 PZ11 PM21 PM21 PZ11
Package Type 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic ZIP Module
Operating Range Commercial
Commercial
Commercial
Commercial
Commercial
Document #: 38-M-00073-B
6
CYM1846
Package Diagrams
72-Pin Plastic SIMM Module PM21
72-Pin Plastic ZIP Module PZ11
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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