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P R E L I M I N A RY I N F O R M AT I O N
ICS1493-17
Clock Synthesizer for Portable Systems
Description
The ICS1493-17 is a low-power, low-jitter clock synthesizer designed to replace multiple crystals and oscillators in portable audio/video systems. The device generates a 37 MHz processor clock, a 48 MHz USB clock, a fixed 22.5792 MHz audio clock, a selectable 24.576 MHz or 22.5792 MHz audio clock, and a 27MHz reference clock for video. Using ICS' proprietary mix of analog and digital Phase-Locked Loop (PLL) technology, the device spreads the frequency spectrum of the 37 MHz output, reducing the peak amplitude of by up to 16 dB. An output enable (OE) pin lowers the chip power consumption while tri-stating all outputs.
Features
* * * * * * * * * *
Extremely low operating current (11 mA) Packaged in 20-pin QFN (Pb-free) Input crystal or clock frequency of 27 MHz Output reference frequency of 27 MHz Fixed output frequencies of 37 MHz, 48 MHz and 22.5792 MHz Selectable output frequency of either 22.5792 MHz or 24.576 MHz Configurable spread spectrum on 37 MHz output Operating core voltage of 1.8 V Output voltage of 1.8 V or 2.5 V Advanced, low-power CMOS process
Block Diagram
VDD 3 PLL1 (Spread) VDDO 2 OE
37M
SCK SDATA
IIC Control Logic
PLL2
48M
PLL3
22/24M
PLL4 27 MHz clock or crystal input X1 Crystal Oscillator/ Clock Buffer 5 GND
22M
27M
X2
Optional tuning capacitors
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5 25 Race Street, San Jo se, CA 9 512 6
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P R E L I M I N A RY I N F O R M AT I O N
ICS1493-17 Clock Synthesizer for Portable Systems
Pin Assignment
GND VDD 27M X1 X2
Output Enable Table
OE Clock Output State
GND 48M VDDO OE VDD
1
16
0
GND VDD 37M VDDO
Normal Operation Hi-Z
1
Note: OE pin has an internal pull-down resistor.
6
11
22/24M
22M
GND
20-pin QFN
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin Name
GND 48M VDDO OE VDD 22M GND SCK SDATA GND 22/24M VDDO 37M VDD GND GND 27M
SDATA
GND
SCK
Pin Type
Power Output Power Input Power Output Power Input Input Power Output Power Output Power Power Power Output Connect to ground.
Pin Description
48 MHz clock output. High impedance state when OE=1. Output voltage level. Connect to +1.8 or 2.5 V. Same voltage as pin 12. Output Enable pin. See table above. Internal pull-down resistor. Connect to +1.8 V. 22.5792 MHz clock output. Internal pull-down. High impedance state when OE=1. Connect to ground. I2C bus clock pin. Internal pull-up resistor. I2C bus data pin. Internal pull-up resistor. Connect to ground. Selectable output clock of either 22.5792M or 24.576M. See table. Internal pull-down. High impedance state. OE=1. Output voltage level. Connect to +1.8 or 2.5 V. Same voltage as pin 3. Spread spectrum 37 MHz clock output. See table. Internal pull-down. High impedance state when OE=1. Connect to +1.8 V. Connect to ground. Connect to ground. 27 MHz reference clock output. Internal pull-down. High impedance state when OE=1. 2
MDS 1493-17 A Integrated Circuit Systems
Revision 101005
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te l (4 08) 297 -1201 w w w. i c s t . c o m
P R E L I M I N A RY I N F O R M AT I O N
ICS1493-17 Clock Synthesizer for Portable Systems
Pin Number
18 19 20 .
Pin Name
VDD X2 X1
Pin Type
Power Output Input Connect to +1.8 V.
Pin Description
Connect to 27 MHz crystal or float for clock input. Crystal connection. Connect to 27 MHz crystal or clock input.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS1493-17 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS1493-17. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
I2C External Resistor Connection
The SCK and SDATA pins can be connected to any voltage between 1.71 V and 2.625 V.
Crystal Load Capacitors
No external crystal load capacitors are required. To save discrete component cost, the ICS1493-17 integrates on-chip capacitance to support a crystal with CL=10 pF. It is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device.
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Revision 101005 te l (4 08) 297 -1201 w w w. i c s t . c o m
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ICS1493-17 Clock Synthesizer for Portable Systems
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS1493-17. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs All Outputs Storage Temperature Junction Temperature Soldering Temperature ESD (HBM) MSL (Moisture Sensitivity Level) -0.5 V to 5 V
Rating
-0.5 V to VDD+0.5 V -0.5 V to 2.5V+0.5 V -65 to +150C 125C 260C 2000V min. 3
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Output Power Supply Voltage (with respect to GND)
Min.
-10 +1.70 +1.71
Typ.
Max.
+80 +2.00 +2.625
Units
C V V
DC Electrical Characteristics
Unless stated otherwise, VDD = 1.8 V -0.1 V/+0.2 V, VDDO=2.5 V 5%, Ambient Temp -10C to +80C
Parameter
Operating Voltage Supply Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Capacitance, inputs Load Capacitance, X1 and X2
Symbol
VDD IDD VIH VIL VOH VOL CIN CL
Conditions
No load,VDDO=2.5 V No load,VDDO=1.8 V
Min.
1.7
Typ.
13 11
Max.
2.0 16 15 0.3VDD
Units
V mA mA V V V V pF pF
0.7VDD IOH = -2 mA IOL = +2 mA 5 No internal load capacitance 5 0.8VDDO 0.2VDDO
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ICS1493-17 Clock Synthesizer for Portable Systems
Parameter
Internal Pull-down Resistor Internal Pull-up Resistor
Symbol
RPD RPu
Conditions
OE, 48M, 22M, 22/24M, 37M, 27M SCK, SDATA
Min.
75 100
Typ.
250 500
Max.
Units
k k
AC Electrical Characteristics
Unless stated otherwise, VDDO = 2.5 V 5%, Ambient Temperature -10C to +80C
Parameter
Input Frequency Output Rise Time Output Fall Time Output Impedance Output Clock Duty Cycle
Symbol
fIN tOR tOF RO
Conditions
20% to 80%, Note 1 80% to 20%, Note 1 VO=VDDO/2 VDDO/2, 27 MHz, Note 1 VDDO/2, Note 1 All outputs
Min.
0.7 0.7 33 40 45 30
Typ.
27 1.5 1.5 46 50 50 0 35 150
Max. Units
MHz 2.2 2.2 68 60 55 40 300 600 800 1.2 ns ns % % ppm kHz ps ps ps ns ns ms ns ns ns
Frequency Synthesis Error Modulation Rate Short Term Jitter Long Term Jitter Long Term Jitter Long Term Jitter Long Term Jitter Power-up Time Output Enable Time Output Disable Time Switching Time Note 1: Measured with a 5 pF load. tPU
Cycle-to-Cycle 27 MHz, n=1000 48 MHz, n=1000 22M and 22/24M, n=1000 37 MHz non-spread, n=1000 From minimum VDD to outputs stable
1.5 1.5
6 3 50 20 100
22/24M, Note 2
Note 2: Finish from prior cycle to start of new cycle.
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P R E L I M I N A RY I N F O R M AT I O N
ICS1493-17 Clock Synthesizer for Portable Systems
AC Electrical Characteristics
Unless stated otherwise, VDDO = 1.8 V 0.1 V, Ambient Temperature -10C to +80C
Parameter
Input Frequency Output Rise Time Output Fall Time Output Impedance Output Clock Duty Cycle
Symbol
fIN tOR tOF RO
Conditions
20% to 80%, Note 1 80% to 20%, Note 1 VO=VDDO/2 VDDO/2, 27 MHz, Note 1 VDDO/2, Note 1 Note 1 All outputs
Min.
1.1 1.1 33 40 45
Typ.
27 2.2 2.2 46 50 50 225 0
Max. Units
MHz 3.3 3.3 68 60 55 ns ns % % ps ppm 40 375 900 750 1200 kHz ps ps ps ps ns ms ns ns ns
Absolute Clock Period Jitter Frequency Synthesis Error Modulation Rate Short Term Jitter Long Term Jitter Long Term Jitter Long Term Jitter Long Term Jitter Power-up Time Output Enable Time Output Disable Time Switching Time Note 1: Measured with a 5 pF load. tPU
30 Cycle-to-cycle 27 MHz, n=1000 48 MHz, n=1000 22M and 22/24M, n=1000 37 MHz, n=1000 From minimum VDD to outputs stable
35 225
2.5 1.5
9 4 50 20 250
22/24M, Note 2
Note 2: Finish from prior cycle to start of new cycle.
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ICS1493-17 Clock Synthesizer for Portable Systems
Serial Data Interface
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in the following table.
Bit
7 (6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'.
The block write and block read protocol is outlined in the table below, followed by the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Block Write Protocol Bit
1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command code -- 8 bit `00000000' stands for block operation Acknowledge from slave Byte count -- 8 bits Acknowledge from slave Data byte 0 -- 8 bits Acknowledge from slave Data byte 1 -- 8 bits Acknowledge from slave ............................. Data byte (N-1) -- 8 bits Acknowledge from slave Data byte N -- 8 bits Acknowledge from slave Stop
Block Read Protocol Bit
1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command code - 8 bit `00000000' stands for block operation Acknowledge from slave Repeat start Slave address -- 7 bits Read = 1 Acknowledge from slave Byte count from slave -- 8 bits Acknowledge from master Data byte from slave -- 8 bits Acknowledge from master Data byte from slave -- 8 bits Acknowledge from master Data byte N from slave -- 8 bits Not Acknowledge from master Stop
Description
Description
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ICS1493-17 Clock Synthesizer for Portable Systems
.
Byte Write Protocol Bit
1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command code -- 8 bit `10000000' stands for byte operation, bits[1:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master-- 8 bits Acknowledge from slave Stop
Byte Read Protocol Bit
1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command code -- 8 bit `10000000' stands for byte operation, bits[1:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address -- 7 bits Read = 1 Acknowledge from slave Data byte from slave -- 8 bits Not Acknowledge from master Stop
Description
Description
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Byte 0: Vendor ID, Revision Code
Bit
7 6 5 4 3 2 1 0
@Pup
0 0 0 1 1 1 1 1
Name
Revision Code(MSB) Revision Code Revision Code Revision Code(LSB) Vendor ID(MSB) Vendor ID Vendor ID Vendor ID(LSB)
Description
Revision Code Revision Code Revision Code Revision Code Vendor ID Vendor ID Vendor ID Vendor ID
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ICS1493-17 Clock Synthesizer for Portable Systems
Byte 1: Control Register
Bit
7 6
@Pup
1 1
Name
REF 37SS
Description
REF Output Enable 0 = Disable, Output pulled low, 1 = Enable 37SS Output Enable 0 = Disable, Output pulled low, corresponding PLL shut off. 1 = Enable 48M Output Enable 0 = Disable, Output pulled low, 1 = Enable 22/24M Clock Output Enable 0 = Disable, Output pulled low, 1 = Enable 22M Output Enable 0 = Disable, Output pulled low and corresponding PLL off, 1 = Enable Reserved Reserved 22/24M Clock Select 1 = 24.576 MHz, 0 = 22.5792 MHz
5 4 3
1 1 0
48M 22/24M 22M
2 1 0
1 1 1
Reserved Reserved 22/24M SEL
Byte 2: Control Register
Bit
7 6 5 4 3 2 1 0
@Pup
0 0 0 0 0 0 1 0
Name
Reserved Reserved Reserved Reserved Reserved SS Table SS Table SS Table Reserved Reserved Reserved Reserved Reserved
Description
Bit 2:0=000: No Spread Bit 2:0=001: -0.5% Spread Bit 2:0=010:-1.0% Spread Bit 2:0=011: No Spread Bit 2:0=100: -2.0% Spread Bit 2:0=101: No Spread Bit 2:0=110: -3.0% Spread Bit 2:0=111: No Spread
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ICS1493-17 Clock Synthesizer for Portable Systems
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA
Conditions
Still air 1 m/s air flow 2.5 m/s air flow
Min.
Typ.
39 36 34
Max. Units
C/W C/W C/W
Marking Diagram
1 16
6
93K17L ###### YYWW 11
Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year and the week number that the part was assembled. 3. "L" denotes Pb (lead) free package. 4. Bottom marking: (origin). Origin = country of origin if not USA.
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P R E L I M I N A RY I N F O R M AT I O N
ICS1493-17 Clock Synthesizer for Portable Systems
Package Outline and Package Dimensions (20-pin QFN)
Package dimensions are kept current with JEDEC Publication No. 95
Seating Plane Index Area N 1 2 A1 A3 Anvil Singulation -- or -Top View Sawn Singulation A E2 E2 (ND-1)x e (Ref) L N 1 2 (Ref) ND & NE Even e 2 (Typ) If ND & NE are Even (NE-1)x e (Ref)
E
2 b e D2 2 D2
D
(Ref) ND & NE Odd
Thermal Base
0.08 C
C
Symbol
Min
Millimeters Max
A A1 A3 b e N ND NE D x E BASIC D2 E2 L
0.80 1.00 0 0.05 0.20 Reference 0.18 0.30 0.50 BASIC 20 5 5 4.00 x 4.00 1.95 2.25 1.95 2.25 0.45 0.75
Ordering Information
Part / Order Number
ICS1493K-17LF ICS1493K-17LFT
Marking
see page 10
Shipping Packaging
Tubes Tape and Reel
Package
20-pin QFN 20-pin QFN
Temperature
-10 to +80C -10 to +80C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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