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| M58LR256GU, M58LR256GL M58LR128GU, M58LR128GL 128 and 256Mbit (x16, Mux I/O, Multiple Bank, Multi-Level, Burst) 1.8V supply Flash memories Feature summary Supply voltage - VDD = 1.7V to 2.0V for program, erase and read - VDDQ = 1.7V to 2.0V for I/O Buffers - VPP = 9V for fast program Multiplexed address/data Synchronous / Asynchronous Read - Synchronous Burst Read mode: 66MHz - Random Access: 85ns (M58LR128GU/L) 90ns (M58LR256GU/L) Synchronous Burst Read Suspend Programming time - 10s typical Word program time using Buffer Enhanced Factory Program command Memory organization - Multiple Bank Memory Array: 16 Mbit (M58LR256GU/L) or 8 Mbit (M58LR128GU/L) Banks - Parameter Blocks (Top or Bottom location) Dual operations - program/erase in one Bank while read in others - No delay between read and write operations Block locking - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WP for Block Lock-Down - Absolute Write Protection with VPP = VSS Security - 64 bit unique device number - 2112 bit user programmable OTP Cells Common Flash Interface (CFI) FBGA VFBGA44 (ZC) 8 x 10mm VFBGA44 (ZB) 7.7 x 9mm 100,000 program/erase cycles per block Electronic signature - Manufacturer Code: 20h - Top Device Codes: M58LR256GU: 882Ch M58LR128GU: 882Eh - Bottom Device Codes M58LR256GL: 882Dh M58LR128GL: 882Fh ECOPACK(R) packages available June 2006 Rev 1 1/114 www.st.com 1 Contents M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Contents 1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 Address Inputs (ADQ0-ADQ15 and A16-Amax) . . . . . . . . . . . . . . . . . . . 15 Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VPP Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 4.2 4.3 4.4 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Contents 4.5 4.6 4.7 4.8 4.9 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 26 4.9.1 4.9.2 4.9.3 Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program and Verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10 4.11 4.12 4.13 4.14 4.15 4.16 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 36 Erase Suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Erase status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Program Suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Bank Write/Multiple Word Program status bit (SR0) . . . . . . . . . . . . . . . . 38 6 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Read Select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 X-Latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Wait Polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Data Output Configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Wait Configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Burst Type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Valid Clock Edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3/114 Contents M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 6.8 6.9 Wrap Burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1 7.2 7.3 Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.1 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 9 Dual operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . 50 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 9.2 9.3 9.4 9.5 Reading a block's Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 53 10 11 12 13 14 Program and Erase times and endurance cycles . . . . . . . . . . . . . . . . . 55 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M58LR256GU/L bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M58LR128GU/L bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Electronic Signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 X-latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Configuration Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Wait at the boundary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Program/Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Reset and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 VFBGA44 8 x 10mm - 10 x 4 ball array, 0.50mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 VFBGA44 7.7 x 9mm - 10 x 4 ball array, 0.50mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 M58LR256GU - Parameter Bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M58LR256GU - Main Bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 M58LR256GU - Block addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 M58LR256GL - Parameter Bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 M58LR256GL - Main Bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 M58LR256GL - Block addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 M58LR128GU - Parameter Bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 M58LR128GU - Main Bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 M58LR128GU - Block addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 M58LR128GL - Parameter Bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 M58LR128GL - Main Bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 M58LR128GL - Block addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5/114 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Bank and Erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Bank and Erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Bank and Erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Command interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 107 Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 111 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M58LR256GU/L memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 M58LR128GU/L memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 X-latency and data output configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous Random Access Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Synchronous Burst Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Single Synchronous Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous Burst Read Suspend AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Reset and Power-up AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 VFBGA44 8 x 10mm - 10 x 4 ball array, 0.50mm pitch, bottom view package outline. . . . 72 VFBGA44 7.7 x 9mm - 10 x 4 ball array, 0.50mm pitch, bottom view package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 VFBGA44 daisy chain - package connections (top view through package) . . . . . . . . . . . . 76 VFBGA44 daisy chain - PCB connection proposal (top view through package). . . . . . . . . 77 Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Buffer Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 99 Block Erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . 103 Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . 104 7/114 Summary description M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 1 Summary description The M58LR128GU/L and M58LR256GU/L are 128 Mbit (8 Mbit x16) and 256 Mbit (16 Mbit x16) non-volatile Flash memories, respectively. They will be referred to as M58LRxxxGU/L in the rest of the document unless otherwise specified. The M58LRxxxGU/L may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.7V to 2.0V VDD supply for the circuitry and a 1.7V to 2.0V VDDQ supply for the Input/Output pins. An optional 9V VPP power supply is provided to speed up factory programming. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A23 (M58LR256GU/L) or A16-A22 (M58LR128GU/L) are the Most Significant Bit addresses. The devices feature an asymmetrical block architecture and are based on a multi-level cell technology. M58LR256GU/L has an array of 259 blocks, and is divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 15 main blocks of 64 KWords. M58LR128GU/L has an array of 131 blocks, and is divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Tables 2 and 3, and the memory maps are shown in Figures 3 and 4. The Parameter Blocks are located at the top of the memory address space for the M58LR256GU and M58LR128GU, and at the bottom for the M58LR256GL and M58LR128GL. Each block can be erased separately. Erase can be suspended, in order to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There is a Buffer Enhanced Factory programming command available to speed up programming. Program and erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 66MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. 8/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Summary description The M58LRxxxGU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power- up. The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 64 bit segment OneTime-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 5, shows the Protection Register Memory Map. The M58LR256GU/L is offered in a VFBGA44, 8 x 10mm, 0.50mm pitch package whereas the M58LR128GU/L is offered in a VFBGA44, 7.7 x 9mm, 0.50mm pitch package. The memories are supplied with all the bits erased (set to '1'). Figure 1. Logic diagram VDD VDDQ VPP 16 A16-Amax(1) W E G RP WP L K M58LR256GU M58LR256GL M58LR128GU M58LR128GL WAIT ADQ0ADQ15 VSS VSSQ AI10088 1. Amax is equal to A22 for the M58LR128GU/L and to A23 for the M58LR256GU/L. 9/114 Summary description Table 1. A16-Amax (1) M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Signal names Address Inputs Data Input/Outputs or Address Inputs, Command Inputs Chip Enable Output Enable Write Enable Reset Write Protect Clock Latch Enable Wait Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Ground Input/Output Supply Not Connected Internally Do Not Use ADQ0-ADQ15 E G W RP WP K L WAIT VDD VDDQ VPP VSS VSSQ NC DU 1. Amax is equal to A22 for the M58LR128GU/L and to A23 for the M58LR256GU/L. 10/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 2. VFBGA connections (top view through package) Summary description NC 13 14 VSSQ ADQ8 ADQ12 A23(1) ADQ13 2 ADQ15 VDDQ WAIT VSS 3 ADQ14 ADQ7 A21 A16 4 VSSQ ADQ6 VSS A20 5 ADQ5 K 6 L ADQ4 VDD 7 ADQ11 ADQ3 RP 8 W ADQ10 ADQ2 VPP WP 9 VDDQ ADQ9 A19 A18 10 ADQ1 A17 11 E ADQ0 A22 12 G NC G C D 1. Ball D7 is A23 in the M58LR256GU/L. It is Not Connected Internally (NC) in the M58LR128GU/L. H A B E F NC 1 NC 11/114 ai10089 Summary description Table 2. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL M58LR256GU/L bank architecture Bank Size 16 Mbits 16 Mbits 16 Mbits 16 Mbits ---Parameter Blocks 4 blocks of 16 KWords ---Main Blocks 15 blocks of 64 KWords 16 blocks of 64 KWords 16 blocks of 64 KWords 16 blocks of 64 KWords ---16 blocks of 64 KWords 16 blocks of 64 KWords Main Blocks 7 blocks of 64 KWords 8 blocks of 64 KWords 8 blocks of 64 KWords 8 blocks of 64 KWords ---8 blocks of 64 KWords 8 blocks of 64 KWords ---- Number Parameter Bank Bank 1 Bank 2 Bank 3 ---Bank 14 Bank 15 16 Mbits 16 Mbits - Table 3. M58LR128GU/L bank architecture Bank Size 8 Mbits 8 Mbits 8 Mbits 8 Mbits ---Parameter Blocks 4 blocks of 16 KWords Number Parameter Bank Bank 1 Bank 2 Bank 3 ---Bank 14 Bank 15 8 Mbits 8 Mbits 12/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 3. M58LR256GU/L memory map M58LR256GU - Top Boot Block Address lines A23-A16 and ADQ15-ADQ0 000000h 00FFFFh Bank 15 0F0000h 0FFFFFh 64 KWord 64 KWord 16 Main Blocks Parameter Bank Summary description M58LR256GL - Bottom Boot Block Address lines A23-A16 and ADQ15-ADQ0 000000h 003FFFh 00C000h 00FFFFh 010000h 01FFFFh 0F0000h 0FFFFFh 100000h 10FFFFh Bank 1 1F0000h 1FFFFFh 200000h 20FFFFh Bank 2 2F0000h 2FFFFFh 300000h 30FFFFh Bank 3 3F0000h 3FFFFFh 64 KWord 64 KWord 64 KWord 16 Main Blocks 64 KWord 64 KWord 16 Main Blocks 16 KWord 4 Parameter Blocks 16 KWord 64 KWord 15 Main Blocks 64 KWord 64 KWord 16 Main Blocks C00000h C0FFFFh Bank 3 CF0000h CFFFFFh D00000h D0FFFFh Bank 2 DF0000h DFFFFFh E00000h E0FFFFh Bank 1 EF0000h EFFFFFh F00000h F0FFFFh FE0000h FEFFFFh FF0000h FF3FFFh FFC000h FFFFFFh 64 KWord 16 Main Blocks 64 KWord 64 KWord 16 Main Blocks 64 KWord 64 KWord 16 Main Blocks 64 KWord 64 KWord 15 Main Blocks 64 KWord 16 KWord 4 Parameter Blocks Bank 15 16 KWord Parameter Bank F00000h F0FFFFh FF0000h FFFFFFh 64 KWord 16 Main Blocks 64 KWord AI09317 13/114 Summary description Figure 4. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL M58LR128GU/L memory map M58LR128GU - Top Boot Block Address lines A22-A16 and ADQ15-ADQ0 000000h 00FFFFh 64 KWord 8 Main Blocks 64 KWord Parameter Bank M58LR128GL - Bottom Boot Block Address lines A22-A16 and ADQ15-ADQ0 000000h 003FFFh 00C000h 00FFFFh 010000h 01FFFFh 070000h 07FFFFh 080000h 08FFFFh Bank 1 0F0000h 0FFFFFh 100000h 10FFFFh Bank 2 170000h 17FFFFh 180000h 18FFFFh Bank 3 1F0000h 1FFFFFh 7 Main Blocks 64 KWord 16 KWord 4 Parameter Blocks Bank 15 16 KWord 780000h 78FFFFh 7F0000h 7FFFFFh 64 KWord 8 Main Blocks 64 KWord 64 KWord 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 16 KWord 4 Parameter Blocks 16 KWord 64 KWord 7 Main Blocks 64 KWord 64 KWord 8 Main Blocks Bank 15 070000h 07FFFFh 600000h 60FFFFh Bank 3 670000h 67FFFFh 680000h 68FFFFh Bank 2 6F0000h 6FFFFFh 700000h 70FFFFh Bank 1 770000h 77FFFFh 780000h 78FFFFh 7E0000h 7EFFFFh 7F0000h 7F3FFFh 7FC000h 7FFFFFh 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord Parameter Bank AI09861 14/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Signal descriptions 2 Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address Inputs (ADQ0-ADQ15 and A16-Amax) Amax is equal to A23 in the M58LR256GU/L and to A22 in the M58LR128GU/L. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. 2.2 Data Input/Output (ADQ0-ADQ15) The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. 2.3 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. 2.4 Output Enable (G) The Output Enable input controls data outputs during the Bus Read operation of the memory. 2.5 Write Enable (W) The Write Enable input controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. 2.6 Write Protect (WP) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 18: Lock status). 15/114 Signal descriptions M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 2.7 Reset (RP) The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 23: DC characteristics - currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 24: DC characteristics - voltages). 2.8 Latch Enable (L) Latch Enable latches the ADQ0-ADQ15 and A16-Amax address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. 2.9 Clock (K) The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations. 2.10 Wait (WAIT) Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is forced deasserted when Output Enable is at VIH. 2.11 VDD supply voltage VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). 2.12 VDDQ supply voltage VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. 16/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Signal descriptions 2.13 VPP Program supply voltage VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 23 and 24, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. 2.14 VSS ground VSS ground is the reference for the core supply. It must be connected to the system ground. 2.15 VSSQ ground VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 9: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents. 17/114 Bus operations M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 3 Bus operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 4: Bus operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. 3.1 Bus Read Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 10, 11 and 12 Read AC Waveforms, and Tables 25 and 26 Read AC Characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the write operation by toggling Latch Enable. In this case the Latch Enable must be tied to VIH during the bus write operation. See Figures 15 and 16, Write AC Waveforms, and Tables 27 and 28, Write AC Characteristics, for details of the timing requirements. 3.3 Address Latch Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable. 3.4 Output Disable The outputs are high impedance when the Output Enable is at VIH. 18/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Bus operations 3.5 Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. 3.6 Reset During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. Table 4. Bus operations(1) E VIL VIL VIL VIL VIH X G VIL VIH VIH VIH X X W VIH VIL X VIH X X L VIH VIH VIL VIH X X RP VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z WAIT(2) ADQ15-ADQ0 Data Output Data Input Address Input Hi-Z Hi-Z Hi-Z Operation Bus Read Bus Write Address Latch Output Disable Standby Reset 1. X = Don't care. 2. WAIT signal polarity is configured using the Set Configuration Register command. 19/114 Command interface M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 4 Command interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. Refer to Table 5: Command codes, Table 6: Standard commands, Table 7: Factory Program command, and Appendix D: Command interface state tables, for a summary of the Command Interface. Table 5. Command codes Command Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Program Setup Clear Status Register Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Buffer Enhanced Factory Program Read Electronic Signature Read CFI Query Program/Erase Suspend Protection Register Program Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm or Buffer Program Confirm Buffer Program Read Array Hex Code 01h 03h 10h 20h 2Fh 40h 50h 60h 70h 80h 90h 98h B0h C0h D0h E8h FFh 20/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface 4.1 Read Array command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read Array mode, subsequent read operations will output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank will return to Read Array mode but the program or erase operation will continue, however the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected. 4.2 Read Status Register command The device contains a Status Register that is used to monitor program or erase operations. The Read Status Register command is used to read the contents of the Status Register for the addressed bank. One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in Read Status Register mode, subsequent read operations will output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Status Register. A Read Array command is required to return the bank to Read Array mode. See Table 10 for the description of the Status Register Bits. 21/114 Command interface M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 4.3 Read Electronic Signature command The Read Electronic Signature command is used to read the Manufacturer and Device Codes, the Lock Status of the addressed bank, the Protection Register, and the Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank is in Read Electronic Signature mode, subsequent read operations in the same bank will output the Manufacturer Code, the Device Code, the Lock Status of the addressed bank, the Protection Register, or the Configuration Register (see Table 8). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. Dual operations between the Parameter bank and the Electronic Signature location are not allowed (see Table 17: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. The Read Electronic Signature command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode. 4.4 Read CFI Query command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank read from the Common Flash Interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to program or erase in the background. The Read CFI Query command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 17: Dual operation limitations for details). See Appendix B: Common Flash Interface, Tables 45, 46, 47, 48, 49, 51, 52, 53 and 54 for details on the information contained in the Common Flash Interface memory area. 22/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface 4.5 Clear Status Register command The Clear Status Register command can be used to reset (set to `0') all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new program or erase command. 4.6 Block Erase command The Block Erase command is used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Block Erase command. The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters Read Status Register mode and any read operation within the addressed bank will output the contents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. The Block Erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Block Erase operation is aborted, the block must be erased again. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 19: Program/Erase times and endurance cycles. See Appendix C, Figure 25: Block Erase flowchart and pseudo code, for a suggested flowchart for using the Block Erase command. 23/114 Command interface M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 4.7 Program command The program command is used to program a single Word to the memory array. If the block being programmed is protected, then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the Program Command. The first bus cycle sets up the Program command. The second latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, read operations in the bank being programmed output the Status Register content. During a Program operation, the bank containing the Word being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. A Read Array command is required to return the bank to Read Array mode. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 19: Program/Erase times and endurance cycles. The Program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the block must be erased before retrying the programming operation. See Appendix C, Figure 22: Program flowchart and pseudo code, for the flowchart for using the Program command. 24/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface 4.8 Buffer Program command The Buffer Program Command makes use of the device's 32-Word Write Buffer to speed up programming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard nonbuffered Program command. Four successive steps are required to issue the Buffer Program command. 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first Bus Write cycle, read operations in the bank will output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of Words to be programmed. Value n is written to the same block address, where n+1 is the number of Words to be programmed. Use n+1 Bus Write cycles to load the address and data for each Word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32 Word boundary. If the start address is not aligned to a 32 word boundary, the total programming time is doubled The final Bus Write cycle confirms the Buffer Program command and starts the program operation. 3. 4. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not accepted. Clear the Status Register before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. During Buffer Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 23: Buffer Program flowchart and pseudo code, for a suggested flowchart on using the Buffer Program command. 25/114 Command interface M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 4.9 Buffer Enhanced Factory Program command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. If the block being programmed is protected, then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The use of the Buffer Enhanced Factory Program command requires certain operating conditions: VPP must be set to VPPH VDD must be within operating range Ambient temperature TA must be 30C 10C The targeted block must be unlocked The start address must be aligned with the start of a 32 Word buffer boundary The address must remain the Start Address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase, Please refer to Table 7: Factory Program command for detail information. 4.9.1 Setup phase The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the command. The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. The second Bus Write cycle confirms the command. After the confirm command is issued, read operations output the contents of the Status Register. The read Status Register command must not be issued as it will be interpreted as data to program. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to `1') and the Buffer Enhanced Factory Program operation is terminated. See Status Register section for details on the error. 26/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface 4.9.2 Program and Verify phase The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 Words). To program less than 32 Words, the remaining Words should be programmed with FFFFh. Three successive steps are required to issue and execute the Program and Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address must remain the Start Address as the P/E.C. increments the address location.If any address that is not in the same block as the Start Address is given, the Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. Once the Write Buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary. 2. 3. The Program and Verify phase can be repeated, without re-issuing the command, to program additional 32 Word locations as long as the address remains in the same block. 4. Finally, after all Words, or the entire block have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate Program and Verify Phase. Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed. 4.9.3 Exit phase Status Register P/E.C. bit SR7 set to `1' indicates that the device has exited the Buffer Enhanced Factory Program operation and returned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical program times are given in Table 19. See Appendix C, Figure 29: Buffer Enhanced Factory Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Enhanced Factory Program command. 27/114 Command interface M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 4.10 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to `1'. The following commands are accepted during Program/Erase Suspend: Program/Erase Resume Read Array (data from erase-suspended block or program-suspended Word is not valid) Read Status Register Read Electronic Signature Read CFI Query. Additionally, if the suspended operation was a Block Erase then the following commands are also accepted: Clear Status Register Program (except in erase-suspended block) Buffer Program (except in erase suspended blocks) Block Lock Block Lock-Down Block Unlock. During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-Down commands. When the Program/Erase Resume command is issued the operation will complete. It is possible to accumulate multiple suspend operations. For example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. If a Program command is issued during a Block Erase Suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. Refer to Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 24: Program Suspend & Resume flowchart and pseudo code, and Figure 26: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using the Program/Erase Suspend command. 28/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface 4.11 Program/Erase Resume command The Program/Erase Resume command is used to restart the program or erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 24: Program Suspend & Resume flowchart and pseudo code, and Figure 26: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using the Program/Erase Resume command. 4.12 Protection Register Program command The Protection Register Program command is used to program the user One-TimeProgrammable (OTP) segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 5: Protection Register memory map. The segments are programmed one Word at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two Bus Write cycles are required to issue the Protection Register Program command. The first bus cycle sets up the Protection Register Program command. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the program operation has started. Attempting to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Table 17: Dual operation limitations for details) The two Protection Register Locks are used to protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 5: Protection Register memory map2, and 29/114 Command interface M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 4.13 Set Configuration Register command The Set Configuration Register command is used to write a new value to the Configuration Register. Two Bus Write cycles are required to issue the Set Configuration Register command. The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the confirm command. The Configuration Register data must be written as an address during the bus write cycles, that is ADQ0 = CR0, ADQ1 = CR1, ..., ADQ15 = CR15. Addresses A16-Amax are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register. 4.14 Block Lock command The Block Lock command is used to lock a block and prevent program or erase operations from changing the data in it. All blocks are locked after power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. The first bus cycle sets up the Block Lock command. The second Bus Write cycle latches the block address and locks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 18 shows the Lock Status after issuing a Block Lock command. Once set, the Block Lock bits remain set even after a hardware reset or power-down/powerup. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 27: Locking operations flowchart and pseudo code, for a flowchart for using the Lock command. 4.15 Block Unlock command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command. The first bus cycle sets up the Block Unlock command. The second Bus Write cycle latches the block address and unlocks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 18 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 27: Locking operations flowchart and pseudo code, for a flowchart for using the Block Unlock command. 30/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface 4.16 Block Lock-Down command The Block Lock-Down command is used to lock-down a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. The first bus cycle sets up the Block Lock-Down command. The second Bus Write cycle latches the block address and locks-down the block. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 18 shows the Lock Status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 27: Locking operations flowchart and pseudo code, for a flowchart for using the Lock-Down command. 31/114 Command interface Table 6. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Standard commands(1) Bus Operations Cycles Commands 1st Cycle Op. Add BKA BKA BKA BKA X BKA or BA(3) BKA or WA(3) BA PA1 PAn+1 X X PRA CRD BKA or BA (3) 2nd Cycle Data FFh 70h 90h 98h 50h 20h 40h or 10h E8h PD1 PDn+1 B0h D0h C0h 60h 60h 60h 60h Write Write Write Write Write PRA CRD BA BA BA PRD 03h 01h D0h 2Fh Write Write Write Write Write BA WA BA PA2 X D0h PD n PD2 D0h Op. Read Read Read Read Add WA BKA(2) BKA (2) Data RD SRD ESD QD Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program 1+ 1+ 1+ 1+ 1 2 2 Write Write Write Write Write Write Write Write BKA(2) Buffer Program(4) n+4 Write Write Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down 1 1 2 2 2 2 2 Write Write Write Write Write Write Write BKA or BA(3) BKA or BA (3) 1. X = Don't Care, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 8. 3. Any address within the bank can be used. 4. n+1 is the number of Words to be programmed. 32/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 7. Factory Program command(1) Bus Write Operations Cycles Command Phase 1st Add Setup 2 BKA or WA(2) WA1 NOT BA1(4) 2nd 3rd Command interface Final -1 Add Data Final Add Data Data Add Data Add Data 80h PD1 X WA1 D0h WA1 PD2 WA1 PD3 Buffer Enhanced Program/ 32 Factory Verify(3) Program Exit 1 WA1 PD31 WA1 PD32 1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X = Don't Care. 2. Any address within the bank can be used. 3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block. 4. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1. Table 8. Electronic Signature codes Code Address (h) Bank Address + 00 Top Bank Address + 01 Bank Address + 01 Data (h) 0020 882C (M58LR256GU) 882E (M58LR128GU) 882D (M58LR256GL) 882F (M58LR128GL) 0001 0000 Block Address + 02 Locked and Locked-Down Unlocked and Locked-Down 0003 0002 Bank Address + 03 Bank Address + 05 Bank Address + 80 OTP Area Permanently Locked Bank Address + 81 Bank Address + 84 0000 Unique Device Number OTP Area PRLD(1) OTP Area DRC(1) CR(1) 0002 Manufacturer Code Device Code Bottom Locked Unlocked Block Protection Die Revision Code Configuration Register Protection Register PR0 Lock ST Factory Default Protection Register PR0 Bank Address + 85 Bank Address + 88 Protection Register PR1 through PR16 Lock Protection Registers PR1-PR16 Bank Address + 89 Bank Address + 8A Bank Address + 109 1. CR = Configuration Register, PRLD = Protection Register Lock Data, DRC = Die Revision Code. 33/114 Command interface Figure 5. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Protection Register memory map PROTECTION REGISTERS 109h PR16 User Programmable OTP 102h 91h PR1 User Programmable OTP 8Ah Protection Register Lock 89h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 88h 85h 84h PR0 User Programmable OTP Unique device number 81h 80h Protection Register Lock 10 AI07563 34/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 9. Protection Register locks Lock Description Number Address Bits Bit 0 Lock 1 80h Bit 1 Bits 2 to 15 Bit 0 Bit 1 Bit 2 ---Lock 2 89h Command interface preprogrammed to protect Unique Device Number, address 81h to 84h in PR0 protects 64bits of OTP segment, address 85h to 88h in PR0 reserved protects 128bits of OTP segment PR1 protects 128bits of OTP segment PR2 protects 128bits of OTP segment PR3 ---protects 128bits of OTP segment PR14 protects 128bits of OTP segment PR15 protects 128bits of OTP segment PR16 Bit 13 Bit 14 Bit 15 35/114 Status Register M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 5 Status Register The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during program and erase operations operations, if no Read Array command has been issued. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 10: Status Register bits. Refer to Table 10 in conjunction with the following text descriptions. 5.1 Program/Erase Controller status bit (SR7) The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. 5.2 Erase Suspend status bit (SR6) The Erase Suspend Status bit indicates that an erase operation has been suspended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. 36/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Status Register 5.3 Erase status bit (SR5) The Erase Status bit is used to identify if there was an error during a Block Erase operation. When the Erase Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command will appear to fail. 5.4 Program status bit (SR4) The Program Status bit is used to identify if there was an error during a program operation. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the Word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while VPP = VPPH will also set the Program Status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the Program Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail. 5.5 VPP status bit (SR3) The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage. when the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and program and erase operations cannot be performed. Once set High, the VPP Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail. 37/114 Status Register M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 5.6 Program Suspend status bit (SR2) The Program Suspend Status bit indicates that a program operation has been suspended in the addressed block. The Program Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. 5.7 Block Protection Status Bit (SR1) The Block Protection Status bit is used to identify if a Program or Block Erase operation has tried to modify the contents of a locked or locked-down block. When the Block Protection Status bit is High (set to `1'), a program or erase operation has been attempted on a locked or locked-down block. Once set High, the Block Protection Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail. 5.8 Bank Write/Multiple Word Program status bit (SR0) The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new Word to be programmed to the memory array. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to `0'), the addressed bank is executing a program or erase operation. When the Program/Erase Controller Status bit is Low (set to `0') and the Bank Write Status bit is High (set to `1'), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to `0'), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to `1') the device is not ready for the next Word. For further details on how to use the Status Register, see the Flowcharts and Pseudocodes provided in Appendix C. 38/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 10. Bit Status Register Status Register bits Name Type Logic Level(1) '1' Ready Busy Erase Suspended Erase In progress or Completed Erase Error Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Program Suspended Program In Progress or Completed Program/Erase on protected Block, Abort No operation to protected blocks SR7 = `1' Not Allowed '1' SR7 = `0' Program or erase operation in a bank other than the addressed bank No Program or erase operation in the device Program or erase operation in addressed bank Definition SR7 P/E.C. Status Status '0' '1' SR6 Erase Suspend Status Status '0' '1' SR5 Erase Status Error '0' '1' SR4 Program Status Error '0' '1' SR3 VPP Status Program Suspend Status Error '0' '1' Status '0' '1' SR2 SR1 Block Protection Status Error '0' Bank Write Status Status SR7 = `1' '0' SR7 = `0' SR0 SR7 = `1' Not Allowed Multiple Word Program Status (Buffer Enhanced Factory Program mode) '1' Status '0' SR7 = `0' 1. Logic level '1' is High, '0' is Low. the device is NOT ready for the next SR7 = `0' Buffer loading or is going to exit the BEFP mode SR7 = `1' the device has exited the BEFP mode the device is ready for the next Buffer loading 39/114 Configuration Register M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 6 Configuration Register The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a reset or power-up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 12. They specify the selection of the burst length, burst type, burst X latency and the read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. 6.1 Read Select bit (CR15) The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When the Read Select bit is set to '1', read operations are asynchronous; when the Read Select bit is set to '0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to '1' for asynchronous access. 6.2 X-Latency bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. Refer to Figure 6: X-latency and data output configuration example. For correct operation the X-Latency bits can only assume the values in Table 12: Configuration Register bits. Table 11 shows how to set the X-Latency parameter, taking into account the speed class of the device and the Frequency used to read the Flash memory in Synchronous mode. Table 11. fmax 30MHz 40MHz 54MHz 66MHz X-latency settings X-Latency min tKmin Speed 85ns (128Mbit) 33ns 25ns 19ns 15ns 3 3 4 5 Speed 90ns (256Mbit) 3 4 5 6 40/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Configuration Register 6.3 Wait Polarity bit (CR10) The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data output are valid or a WAIT state must be inserted. When the Wait Polarity bit is set to `0' the Wait signal is active Low. When the Wait Polarity bit is set to `1' the Wait signal is active High. 6.4 Data Output Configuration bit (CR9) The Data Output Configuration bit is used to configure the output to remain valid for either one or two clock cycles during synchronous mode. When the Data Output Configuration Bit is '0' the output data is valid for one clock cycle, when the Data Output Configuration Bit is '1' the output data is valid for two clock cycles. The Data Output Configuration must be configured using the following condition: tK > tKQV + tQVK_CPU tK is the clock period tQVK_CPU is the data setup time required by the system CPU tKQV is the clock to data valid time where: If this condition is not satisfied, the Data Output Configuration bit should be set to `1' (two clock cycles). Refer to Figure 6: X-latency and data output configuration example. 6.5 Wait Configuration bit (CR8) The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in Synchronous Burst Read mode. When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait Configuration bit is Low (set to '0') the Wait output pin is asserted during the WAIT state. When the Wait Configuration bit is High (set to '1'), the Wait output pin is asserted one data cycle before the WAIT state. 6.6 Burst Type bit (CR7) The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads. The Burst Type bit is High (set to '1'), as the memory outputs from sequential addresses only. See Table 13: Burst type definition, for the sequence of addresses output from a given starting address in sequential mode. 41/114 Configuration Register M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 6.7 Valid Clock Edge bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during synchronous read operations. When the Valid Clock Edge bit is Low (set to '0') the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to '1') the rising edge of the Clock is the active edge. 6.8 Wrap Burst bit (CR3) The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to `0') the burst read wraps. When it is High (set to `1') the burst read does not wrap. 6.9 Burst length bits (CR2-CR0) The Burst Length bits are used to set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 Words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is aligned to an 8 Word boundary no WAIT states are needed and the WAIT output is not asserted. If the starting address is not aligned to the 8 Word boundary, WAIT will be asserted when the burst sequence crosses the first 16 Word boundary to indicate that the device needs an internal delay to read the successive Words in the array. In the worst case, the number of WAIT states is one clock cycle less than the latency setting. The exact number is reported in Table 14: Wait at the boundary. WAIT will be asserted only once during a continuous burst access. See also Section Table 13.: Burst type definition. CR14, CR5 and CR4 are reserved for future use. 42/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 12. Bit CR15 CR14 Configuration Register Configuration Register bits Description Read Select 1 Reserved 010 011 100 2 clock latency(1) 3 clock latency 4 clock latency 5 clock latency 6 clock latency 7 clock latency (default) Asynchronous Read (Default at power-on) Value 0 Description Synchronous Read CR13-CR11 X-Latency 101 110 111 Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data Output Configuration 0 1 0 CR8 Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 CR5-CR4 CR3 Valid Clock Edge 1 Reserved 0 Wrap Burst 1 001 010 CR2-CR0 Burst Length 011 111 16 Words Continuous (default) No Wrap (default) 4 Words 8 Words Wrap Rising Clock edge (default) Sequential (default) Falling Clock edge WAIT is active High Data held for one clock cycle Data held for two clock cycles (default)(1) WAIT is active during WAIT state (default) WAIT is active one data cycle before WAIT state(1) Reserved WAIT is active Low (default) 1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported. 43/114 Configuration Register Table 13. Mode Start Add. 0 1 2 3 ... Wrap 7 ... 12 13 14 15 0 1 2 3 ... No-wrap 7 ... 12 13 14 15 12-13-14-15 13-14-15-16 14-15-16-17 15-16-17-18 7-8-9-10 12-13-14-15 13-14-15-12 14-15-12-13 15-12-13-14 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 7-4-5-6 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Burst type definition Sequential Continuous Burst 4 Words 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 Words 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 16 Words 0-1-2-3-4-5-6-7-8-9-10-11-1213-14-15 1-2-3-4-5-6-7-8-9-10-11-12-1314-15-0 2-3-4-5-6-7-8-9-10-11-12-1314-15-0-1 3-4-5-6-7-8-9-10-11-12-13-1415-0-1-2 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-27-8-9-10-11-12-13... 3-4-5-6 12-13-14-15-8-910-11 13-14-15-8-9-1011-12 14-15-8-9-10-1112-13 15-8-9-10-11-1213-14 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9... 3-4-5-6-7-8-9-10 12-13-14-15-0-1-2-3-4-5-6-7-89-10-11 13-14-15-0-1-2-3-4-5-6-7-8-910-11-12 14-15-0-1-2-3-4-5-6-7-8-9-1011-12-13 15-0-1-2-3-4-5-6-7-8-9-10-1112-13-14 0-1-2-3-4-5-6-7-8-9-10-11-1213-14-15 1-2-3-4-5-6-7-8--9-10-11-12-1314-15-16 2-3-4-5--6-7-8-9-10-11-12-1314-15-16-17 3-4-5-6-7-8-9-10-11-12-13-1415-16-17-18 12-13-14-15-1617... 13-14-15-16-1718... 14-15-16-17-1819... 15-16-17-18-1920... 7-8-9-10-11-1213-14 7-8-9-10-11-12-13-14-15-1617-18-19-20-21-22 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst) 12-13-14-15-1617-18-19 13-14-15-16-1718-19-20 14-15-16-17-1819-20-21 15-16-17-18-1920-21-22 12-13-14-15-16-17-18-19-2021-22-23-24-25-26-27 13-14-15-16-17-18-19-20-2122-23-24-25-26-27-28 14-15-16-17-18-19-20-21-2223-24-25-26-27-28-29 15-16-17-18-19-20-21-22-2324-25-26-27-28-29-30 44/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 14. Start Address 0 1 2 3 4 5 6 7 Configuration Register Wait at the boundary Number of WAIT states X-Latency = 7 X-Latency = 6 X-Latency = 5 X-Latency = 4 X-Latency = 3 X-Latency = 2 0 0 1 2 3 4 5 6 0 0 0 1 2 3 4 5 0 0 0 0 1 2 3 4 0 0 0 0 0 1 2 3 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 1 Figure 6. X-latency and data output configuration example X-latency 1st cycle 2nd cycle 3rd cycle 4th cycle K E L Amax-A16(1) VALID ADDRESS tQVK_CPU tKQV tK ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA AI10977 1. Amax is equal to A22 for the M58LR128GU/L and to A23 for the M58LR256GU/L. 2. The settings shown are X-latency = 4, Data Output held for one clock cycle. 45/114 Configuration Register Figure 7. E M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Wait configuration example K L G Amax-A16(1) VALID ADDRESS ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA NOT VALID VALID DATA WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1' AI10091 1. Amax is equal to A22 for the M58LR128GU/L and to A23 for the M58LR256GU/L. 46/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Read modes 7 Read modes Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (See Configuration Register section for details). All banks support both asynchronous and synchronous read operations. 7.1 Asynchronous Read mode In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for asynchronous operations. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always deasserted. See Table 25: Asynchronous Read AC characteristics, Figure 10: Asynchronous Random Access Read AC waveforms, for details. 47/114 Read modes M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 7.2 Synchronous Burst Read mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 Word boundary (Wrap) or overcome the boundary (No Wrap). The WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word burst. It is only deasserted when output data are valid or when G is at VIH. In Continuous Burst Read mode a WAIT state will occur when crossing the first 16 Word boundary. If the starting address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 26: Synchronous Read AC characteristics, and Figure 11: Synchronous Burst Read AC waveforms, for details. 48/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Read modes 7.2.1 Synchronous Burst Read Suspend A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output), or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT being gated by E, it will remain active and will not revert to high impedance when G goes High. So if two or more devices are connected to the system's READY signal, to prevent bus contention the WAIT signal of the M58LRxxxGU/L should not be directly connected to the system's READY signal. WAIT will revert to high-impedance when Chip Enable, E, goes High. See Table 26: Synchronous Read AC characteristics, and Figure 13: Synchronous Burst Read Suspend AC waveforms, for details. 7.3 Single Synchronous Read mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is deasserted when Output Enable, G, is at VIH or for the one clock cycle during which output data is valid. Otherwise, it is asserted. See Table 26: Synchronous Read AC characteristics, and Figure 11: Synchronous Burst Read AC waveforms, for details. 49/114 Dual operations and Multiple Bank architecture M58LR256GU, M58LR256GL, M58LR128GU, 8 Dual operations and Multiple Bank architecture The Multiple Bank architecture of the M58LRxxxGU/L gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The Dual Operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in read mode. Bus Read operations are allowed in another bank between setup and confirm cycles of program or erase operations. By using a combination of these features, read operations are possible at any moment in the M58LRxxxGU/L device. Dual operations between the Parameter Bank and either of the CFI, the OTP or the Electronic Signature memory space are not allowed. Table 17 shows which dual operations are allowed or not between the CFI, the OTP, the Electronic Signature locations and the memory array. Tables 15 and 16 show the dual operations possible in other banks and in the same bank. Table 15. Dual operations allowed in other banks Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Read Read Status CFI Electronic Register Query Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Program, Buffer Program Yes - - - Yes Block Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes Idle Programming Erasing Program Suspended Erase Suspended 50/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Dual operations and Multiple Bank arTable 16. Dual operations allowed in same bank Commands allowed in same bank Status of bank Read Array Yes - (1) (1) Read Read Read Program, Status CFI Electronic Buffer Register Query Signature Program Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - - - Yes(2) Block Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes Idle Programming Erasing Program Suspended Erase Suspended - Yes(2) Yes(2) 1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed. 2. Not allowed in the Word that is being erased or programmed. Table 17. Dual operation limitations Commands allowed Read Main Blocks Current Status Read CFI / OTP / Electronic Signature Read Parameter Blocks Located in Parameter Bank No Not Located in Parameter Bank Yes Programming / Erasing Parameter Blocks Located in Parameter Bank Not Located in Parameter Bank No No Yes No No Yes Programming / Erasing Main Blocks Yes No Yes No Yes No In Different Bank Only No Programming OTP 51/114 Block locking M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 9 Block locking The M58LRxxxGU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows software only control of block locking. Lock-Down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to Locked, Unlocked, and Locked-Down. Table 18, defines all of the possible protection states (WP, ADQ1, ADQ0), and Appendix C, Figure 27, shows a flowchart for the locking operations. 9.1 Reading a block's Lock status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 8, will output the protection status of that block. The lock status is represented by ADQ0 and ADQ1. ADQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. ADQ0 is automatically set when entering Lock-Down. ADQ1 indicates the Lock-Down status and is set by the Lock-Down command. ADQ1 cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. 9.2 Locked state The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Locked-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. 9.3 Unlocked state Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powereddown. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. 52/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Block locking 9.4 Lock-Down state Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the Write Protect, WP, input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. When the Lock-Down function is disabled (WP=1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP=0 blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes that were made while WP=1. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state. 9.5 Locking operations during Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. 53/114 Block locking Table 18. Lock status M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Current Protection Status(1) (WP, ADQ1, ADQ0) Program/Erase Allowed yes no yes no yes no no Next Protection Status(1) (WP, ADQ1, ADQ0) After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 Current State 1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1 After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0(3) 1. The lock status is defined by the write protect pin and by ADQ1 (`1' for a locked-down block) and ADQ0 (`1' for a locked block) as read in the Read Electronic Signature command with ADQ1 = VIH and ADQ0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous ADQ0 value, giving a 111 or 110. 54/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Program and Erase times and endur- 10 Program and Erase times and endurance cycles The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 19 Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block are at `0' (pre-programmed). The worst case is when all the bits in the block are at `1' (not preprogrammed). Usually, the system overhead is negligible with respect to the erase time. In the M58LRxxxGU/L the maximum number of Program/Erase cycles depends on the VPP voltage supply used. Table 19. Program/Erase times and endurance cycles(1) (2) Parameter Condition Min Typ 0.4 1 1.2 30 30 90 90 440 880 20 20 100,000 100,000 0.4 1 85 10 340 320 640 640 10 10 680 2.5 4 170 25 25 Typical after Max 100kW/E Cycles 1 3 2.5 4 4 60 60 180 180 880 Unit s s s s s s s s ms s s cycles cycles s s s s s s ms ms s s 1000 cycles 2500 cycles Parameter Block (16 KWord) Erase Main Block (64 Preprogrammed KWord) Not Preprogrammed SIngle Cell VPP = VDD Program(3) Single Word Word Program Buffer Program Word Program Buffer Program Buffer (32 Words) (Buffer Program) Main Block (64 KWord) Suspend Latency Program/Erase Cycles (per Block) Erase Program Erase Main Blocks Parameter Blocks Parameter Block (16 KWord) Main Block (64 KWord) Word Program Single Word Buffer Enhanced Factory Program(4) Buffer Program Buffer Enhanced Factory Program VPP = VPPH Buffer (32 Words) Program(3) Buffer Program Main Block (64 Buffer Enhanced KWords) Factory Program Buffer Program Bank (16 Mbits) Buffer Enhanced Factory Program Program/Erase Cycles (per Block) Main Blocks Parameter Blocks 1. TA = -25 to 85C; VDD = 1.7V to 2V; VDDQ = 1.7V to 2V. 2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 3. Excludes the time needed to execute the command sequence. 4. This is an average value on the entire device. 55/114 Maximum rating M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 11 Maximum rating Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 20. Symbol TA TBIAS TSTG VIO VDD VDDQ VPP IO tVPPH Absolute maximum ratings Value Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPP at VPPH -25 -25 -65 -0.5 -0.2 -0.2 -0.2 Max 85 85 125 3.8 2.5 2.5 10 100 100 C C C V V V V mA hours Unit 56/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL DC and AC parameters 12 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 21: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 21. Operating and AC measurement conditions M58LR128GU/L Parameter Min VDD Supply Voltage VDDQ Supply Voltage VPP Supply Voltage (Factory environment) VPP Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 1.7 1.7 8.5 -0.4 -25 30 5 0 to VDDQ VDDQ/2 85 Max 2.0 2.0 9.5 VDDQ+0.4 85 Min 1.7 1.7 8.5 -0.4 -25 30 5 0 to VDDQ VDDQ/2 M58LR256GU/L 90 Max 2.0 2.0 9.5 VDDQ+0.4 85 V V V V C pF ns V V Units Figure 8. AC measurement I/O waveform VDDQ VDDQ/2 0V AI06161 57/114 DC and AC parameters Figure 9. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL AC measurement load circuit VDDQ VDDQ VDD 16.7k DEVICE UNDER TEST 0.1F 0.1F CL 16.7k CL includes JIG capacitance AI06162 Table 22. Symbol CIN COUT Capacitance(1) Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF 1. Sampled only, not 100% tested. 58/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 23. Symbol ILI ILO DC and AC parameters DC characteristics - currents Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=5MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 Word Supply Current Synchronous Read (f=66MHz) 8 Word 16 Word Continuous M58LR256GU/L 13 18 20 25 28 50 25 50 25 50 25 8 10 8 10 23 Typ Max 1 1 15 20 22 27 30 110 A M58LR128GU/L 70 110 A 70 110 A M58LR128GU/L 70 20 25 20 25 40 mA mA mA mA mA Unit A A mA mA mA mA mA IDD1 IDD2 Supply Current (Reset) RP = VSS 0.2V IDD3 Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) E = VDD 0.2V M58LR256GU/L K=VSS M58LR128GU/L M58LR256GU/L E = VIL, G = VIH IDD4 VPP = VPPH VPP = VDD IDD5(1) Supply Current (Erase) VPP = VPPH VPP = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (Continuous f=66MHz) in another Bank IDD6 (1), (2) Supply Current (Dual Operations) 38 50 25 2 0.2 2 0.2 0.2 0.2 55 110 mA IDD7(1) E = VDD 0.2V M58LR256GU/L Supply Current Program/ Erase Suspended (Standby) K=VSS M58LR128GU/L VPP Supply Current (Program) VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP VDD VPP VDD A 70 5 5 5 5 5 5 mA A mA A A A IPP1(1) VPP Supply Current (Erase) IPP2 IPP3(1) VPP Supply Current (Read) VPP Supply Current (Standby) 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents. 59/114 DC and AC parameters Table 24. Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL DC characteristics - voltages Parameter Test Condition Min 0 VDDQ -0.4 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.3 8.5 1.8 9.0 3.3 9.5 0.4 1 3.3 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Program Voltage-Logic VPP Program Voltage Factory Program or Erase Lockout VDD Lock Voltage RP pin Extended High Voltage 60/114 tAVQV ADQ0-ADQ15 VALID DATA VALID ADDRESS Hi-Z A16-Amax(2) VALID ADDRESS tAVAV tAVLH L tLLLH tLLQV tELLH E tELQV tEHQZ tEHQX G tGLQV tGLQX tELTV WAIT(1) Hi-Z tGHQX tGHQZ tEHTZ tLHGL tLHAX M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 10. Asynchronous Random Access Read AC waveforms VALID Valid Address Latch Outputs Enabled Data Valid Standby AI10092 DC and AC parameters Notes: 1- Write Enable, W, is High, WAIT is active Low. 2- Amax is equal to A23 in the M58LR256GU/L and to A22 in the M58LR128GU/L. 61/114 DC and AC parameters Table 25. Symbol tAVAV tAVQV tELTV tELQV(1) Read Timings tEHTZ tEHQX(2) tEHQZ(2) tGLQV(2) tGLQX(2) tGHQX(2) tGHQZ(2) tAVLH tELLH Latch Timings tLHAX tLLLH tLLQV tLHGL tOH tHZ tOE tOLZ tOH tDF tAVADVH tELADVH tADVHAX tCE M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Asynchronous Read AC characteristics M58LR128GU/L M58LR256GU/L Alt tRC tACC Parameter 85 Address Valid to Next Address Valid Address Valid to Output Valid (Random) Chip Enable Low to Wait Valid Chip Enable Low to Output Valid Chip Enable High to Wait Hi-Z Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Min Max Max Max Max Min Max Max Min Min Max Min Min Min Min Max Min 85 85 11 85 14 0 14 25 0 0 14 7 10 7 7 85 7 90 90 90 11 90 14 0 14 25 0 0 14 7 10 7 7 90 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tADVLADVH Latch Enable Pulse Width tADVLQV tADVHGL Latch Enable Low to Output Valid (Random) Latch Enable High to Output Enable Low 1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 2. Sampled only, not 100% tested. 62/114 ADQ0-ADQ15 VALID ADDRESS VALID VALID VALID NOT VALID VALID A16-Amax(4) VALID ADDRESS tAVLH tLLLH L tEHQX tKHQV Note 1 tKHAX tEHEL tKHQX tEHQZ tLLKH tAVKH K M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL tELKH E tGLQV tGLQX tGHQX tGHQZ Figure 11. Synchronous Burst Read AC waveforms G tKHTV tGLTV Note 2 X Latency Valid Data Flow Note 2 tKHTX Note 2 Boundary Crossing Standby tEHTZ tELTV Hi-Z WAIT Address Latch DC and AC parameters Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Amax is equal to A23 in the M58LR256GU/L and to A22 in the M58LR128GU/L. 63/114 AI10093 64/114 VALID NOT VALID NOT VALID NOT VALID NOT VALID NOT VALID tEHQX tKHQV Note 1 tKHAX tEHEL tEHQZ DC and AC parameters ADQ0-ADQ15 VALID ADDRESS A16-Amax(4) VALID ADDRESS tAVLH tLLLH L tLLKH tAVKH K(3) tELKH E tGLQX tGLQV tGHQX tGHQZ Figure 12. Single Synchronous Read AC waveforms G tGLTV tKHTV tGHTV tEHTZ tELTV Hi-Z WAIT(2) M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Amax is equal to A23 in the M58LR256GU/L and to A22 in the M58LR128GU/L. AI10094 ADQ0-ADQ15 VALID ADDRESS VALID VALID VALID VALID A16-Amax(5) VALID ADDRESS tAVLH tLLLH L tEHQX tKHQV Note 1 Note 3 tEHEL tEHQZ tLLKH tAVKH K(4) M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL tELKH tKHAX E tGLQX tGLQV tGHQZ tGLQV tGHQX tGHQZ G tGLTV tEHTZ Figure 13. Synchronous Burst Read Suspend AC waveforms tELTV Hi-Z WAIT(2) DC and AC parameters Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low 4. Address latched and data output on the rising clock edge. 5. Amax is equal to A23 in the M58LR256GU/L and to A22 in the M58LR128GU/L AI10095 65/114 DC and AC parameters M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 14. Clock input AC waveform tKHKL tKHKH tf tr tKLKH AI06981 Table 26. Symbol tAVKH tELKH tELTV Synchronous Read Timings tEHEL tEHTZ tGHTV tGLTV tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock Specifications tKHKH tKHKL tKLKH tf tr Synchronous Read AC characteristics Alt tAVCLKH tELCLKH Parameter Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Output Enable High to Wait Valid Output Enable Low to Wait Valid tCLKHAX tCLKHQV tCLKHQX Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Min Min Max Min Max Min Max Min Max Min Min Min Min M58LR128GU/L, M58LR256GU/L 5 6 11 14 14 11 11 7 11 3 5 15 3.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tADVLCLKH Latch Enable Low to Clock High tCLK Clock Period (f=66MHz) Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time Max 3 ns 1. Sampled only, not 100% tested. 2. For other timings please refer to Table 25: Asynchronous Read AC characteristics 66/114 PROGRAM OR ERASE tAVAV BANK ADD. tLHAX BANK ADDRESS VALID ADDRESS VALID ADDRESS tWHDX COMMAND VALID ADD. CMD OR DATA VALID ADD. STATUS REGISTER tAVAV ADQ0-ADQ15 A16-Amax(1) tAVLH tLLLH tDVWH L tELLH tWHLL tELLH tELQV tLHGL E tELWL tWHEH G tGHLL tWLWH tWHEL Figure 15. Write AC waveforms, Write Enable controlled M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL W tWHWL tWPHWH tWHWPL tQVWPL WP tWHVPL VPP tVPHWH tQVVPL K SET-UP COMMAND CONFIRM COMMAND STATUS REGISTER READ 1ST POLLING Ai11075 DC and AC parameters 67/114 Note1. Amax is equal to A23 in the M58LR256GU/L and to A22 in the M58LR128GU/L. DC and AC parameters Table 27. Symbol tAVAV tAVLH tDVWH tELLH Write Enable Controlled Timings tELWL tELQV tGHLL tLHAX tLHGL tLLLH tWHDX tWHEH tWHEL (2) M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Write AC characteristics, Write Enable controlled M58LR128GU/L Alt Parameter 85 tWC Address Valid to Next Address Valid Address Valid to Latch Enable High tDS Data Valid to Write Enable High Chip Enable Low to Latch Enable High tCS Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width tDH Write Enable High to Input Transition tCH Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Latch Enable Low tWP H M58LR256GU/L Unit 90 90 9 40 10 0 90 20 9 9 9 0 0 25 0 25 50 0 0 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 9 40 10 0 85 20 9 9 9 0 0 25 0 25 50 0 0 200 200 200 200 tWHLL tWHWL tWLWH tQVVPL Protection Timings tQVWPL Write Enable High to Write Enable Low tWP Write Enable Low to Write Enable High Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low tVPHWH tVPS VPP High to Write Enable High tWHVPL tWHWPL tWPHWH Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High 1. tWHEL has the values shown when reading in the targeted bank or when reading following a Set Configuration Register command.System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0ns. 2. Sampled only, not 100% tested. 68/114 PROGRAM OR ERASE tAVAV BANK ADD tLHAX BANK ADDRESS tAVLH tLLLH L tELLH E tELEH tWLEL G tGHLL W tEHWPL tWPHEH WP tEHVPL tVPHEH VPP tQVVPL tQVWPL tEHWH tWHEL tEHEL tELQV tEHLL tELLH tLHGL VALID ADDRESS VALID ADDRESS tDVEH tEHDX COMMAND VALID ADD CMD OR DATA VALID ADD STATUS REGISTER tAVAV ADQ0-ADQ15 Figure 16. Write AC waveforms, Chip Enable controlled M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL A16-Amax(1) K SET-UP COMMAND CONFIRM COMMAND STATUS REGISTER READ 1ST POLLING Ai11076 DC and AC parameters 69/114 Note1. Amax is equal to A23 in the M58LR256GU/L and to A22 in the M58LR128GU/L. DC and AC parameters Table 28. Symbol tAVAV tAVLH tDVEH tEHDX Chip Enable Controlled Timings tEHEL tEHLL tEHWH tELEH tELLH tELQV tGHLL tLHAX tLHGL tLLLH tWHEL(2) tWLEL tEHVPL Protection Timings tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH tCS tCH tWP tDS tDH M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Write AC characteristics, Chip Enable controlled M58LR128GU/L M58LR256GU/L Alt tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Latch Enable High Data Valid to Chip Enable High Chip Enable High to Input Transition Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 9 40 0 25 0 0 50 10 85 20 9 9 9 25 0 200 200 0 0 200 200 90 90 9 40 0 25 0 0 50 10 90 20 9 9 9 25 0 200 200 0 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tWPH Chip Enable High to Chip Enable Low Chip Enable High to Latch Enable Low Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width Write Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low tVPS VPP High to Chip Enable High Write Protect High to Chip Enable High 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank or when reading following a Set Configuration Register command.System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0ns. 70/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 17. Reset and Power-up AC waveforms DC and AC parameters W, E, G, L tPHWL tPHEL tPHGL tPHLL tPLWL tPLEL tPLGL tPLLL RP tVDHPH VDD, VDDQ Power-Up Reset AI06976 tPLPH Table 29. Symbol Reset and Power-up AC characteristics M58LR128GU/L Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low RP Pulse Width Supply Voltages High to Reset High Test Condition 85 90 25 25 90 s s ns During Program During Erase Other Conditions Min Min Min 25 25 85 M58LR256GU/L Unit tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH(1),(2) tVDHPH(3) Min 30 30 ns Min Min 50 100 50 100 ns s 1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset. 71/114 Package mechanical M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 13 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 18. VFBGA44 8 x 10mm - 10 x 4 ball array, 0.50mm pitch, bottom view package outline D D2 D1 FE FE1 SD E1 SE E2 E BALL "A1" FD1 FD e b ddd A A1 A2 BGA-Z54 1. Drawing is not to scale. 72/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 30. Package mechanical VFBGA44 8 x 10mm - 10 x 4 ball array, 0.50mm pitch, package mechanical data millimeters inches Max 1.000 0.150 0.660 0.300 8.000 4.500 6.500 0.080 10.000 1.500 3.500 0.500 1.750 0.750 4.250 3.250 0.250 0.250 - - 9.900 10.100 0.3937 0.0591 0.1378 0.0197 0.0689 0.0295 0.1673 0.1280 0.0098 0.0098 - - 0.3898 0.250 7.900 0.350 8.100 0.0260 0.0118 0.3150 0.1772 0.2559 0.0031 0.3976 0.0098 0.3110 0.0138 0.3189 0.0059 Typ Min Max 0.0394 Symbol Typ A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE Min 73/114 Package mechanical M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 19. VFBGA44 7.7 x 9mm - 10 x 4 ball array, 0.50mm pitch, bottom view package outline D D2 D1 FE FE1 SD E1 SE E2 E BALL "A1" FD1 FD e b ddd A A1 A2 BGA-Z47 1. Drawing is not to scale. 74/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 31. Package mechanical VFBGA44 7.7 x 9mm - 10 x 4 ball array, 0.50mm pitch, package mechanical data millimeters inches Max 1.00 0.15 0.66 0.32 7.70 4.50 6.50 0.08 9.00 1.50 3.50 0.50 1.60 0.60 3.75 2.75 0.25 0.25 - - - - - - 8.90 9.10 0.354 0.059 0.138 0.020 0.063 0.024 0.148 0.108 0.010 0.010 - - - - - - 0.350 0.27 7.60 0.37 7.80 0.026 0.013 0.303 0.177 0.256 0.003 0.358 0.011 0.299 0.015 0.307 0.006 Typ Min Max 0.039 Symbol Typ A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE Min 75/114 Package mechanical M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 20. VFBGA44 daisy chain - package connections (top view through package) AI08181 1 2 3 4 5 6 7 8 9 10 11 12 13 14 G C D 76/114 H A B E F M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Package mechanical Figure 21. VFBGA44 daisy chain - PCB connection proposal (top view through package) AI08182 13 14 4 5 6 7 8 9 10 11 1 2 G C D START POINT H A B E F 3 END POINT 12 77/114 Part numbering M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL 14 Part numbering Table 32. Example: Device Type M58 Architecture L = Multi-Level, Multiple Bank, Burst Mode Operating Voltage R = VDD = 1.7V to 2.0V, VDDQ = 1.7V to 2.0V Density 128 = 128 Mbit (x16) 256 = 256 Mbit (x16) Technology G = 0.13m technology Multi-Level Design Parameter Location U = Top Boot, Mux I/O L = Bottom Boot, Mux I/O Speed 85 = 85ns (M58LR128GU/L) 90 = 90ns (M58LR256GU/L) Package ZC = VFBGA44, 8 x 10mm, 0.50mm pitch (M58LR256GU/L only) ZB = VFBGA44, 7.7 x 9mm, 0.50mm pitch (M58LR128GU/L only) Temperature Range 5 = -25 to 85C Packing Option E = ECOPACK(R) Package, Standard Packing U = ECOPACK(R) Package, Tape & Reel Packing, 16mm Ordering information scheme M58LR256GU 90 ZC 5 E Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.), for daisy chain ordering information, or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 78/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Block address tables Appendix A Block address tables The following set of equations can be used to calculate a complete set of block addresses for the M58LRxxxGU/L using the information contained in Tables 33 to 44. To calculate the Block Base Address from the Block Number: First it is necessary to calculate the Bank Number and the Block Number Offset. This can be achieved using the following formulas: Bank_Number = (Block_Number -3) / Num_Blocks_In_a_Main_Bank Block_Number_Offset = Block_Number -3 -(Bank_Number x Num_Blocks_In_a_Main_Bank), where Num_Blocks_In_a_Main_Bank is equal to 8 for the M58LR256GU/L and to 16 for the M58LR128GU/L. If Bank_Number = 0, the Block Base Address can be directly read from Tables 33 and 36 for the M58LR256GU/L or Tables 39 and 42 for the M58LR128GU/L (Parameter Bank Block Addresses) in the Address Range column, in the row that corresponds to the given block number. Otherwise: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the Bank Number and the Block Number from the Block Base Address: If the address is in the range of the Parameter Bank, the Bank Number is 0 and the Block Number can be directly read from Tables 33 and 36 for the M58LR256GU/L or Tables 39 and 42 for the M58LR128GU/L (Parameter Bank Block Addresses), in the Block Number column, in the row that corresponds to the address given. Otherwise, the Block Number can be calculated using the formulas below: For the top configuration (M58LRxxxGU): Block_Number = ((NOT address) / 216) + 3 For the bottom configuration (M58LRxxxGL): Block_Number = (address / 216) + 3 For both configurations the Bank Number and the Block Number Offset can be calculated using the following formulas: Bank_Number = (Block_Number -3) / Num_Blocks_In_a_Main_Bank Block_Number_Offset = Block_Number - 3 -(Bank_Number x Num_Blocks_In_a_Main_Bank) where Num_Blocks_In_a_Main_Bank is equal to 8 for the M58LR256GU/L and to 16 for the M58LR128GU/L. 79/114 Block address tables Table 33. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL M58LR256GU - Parameter Bank block addresses Size (KWords) 16 16 16 16 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range FFC000-FFFFFF FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF FD0000-FDFFFF FC0000-FCFFFF FB0000-FBFFFF FA0000-FAFFFF F90000-F9FFFF F80000-F8FFFF F70000-F7FFFF F60000-F6FFFF F50000-F5FFFF F40000-F4FFFF F30000-F3FFFF F20000-F2FFFF F10000-F1FFFF F00000-F0FFFF Block Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 80/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 34. M58LR256GU - Main Bank base addresses Block Numbers 19-34 35-50 51-66 67-82 83-98 99-114 115-130 131-146 147-162 163-178 179-194 195-210 211-226 227-242 243-258 Block address tables Bank Number(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bank Base Address E00000 D00000 C00000 B00000 A00000 900000 800000 700000 600000 500000 400000 300000 200000 100000 000000 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 35. M58LR256GU - Block addresses in Main Banks Block Base Address Offset 0F0000 0E0000 0D0000 0C0000 0B0000 0A0000 090000 080000 070000 060000 050000 040000 030000 020000 010000 000000 Block Number Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 81/114 Block address tables Table 36. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL M58LR256GL - Parameter Bank block addresses Size (KWords) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 16 16 16 16 Address Range 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF Block Number 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 82/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 37. M58LR256GL - Main Bank base addresses Block Numbers 243-258 227-242 211-226 195-210 179-194 163-178 147-162 131-146 115-130 99-114 83-98 67-82 51-66 35-50 19-34 Block address tables Bank Number(1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bank Base Address F00000 E00000 D00000 C00000 B00000 A00000 900000 800000 700000 600000 500000 400000 300000 200000 100000 1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 38. M58LR256GL - Block addresses in Main Banks Block Base Address Offset 0F0000 0E0000 0D0000 0C0000 0B0000 0A0000 090000 080000 070000 060000 050000 040000 030000 020000 010000 000000 Block Number Offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 83/114 Block address tables Table 39. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL M58LR128GU - Parameter Bank block addresses Size (KWords) 16 16 16 16 64 64 64 64 64 64 64 Address Range 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF 780000-78FFFF Block Number 0 1 2 3 4 5 6 7 8 9 10 Table 40. M58LR128GU - Main Bank base addresses Block Numbers 11-18 19-26 27-34 35-42 43-50 51-58 59-66 67-74 75-82 83-90 91-98 99-106 107-114 115-122 123-130 Bank Base Address 700000 680000 600000 580000 500000 480000 400000 380000 300000 280000 200000 180000 100000 080000 000000 Bank Number(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). 84/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 41. M58LR128GU - Block addresses in Main Banks Block Number Offset 0 1 2 3 4 5 6 7 Block address tables Block Base Address Offset 070000 060000 050000 040000 030000 020000 010000 000000 Table 42. M58LR128GL - Parameter Bank block addresses Size (KWords) 64 64 64 64 64 64 64 16 16 16 16 Address Range 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF Block Number 10 9 8 7 6 5 4 3 2 1 0 85/114 Block address tables Table 43. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL M58LR128GL - Main Bank base addresses Block Numbers 123-130 115-122 107-114 99-106 91-98 83-90 75-82 67-74 59-66 51-58 43-50 35-42 27-34 19-26 11-18 Bank Base Address 780000 700000 680000 600000 580000 500000 480000 400000 380000 300000 280000 200000 180000 100000 080000 Bank Number(1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 44. M58LR128GL - Block addresses in Main Banks Block Number Offset 7 6 5 4 3 2 1 0 Block Base Address Offset 070000 060000 050000 040000 030000 020000 010000 000000 86/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Common Flash Interface Appendix B Common Flash Interface The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 45, 46, 47, 48, 49, 50, 51, 52, 53 and 54 show the addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (ADQ0-ADQ7), the other outputs (ADQ8-ADQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Offset 000h 010h 01Bh 027h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Security Code Area Query structure overview(1) Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP 080h 1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 46, 47, 48 and 49. Query data is always presented on the lowest order data outputs. 87/114 Common Flash Interface Table 46. Offset 000h M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL CFI query identification string Sub-section Name 0020h 882Ch 882Eh 882Dh 882Fh reserved DRC reserved 0051h 0052h 0059h 0001h 0000h offset = P = 000Ah 0001h 0000h 0000h value = A = 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 49) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table p = 10Ah Query Unique ASCII String "QRY" Manufacturer Code M58LR256GU M58LR128GU M58LR256GL M58LR128GL Description Value ST Top Top Bottom Bottom 001h Device Code 002h 003h 004h00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah Reserved Die Revision Code Reserved "Q" "R" "Y" NA NA 88/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 47. Offset Common Flash Interface CFI query system interface information Data Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for Buffer Program = 2 s Typical time-out per individual block erase = Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2 times typical Maximum time-out for Buffer Program = 2n times typical n n n Value 01Bh 0017h 1.7V 01Ch 0020h 2V 01Dh 0085h 8.5V 01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h 0095h 0008h 0009h 000Ah 0000h 0001h 0001h 0002h 0000h 9.5V 256s 512s 2n ms 1s NA 512s 1024s 4s NA Maximum time-out per individual block erase = 2 times typical Maximum time-out for chip erase = 2n times typical 89/114 Common Flash Interface Table 48. Offset 027h 0018h 028h 029h 02Ah 02Bh 02Ch 0001h 0000h 0006h 0000h 0002h 00FEh 0000h 007Eh 0000h 0000h 0002h 0003h 0000h 0080h 0000h M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Device geometry definition Data 0019h Description M58LR256GU/L Device Size = 2n in number of bytes M58LR128GU/L Device Size = 2 in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions M58LR256GU/L Erase Block Region 1 Information Number of identical-size erase blocks = 00FEh+1 M58LR128GU/L Erase Block Region 1 Information Number of identical-size erase blocks = 007Eh+1 Erase Block Region 1 Information Block size in Region 1 = 0200h * 256 Byte Erase Block Region 2 Information Number of identical-size erase blocks = 0003h+1 Erase Block Region 2 Information Block size in Region 2 = 0080h * 256 Byte n Value 32 MBytes 16 MBytes x16 Async. 64 Bytes 2 255 127 128 KByte 4 32 KByte NA 4 32 KBytes 255 127 128 KBytes NA 02Dh 02Eh TOP DEVICES 02Fh 030h 031h 032h 033h 034h 035h Reserved Reserved for future erase block region information 038h 02Dh 02Eh 02Fh 030h 0003h 0000h 0080h 0000h 00FEh 0000h 007Eh 0000h 0000h 0002h Erase Block Region 1 Information Number of identical-size erase block = 0003h+1 Erase Block Region 1 Information Block size in Region 1 = 0080h * 256 bytes M58LR256GU/L Erase Block Region 2 Information Number of identical-size erase block = 00FEh+1 M58LR128GU/L Erase Block Region 2 Information Number of identical-size erase block = 007Eh+1 Erase Block Region 2 Information Block size in Region 2 = 0200h * 256 bytes BOTTOM DEVICES 90/114 031h 032h 033h 034h 035h Reserved Reserved for future erase block region information 038h M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 49. Offset (P)h = 10Ah Common Flash Interface Primary algorithm-specific extended query table Data 0050h Primary Algorithm extended Query table unique ASCII string 0052h "PRI" 0049h Description Value "P" "R" "I" "1" "3" (P+3)h =10Dh (P+4)h = 10Eh (P+5)h = 10Fh 0031h Major version number, ASCII 0033h Minor version number, ASCII 00E6h Extended Query table contents for Primary Algorithm. Address 0003h (P+5)h contains less significant byte. 0000h bit 0 Chip Erase supported(1 = Yes, 0 = No) bit 1 Erase Suspend supported(1 = Yes, 0 = No) bit 2 Program Suspend supported(1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported(1 = Yes, 0 = No) bit 4 Queued Erase supported(1 = Yes, 0 = No) bit 5 Instant individual block locking supported(1 = Yes, 0 = No) bit 6 Protection bits supported(1 = Yes, 0 = No) bit 7 Page mode read supported(1 = Yes, 0 = No) bit 8 Synchronous read supported(1 = Yes, 0 = No) bit 9 Simultaneous operation supported(1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. Supported Functions after Suspend Read Array, Read Status Register and CFI Query (P+7)h = 111h (P+8)h = 112h 0000h No Yes Yes No No Yes Yes Yes Yes Yes (P+9)h = 113h 0001h bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' Yes (P+A)h = 114h 0003h Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' (P+B)h = 115h 0000h Yes Yes (P+C)h = 116h VDD Logic Supply Optimum Program/Erase voltage (highest performance) 0018h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 0090h VPP Supply Optimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 1.8V (P+D)h = 117h 9V 91/114 Common Flash Interface Table 50. Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h = 122h (P+19)h = 123h (P+1A)h = 124h (P+1B)h = 125h (P+1C)h = 126h M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Protection Register information Data 0002h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Value 2 80h 00h 8 Bytes 8 Bytes 89h Protection Register 2: Protection Description Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region 00h 00h 00h 0 0 0 16 0 16 0080h Protection Field 1: Protection Description 0000h Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address 0003h Bits 16-23 2n bytes in factory pre-programmed region 0003h Bits 24-31 2n bytes in user programmable region 0089h 0000h 0000h 0000h 0000h 0000h 0000h 0010h 0000h 0004h Table 51. Offset Burst Read information Data Description Value Page-mode read capability bits 0-7 n' such that 2n HEX value represents the number of (P+1D)h = 127h 0004h read-page bytes. See offset 0028h for device word width to determine page-mode data output width. (P+1E)h = 128h 0004h Number of synchronous mode read configuration fields that follow. 16 Bytes 4 (P+1F)h = 129h Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear 0001h bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. 4 (P+20)h = 12Ah 0002h Synchronous mode read capability configuration 2 (P-21)h = 12Bh 0003h Synchronous mode read capability configuration 3 (P+22)h = 12Ch 0007h Synchronous mode read capability configuration 4 8 16 Cont. 92/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 52. Bank and Erase block region information(1) Flash memory (bottom) Common Flash Interface Flash memory (top) Offset (P+23)h = 12Dh Data 02h Description Offset (P+23)h = 12Dh Data 02h Number of Bank Regions(2) within the device 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Tables 33 to 38 for the M58LR256GU/L and Tables 39 to 44 for the M58LR128GU/L. Table 53. Bank and Erase block region 1 information(1) (2) Flash memory (bottom) Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 01h Number of identical banks within Bank Region 1 00h Number of program or erase operations allowed in Bank Region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(3) Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Description Flash memory (top) Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 0Fh 00h (P+26)h = 130h 11h (P+26)h = 130h 11h (P+27)h = 131h 00h (P+27)h = 131h 00h (P+28)h = 132h 00h (P+28)h = 132h 00h (P+29)h = 133h 01h (P+29)h = 133h 02h 0Fh(4) (P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h 07h(5) 00h 00h 02h (P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h 03h 00h 80h 00h 93/114 Common Flash Interface Table 53. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Bank and Erase block region 1 information(1) (2) Flash memory (bottom) Offset (P+2E)h = 138h (P+2F)h = 139h Data 64h 00h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 1 Erase Block Type 2 Information Description Flash memory (top) Offset (P+2E)h = 138h (P+2F)h = 139h Data 64h 00h (P+30)h = 13Ah 02h (P+30)h = 13Ah 02h (P+31)h = 13Bh 03h (P+31)h = 13Bh 03h 0Eh(4) (P+32)h = 13Ch (P+33)h = 13Dh (P+34)h = 13Eh (P+35)h = 13Fh (P+36)h = 140h (P+37)h = 141h 06h(5) 00h 00h 02h 64h 00h Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+38)h = 142h 02h (P+39)h = 143h 03h 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. 3. Bank Regions. There are two Bank Regions, see Tables 33 to 38 for the M58LR256GU/L and Tables 39 to 44 for the M58LR128GU/L. 4. Applies to M58LR256G devices. 5. Applies to M58LR128G devices. 94/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 54. Bank and Erase block region 2 information(1) (2) Flash memory (bottom) Offset (P+3A)h = 144h (P+3B)h = 145h Data 0Fh 00h Common Flash Interface Flash memory (top) Offset (P+32)h = 13Ch (P+33)h = 13Dh Data 01h 00h Description Number of identical banks within Bank Region 2 Number of program or erase operations allowed in Bank Region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(3) Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved (P+34)h = 13Eh 11h (P+3C)h = 146h 11h (P+35)h = 13Fh 00h (P+3D)h = 147h 00h (P+36)h = 140h 00h (P+3E)h = 148h 00h (P+37)h = 141h 02h (P+3F)h = 149h 01h 0Eh(4) (P+38)h = 142h (P+39)h = 143h (P+3A)h = 144h (P+3B)h = 145h (P+3C)h = 146h (P+3D)h = 147h 06h(5) 00h 00h 02h 64h 00h (P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh 0Fh(4) 07h(5) 00h 00h 02h 64h 00h (P+3E)h = 148h 02h (P+46)h = 150h 02h 95/114 Common Flash Interface Table 54. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Bank and Erase block region 2 information(1) (2) (continued) Flash memory (bottom) Offset Data Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined in Table 51) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined in Table 51) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+43)h = 153h Feature Space definitions Reserved Description Flash memory (top) Offset Data (P+3F)h = 149h 03h (P+47)h = 151h 03h (P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh 03h 00h 80h 00h 64h 00h (P+46)h = 150h 02h (P+47)h = 151h 03h (P+48)h = 152h (P+49)h = 153h 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. 3. Bank Regions. There are two Bank Regions, see Tables 33 to 38 for the M58LR256GU/L and Tables 39 to 44 for the M58LR128GU/L. 4. Applies to M58LR256G devices. 5. Applies to M58LR128G devices. 96/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Flowcharts and pseudo codes Appendix C Flowcharts and pseudo codes Figure 22. Program flowchart and pseudo code Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h (3) writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; Write Address & Data Read Status Register (3) SR7 = 1 AI06170b 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 97/114 Flowcharts and pseudo codes M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 23. Buffer Program flowchart and pseudo code Start Buffer_Program_command (Start_Address, n, buffer_Program[] ) /* buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ { do {writeToFlash (Start_Address, 0xE8) ; Buffer Program E8h Command, Start Address Read Status Register status_register=readFlash (Start_Address); SR7 = 1 YES Write n(1), Start Address NO } while (status_register.SR7==0); writeToFlash (Start_Address, n); Write Buffer Data, Start Address writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/ X=0 x = 0; X=n NO YES while (x { writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data); x++; X=X+1 } Program Buffer to Flash Confirm D0h writeToFlash (Start_Address, 0xD0); Read Status Register do {status_register=readFlash (Start_Address); SR7 = 1 YES Full Status Register Check(3) NO } while (status_register.SR7==0); full_status_register_check(); } End AI08913b 1. n + 1 is the number of data being programmed. 2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to buffer_Program[].address 3. Routine for Error Check by reading SR3, SR4 and SR1. 98/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Flowcharts and pseudo codes Figure 24. Program Suspend & Resume flowchart and pseudo code Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ Write B0h Read Status Register SR7 = 1 YES SR2 = 1 NO } while (status_register.SR7== 0) ; NO Program Complete if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ; Write FFh YES Write FFh Read Data Read data from another address read_data ( ); /*read data from another address*/ Write D0h writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ Write 70h(1) } Program Continues with Bank in Read Status Register Mode } writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */ AI10117b 1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command. 99/114 Flowcharts and pseudo codes M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 25. Block Erase flowchart and pseudo code Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* Memory enters read status state after the Erase Command */ Write 20h (2) Write Block Address & D0h Read Status Register (2) do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/ SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; AI10976 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used. 100/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 26. Erase Suspend & Resume flowchart and pseudo code Start Flowcharts and pseudo codes Write B0h erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ Write 70h Read Status Register do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ SR7 = 1 YES SR6 = 1 NO } while (status_register.SR7== 0) ; NO Erase Complete if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ; Write FFh Read Data YES Write FFh Read data from another block or Program/Protection Register Program or Block Lock/Unlock/Lock-Down Write D0h else } read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ { writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another block*/ writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ writeToFlash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } Write 70h(1) Erase Continues with Bank in Read Status Register Mode AI10116b 1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command. 101/114 Flowcharts and pseudo codes M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 27. Locking operations flowchart and pseudo code Start Write 60h (1) locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */ Write 01h, D0h or 2Fh Write 90h (1) Read Block Lock States Locking change confirmed? YES Write FFh (1) NO if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/ writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ } End AI06176b 1. Any address within the bank can equally be used. 102/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Flowcharts and pseudo codes Figure 28. Protection Register Program Flowchart and Pseudo Code Start Write C0h (3) protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; Write Address & Data Read Status Register (3) SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; } AI06177b 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 103/114 Flowcharts and pseudo codes M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Figure 29. Buffer Enhanced Factory Program Flowchart and Pseudo Code Start Write 80h to Address WA1 SETUP PHASE Buffer_Enhanced_Factory_Program_Command (start_address, DataFlow[]) { writeToFlash (start_address, 0x80) ; Write D0h to Address WA1 writeToFlash (start_address, 0xD0) ; do { do { status_register = readFlash (start_address); Read Status Register NO SR7 = 0 YES NO SR4 = 1 Initialize count X=0 Write PDX Address WA1 if (status_register.SR4==1) { /*error*/ if (status_register.SR3==1) error_handler ( ) ;/*VPP error */ if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */ PROGRAM AND } VERIFY PHASE while (status_register.SR7==1) x=0; /* initialize count */ do { writeToFlash (start_address, DataFlow[x]); Read Status Register SR3 and SR1for errors Exit Increment Count X=X+1 x++; NO X = 32 YES Read Status Register }while (x<32) do { status_register = readFlash (start_address); NO SR0 = 0 YES }while (status_register.SR0==1) NO Last data? YES Write FFFFh to Address = NOT WA1 } while (not last data) writeToFlash (another_block_address, FFFFh) EXIT PHASE Read Status Register do { status_register = readFlash (start_address) NO SR7 = 1 }while (status_register.SR7==0) YES Full Status Register Check End full_status_register_check(); } AI07302a 104/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface state tables Appendix D Table 55. Command interface state tables Command interface states - modify table, next state(1) Command Input Block Buffer Read Program Program Erase, (3)(4) Setup(3)( Array(2)( Setup (3)(4) 4) FFh) (10/40h) (E8h) (20h) Buffer Program Program Setup Setup Clear Erase Confirm Read Buffer Status P/E Resume, Block Status Program, Register Unlock confirm, Register (5) BEFP Confirm(3)(4) Program/Erase Suspend (B0h) (70h) (D0h) (50h) Read Electronic Signature, Read CFI Query (90h, 98h) Current CI State BEFP Setup (80h) Ready Ready Erase Setup BEFP Setup Ready (unlock block) Ready Lock/CR Setup Setup OTP Busy Setup Program Busy Suspend Setup Buffer Load 1 Buffer Load 2 Confirm Busy Suspend Setup Busy Erase Erase Suspend Suspend Ready (Lock Error) Ready (Lock Error) OTP Busy Program Busy Program Busy Program Suspend Program Busy Buffer Program Load 1 (give word count load (N-1)); if N=0 go to Buffer Program Confirm. Else (N not =0) go to Buffer Program Load 2 (data load) Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) Buffer Program Busy Buffer Program Suspend Ready (error) Erase Busy Buffer Program Program in Erase Setup in Suspend Erase Suspend Buffer Program Busy Erase Busy Erase Suspend Buffer Program Busy Buffer Program Suspend Ready (error) Buffer Program Busy Program Suspend Program Busy Program Suspend Buffer Program Buffer Program Suspend Ready (error) Erase Busy Erase Suspend Erase Busy Erase Suspend Setup Program in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend Program Busy in Erase Suspend Busy Program Busy in Erase Suspend Program Busy in Erase Suspend Suspend Program Suspend in Erase Suspend Program Suspend in Erase Suspend 105/114 Command interface state tables Table 55. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface states - modify table, next state(1) (continued) Command Input Block Buffer Read Program Program Erase, (3)(4) Setup(3)( Array(2)( Setup (3)(4) 4) FFh) (10/40h) (E8h) (20h) Clear Erase Confirm Read Buffer Status P/E Resume, Block Status Program, Register Unlock confirm, Register (5) BEFP Confirm(3)(4) Program/Erase Suspend (B0h) (70h) (D0h) (50h) Read Electronic Signature, Read CFI Query (90h, 98h) Current CI State BEFP Setup (80h) Setup Buffer Load 1 Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N not =0) go to Buffer Program Load 2 Buffer Program Load 2 in Erase Suspend (data load) Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) Buffer Program Busy in Erase Suspend Buffer Program Suspend in Erase Suspend Ready (error) Buffer Load 2 Buffer Program Confirm in Erase Suspend Busy Buffer Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Suspend Buffer Program Suspend in Erase Suspend Erase Suspend (Lock Error) Ready (error) Buffer Program Busy in Erase Suspend Erase Suspend BEFP Busy BEFP Busy(6) Buffer Program Suspend in Erase Suspend Erase Suspend (Lock Error) Ready (error) Lock/CR Setup in Erase Suspend Setup Busy Buffer EFP 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. BEFP is allowed only when Status Register bit SR0 is set to `0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. 106/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 56. Command interface state tables Command interface states - modify table, next output state(1) (2) Command Input Erase Confirm, P/E Block Clear Read Program Program/ Read BEFP Resume, Block Erase, Status Status Array Setup(4) Buffer Erase Unlock confirm, Program Setup(4)(5) Setup (5) (3) (4)(5) Suspend Register Register (E8h) (80h) BEFP Confirm (B0h) (70h) (50h) (FFh) (10/40h) (20h) (D0h) Read Electronic signature, Read CFI Query (90h, 98h) Current CI State Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Status Register Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Lock/CR Setup Lock/CR Setup in Erase Suspend 107/114 Command interface state tables Table 56. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface states - modify table, next output state(1) (2) (continued) Command Input Erase Confirm, P/E Block Clear Read Program Program/ Read BEFP Resume, Block Erase, Status Status Array Setup(4) Buffer Erase Unlock confirm, Program Setup(4)(5) Setup (5) (3) (4)(5) Suspend Register Register (E8h) (80h) BEFP Confirm (B0h) (70h) (50h) (FFh) (10/40h) (20h) (D0h) Read Electronic signature, Read CFI Query (90h, 98h) Status Register Current CI State OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Array Status Register Output Unchanged Status Output Register Unchanged Electronic Signature/CFI 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 4. The two cycle command should be issued to the same bank address. 5. If the P/E.C. is active, both cycles are ignored. 108/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 57. Command interface states - lock table, next state(1) Command Input Current CI State Lock/CR Setup(2) (60h) Lock/CR Setup OTP Setup(2) (C0h) OTP Setup Ready Block LockBlock Lock Down Confirm Confirm (01h) (2Fh) Set CR Confirm (03h) Ready Command interface state tables Block Address (WA0)(3) (XXXXh) Illegal Command (4) WSM Operation Completed N/A Ready Lock/CR Setup Setup OTP Busy Setup Program Busy Suspend Setup Buffer Load 1 Buffer Load 2 Confirm Busy Suspend Setup Busy Ready (Lock error) Ready (Lock error) N/A N/A OTP Busy Ready Program Busy Program Busy Program Suspend Buffer Program Load 1 (give word count load (N-1)); Buffer Program Load 2(5) Exit see note(5) N/A Ready N/A N/A N/A Buffer Program Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) Buffer Program Busy Buffer Program Suspend Ready (error) Erase Busy Lock/CR Setup in Erase Suspend N/A N/A Ready N/A N/A Ready Erase Suspend Erase Suspend N/A Setup Program in Erase Suspend Busy Suspend Setup Buffer Load 1 Buffer Program in Erase Suspend Buffer Load 2 Confirm Busy Suspend Lock/CR Setup in Erase Suspend Erase Suspend (Lock error) Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)) Buffer Program Load 2 in Erase Suspend(6) Exit see note(6) N/A Erase Suspend Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) Buffer Program Busy in Erase Suspend Buffer Program Suspend in Erase Suspend Erase Suspend Erase Suspend (Lock error) N/A N/A 109/114 Command interface state tables Table 57. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface states - lock table, next state(1) (continued) Command Input Current CI State Lock/CR Setup(2) (60h) OTP Setup(2) (C0h) Block LockBlock Lock Down Confirm Confirm (01h) (2Fh) Ready (error) BEFP Busy (7) Set CR Confirm (03h) Block Address (WA0)(3) (XXXXh) Illegal Command (4) WSM Operation Completed N/A Setup BEFP Busy Exit BEFP Busy(7) N/A 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller, WA0 = Address in a block different from first BEFP address. 2. If the P/E.C. is active, both cycles are ignored. 3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 4. Illegal commands are those not defined in the command set. 5. if N=0 go to Buffer Program Confirm. Else (N 0) go to Buffer Program Load 2 (data load). 6. if N=0 go to Buffer Program Confirm in Erase Suspend. Else (N 0) go to Buffer Program Load 2 in Erase Suspend. 7. BEFP is allowed only when Status Register bit SR0 is set to `0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. 110/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Table 58. Command interface state tables Command interface states - lock table, next output state(1) (2) Command Input Current CI State Lock/CR Setup(3) (60h) OTP Setup(3) (C0h) Block Lock Confirm (01h) Block LockDown Confirm (2Fh) Set CR Confirm (03h) BEFP Exit(4) (FFFFh) Illegal Command(5) WSM Operation Completed Program Setup Erase Setup OTP Setup Program in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Status Register Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Lock/CR Setup Lock/CR Setup in Erase Suspend Status Register Array Status Register Output Unchanged 111/114 Command interface state tables Table 58. M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Command interface states - lock table, next output state(1) (2) (continued) Command Input Current CI State Lock/CR Setup(3) (60h) OTP Setup(3) (C0h) Block Lock Confirm (01h) Block LockDown Confirm (2Fh) Set CR Confirm (03h) BEFP Exit(4) (FFFFh) Illegal Command(5) WSM Operation Completed OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Status Register Output Unchanged Array Output Unchanged Output Unchanged 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller, WA0 = Address in a block different from first BEFP address. 3. If the P/E.C. is active, both cycles are ignored. 4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 5. Illegal commands are those not defined in the command set. 112/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Revision history Revision history Table 59. Date 05-Jun-2006 Document revision history Version 1 Initial release. Changes 113/114 M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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(c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 114/114 |
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