View MB90050_333236.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS04-28829-1E
ASSP For Screen Display Control
CMOS
On-Screen Display Controller
MB90050
s DESCRIPTION
The MB90050 is an on-screen display controller for displaying text and graphics on the TV screen. The MB90050 controls a display area of 35 characters by 16 lines, and provides each character composed of 24 x 32 dots at most. The display functions include a wealth of characters with qualifying functions such as character background shading (shadow casting) , sprite character functions and graphic character functions, contributing to the use of control GUI displays. The MB90050 incorporates display memory (VRAM) , character font ROM, and sync signal generation circuit and video signal generation circuit supporting the NTSC and PAL systems, allowing text and graphics to be displayed in conjunction with a small number of external components.
s FEATURES
* Main screen display capacity 35 characters x 16 lines (maximum 560 characters) * Character configuration Normal characters : 24 x 32 dots Graphic characters : 12 x 16 dots* (colorable per 1 dot)
(Continued)
s PACKAGE
48-pin plastic QFP
(FPT-48P-M15)
MB90050
* Font display configuration Three horizontal width settings (selectable setting L/M/S for each character) per character. L size : 24 dots M size : 18 dots S size : 12 dots Two vertical height settings (selectable A/B for each line) per line. A : 18 to 32 dots (setting per 2 dots) B : 18 to 32 dots (setting per 2 dots) (These sizes are dot sizes of typical character. Each size of graphic characters uses half the number of dots of typical characters. Note, however, that both of the typical and graphic characters are the same in character area size. * Character types Usable all 512 character types (font ROM+, font RAM) Font ROM : 512 character types (all area user setting) Font RAM : 8 character types (all area user command setting) Capable of setting a specific eight-character area in font ROM so that the area is replaced with font RAM. * Display modes Character : Normal character/graphic character (set for each character) Character trimming : Side trimming 1/side trimming 2/patern background 1/patern background 2 (set for each screen) Character background : None/Solid-fill/Shaded background (concave) /Shaded background (convex) (set for each character) Line background : None/Solid-fill/Shaded background (concave) /Shaded background (convex) (set for each line) Character enlargement : Normal, Double width, Double height, Double width x double height (set for each line) Brink : OFF/ON (set for each character) * Main screen display position control Horizontal display position : Control in 2-dot units (movable through the entire screen) Vertical display position : Control in 2-dot units (movable through the entire screen) Line spacing control : 0 to 14 dots, 2-dot units (set for each line) Sprite character display control Capable of displaying one block for an arbitrary character on the topmost layer on the screen. Sprite character display : OFF/ON (graphic character display) Sprite character types : 256 types (character codes 000H to 0FFH) Sprite character configuration : 1 character/2 characters horizontal/2 characters vertical/ 2x2 characters Sprite character horizontal display position : Control in 1-dot units Sprite character vertical display position : Control in 1-dot units Screen background color display control Capable of displaying an arbitrary color on the entire bottommost layer on the screen. Screen background color display : OFF/ON * Display colors Digital output : 16 colors selectable from among 64 colors (built in palette circuit) Video output : Any 16 colors selectable (Command setting enable) (Continued)
2
MB90050
(Continued) * Display colors and setting units Character color : 16 colors (set for each character) Character background color : 16 colors (set for each character) Character trimming color : 16 colors (set for each line) Line background color : 16 colors (set for each line) Graphic character color : 16 colors (set for each dot) Sprite character color : 16 colors (set for each dot) Screen background character color : 16 colors (set for each dot) Screen background color : 16 colors (set for all screen) Shaded background frame highlight color : 16 colors (set for all screen) Shaded background frame shadow color : 16 colors (set for all screen) * Digital display signal output Color signal output : DCOL5 to DCOL0 pins (6 bits) Display period signal output : VOB1 pin Translucent display period signal output : VOB2 pin * Analog (video) signal input/output Composit video input/output : VIN, VOUT pins Y/C video input/output : YIN, YOUT pins, CIN, COUT pins * Internal sync control Internal sync signal generator and video signal generator supporting the NTSC and PAL systems. * External interface 16-bit serial input (3-signal input) Chip select signal Serial clock signal Serial data signal * Package QFP-48 (FPT-48P-M15) * Supply voltage +5 V10%
* : 1 dot of graphic characters is the same size as 2 x 2 dots of normal characters.
3
MB90050
s PIN ASSIGNMENT
(TOP VIEW)
TESTI2 TESTI1 37 AVCC2 AVCC1 39
AVSS2
AVSS1
COUT
VOUT
YOUT
CIN
YIN
48
47
46
45
44
43
42
41
40
38
VIN
FLDI VSYNCI HSYNCI VCC VSS EXS XS FSC4O VSYNCO HSYNCO CSYNCO VBLKO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33
PO3 PO2 DCOL5 DCOL4 DCOL3 DCOL2 DCOL1 DCOL0 DCLKO DB DH RESET
MB90050
32 31 30 29 28 27 26 25
FLDO
SYNCST
CS
SCLK
SIN
BUSY
XD
EXD
VSS
VCC
PO0
(FPT-48P-M15)
4
PO1
MB90050
s PIN DESCRIPTIONS
Pin no. 6 7 20 19 15 16 17 Pin name I/O EXS XS EXD XD CS SCLK SIN Circuit type A Function Crystal oscillation circuit pins for color burst clock generator. Connect an external crystal oscillator (14.31818 MHz for NTSC or 17.734475 MHz for PAL) and load capacitance (C) to these pins to form a crystal oscillation circuit. LC oscillation circuit pins for display dot clock generator. Connect these pins to external "L" and "C" to from an LC oscillation circuit. Chip select signal input pin. For serial command transfer, set this pin to the Low level. Serial clock signal input pin. This pin feeds a clock signal upon transfer of a serial command. It feeds serial data at the rising edge. Serial data signal input pin. Input data during serial command transfer. Busy signal output pin. This pin outputs a significant level signal during VRAM filling. Do not input a serial command while the pin outputs the significant level signal. Supplying a low level signal to the CS pin during the significant level signal output period terminates the VRAM fill operation and causes this pin to output an insignificant level signal. The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting. The pin can also serve as the ACK signal output pin using the command setting for output selection control (BUS = 1). In this case, the pin outputs the significant level signal upon completion of VRAM filling. When the RESET pin inputs a low level signal, this pin outputs the busy signal, turns off the internal pull-up resistor, and sets the output to OFF (output tied to the low). Vertical sync signal input pin. (The input signal to this pin is disabled when the composite sync signal input is selected by the command setting.) Active low signal or active high signal input is command-selectable for the pin. When the RESET pin inputs the low level signal, this pin inputs the active low signal. Horizontal sync signal input pin. (This pin can also serve as a composite sync signal input pin with the command setting.) Active low signal or active high signal input is command-selectable for the pin. When the RESET pin inputs the low level signal, this pin inputs the active low, horizontal sync signal. Field signal input pin. The internal field signal identically detected from among input sync signals or the input signal to this pin is command-selectable for field control. During operation under external synchronization control, the input signal is used to control the least significant bit of the font ROM/RAM raster address. The input signal to this pin is disabled during operation under internal synchronization control.
I/O
I/O I I I
B C C C
18
BUSY
O
F
2
VSYNCI
I
D
3
HSYNCI
I
D
1
FLDI
I
D
(Continued)
5
MB90050
Pin no.
Pin name
I/O
Circuit type
Function Vertical sync signal output pin. The pin enables output (ON/OFF) control, output logic control, and internal pull-up ON/OFF control depending on the command setting. When the RESET pin inputs the low level signal, this pin turns off the internal pull-up resistor and sets the output to OFF (output tied to the high). Horizontal sync signal output pin. The pin enables output (ON/OFF) control, output logic control, and internal pull-up ON/OFF control depending on the command setting. When the RESET pin inputs the low level signal, this pin turns off the internal pull-up resistor and sets the output to OFF (output tied to the high). Composite sync signal output pin. The pin enables output (ON/OFF) control, output logic control, and internal pull-up ON/OFF control depending on the command setting. When the RESET pin inputs the low level signal, this pin turns off the internal pull-up resistor and sets the output to OFF (output tied to the high). Vertical blanking interval (VBI) output pin. The pin enables output (ON/OFF) control, output logic control, and internal pull-up ON/OFF control depending on the command setting. When the RESET pin inputs the low level signal, this pin turns off the internal pull-up resistor and sets the output to OFF (output tied to the low). Field signal output pin. During operation under internal synchronization control, this pin outputs the internally generated field signal. During operation under external synchronization control, the pin outputs the field signal (internally detected field signal or external input field signal) used for internal operations. The pin enables output (ON/OFF) control, output logic control, and internal pull-up ON/OFF control depending on the command setting. When the RESET pin inputs the low level signal, this pin turns off the internal pull-up resistor and sets the output to OFF (output tied to the low). Synchronization detection signal output pin. This pin outputs a significant level signal with a sync signal detected and an insignificant level signal with no sync signal detected. The pin enables output (ON/OFF) control, output logic control, and internal pull-up ON/OFF control depending on the command setting. When the RESET pin inputs the low level signal, this pin turns off the internal pull-up resistor and sets the output to OFF (output tied to the low).
9
VSYNCO
O
F
10
HSYNCO
O
F
11
CSYNCO
O
F
12
VBLKO
O
F
13
FLDO
O
F
14
SYNCST
O
F
(Continued)
6
MB90050
Pin no.
Pin name
I/O
Circuit type
Function Dot clock signal output pin. This pin outputs an LC oscillation clock signal. The pin enables output (ON/OFF) control depending on the command setting. The normal clock (that stops oscillation during horizontal synchronization) or continuous clock (that does not stop oscillation during horizontal synchronization) can be command-selected for the output using the command setting for output selection control (CKS). When the TESTI2 pin inputs a low level signal, this pin outputs the continuous clock signal that does not stop oscillation during horizontal synchronization (where the output selection control (CKS) setting is disabled). When the RESET pin inputs the low level signal, the pin outputs a dot clock signal. Crystal oscillator 4FSC clock signal output pin. This pin enables output (ON/OFF) control depending on the command setting. The crystal oscillation clock (4FSC) or its 1/4 frequency clock (FSC) can be command-selected for the output using the command setting for output selection control (FSS). When the TESTI2 pin inputs the low level signal, this pin outputs the 4FSC clock signal (where the output selection control (FSS) setting is disabled). When the RESET pin inputs the low level signal, this pin outputs the 4FSC clock signal. Halftone display period signal output pin. This pin enables output (ON/OFF) control and output logic control depending on the command setting. When the RESET pin inputs the low level signal, this pin sets the output to OFF (output tied to the low). (The input feature of the pin is a test function. Use the pin usually only for output.) Display period signal output pin. This pin enables output (ON/OFF) control and output logic control depending on the command setting. When the RESET pin inputs the low level signal, this pin sets the output to OFF (entering the low level signal fixed output state). (The input feature of the pin is a test function. Use the pin usually only for output.) Display color signal output pin. This pin enables output (ON/OFF) control and output logic control depending on the command setting. When the RESET pin inputs the low level signal, this pin sets the output to OFF (entering the low level signal fixed output state). (The input feature of the pin is a test function. Use the pin usually only for output.) Port signal output pin. This pin enables output level (High/Low) control depending on the command setting. When the RESET pin inputs the low level signal, this pin sets the output to OFF (entering the low level signal fixed output state). (The input feature of the pin is a test function. Use the pin usually only for output.)
28
DCLKO
O
G
8
FSC4O
O
G
26
DH
I/O
H
27
DB
I/O
H
34 33 32 31 30 29 36 35 24 23
DCOL5 DCOL4 DCOL3 DCOL2 DCOL1 DCOL0 PO3 PO2 PO1 PO0
I/O
H
I/O
H
(Continued)
7
MB90050
(Continued)
Pin no. Pin name I/O Circuit type Function Reset signal input pin. Upon input of the low level signal, this pin causes an internal reset. After the power supply is inserted, the reset input is required for normal operation. During regular operation, the pin inputs the high level signal. Test signal input pin. Input High level signal during normal operation. (Input of the Low level signal activates test mode operation.) Test signal input pin. Input High level signal during normal operation. Composite video signal input pin. This pin inputs a DC-reproduced signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V) . Luminance video signal (Y video signal) input pin. This pin inputs a DC-reproduced signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V) . Saturation video signal (C video signal) input pin. This pin inputs a signal at 1.57 VDC and a color burst signal amplitude of 0.57 VP-P. Composite video signal output pin. This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V) . When the RESET signal inputs the low level signal, this pin outputs the black video (pedestal level without color burst) signal. Luminance video signal (Y video signal) output pin. This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V) . When the RESET pin inputs the low level signal, this pin outputs the black video (pedestal level) signal. Saturation video signal (C video signal) output pin. This pin outputs a signal at 1.57 VDC and a color burst signal amplitude of 0.57 VP-P. When the RESET pin inputs the low level signal, this pin outputs the black video signal (a DC voltage of 1.57 V without color burst). Power supply pin for digital circuit. These pins supply +5 V and make all VCC pins same potential. Digital ground pins. These pins make all VSS pins and AVSS1/AVSS2 pins same potential. Power supply pin for analog circuit and composite video signal Input/Output (VIN-VOUT) circuit. This pin supplies +5 V. Input analog ground level when not using this analog circuit. Power supply pin for analog circuit, luminance video signal Input/Output (YIN-YOUT) circuit, and saturation video signal Input/Output (CIN-COUT) circuit. This pin supplies +5 V. Input analog ground level when not using this analog circuit. Analog ground pins. These pins make AVSS1/AVSS2 pins and VSS pins same potential.
25
RESET
I
C
37 47 38
TESTI1 TESTI2 VIN
I I I
E E I
46
YIN
I
I
44
CIN
I
I
40
VOUT
O
I
48
YOUT
O
I
42
COUT
O
I
4 22 5 21 39
VCC VSS

AVCC1
43
AVCC2
41 45
AVSS1 AVSS2
8
MB90050
Note : A : Crystal oscillation B : LC oscillation C : TTL level, Hysteresis input D : CMOS level, Hysteresis input E : CMOS level, Hysteresis input, with pull-up resistor (approx. 50 k) F : Open-drain output, with pull-up resistor SW (approx. 50 k) G : CMOS output H : CMOS I/O (Input is for test.) I : Analog I/O
9
MB90050
s I/O CIRCUIT TYPES
Type Circuit Remarks * Crystal oscillation Oscillator feedback resistor (approx. 1M)
EXS
A
XS
TEST signal * LC oscillation
EXD
B
XD
STOP signal * TTL hysteresis input
C
TTL
* CMOS hysteresis input
D
CMOS
5V
* CMOS hysteresis input with pull-up resistor (approx. 50 k)
E
CMOS
(Continued)
10
MB90050
(Continued)
Type Circuit Remarks * Nch open-drain output with pull-up resistor SW (approx. 50 k) Pull UP control signal
5V Pch
F
Nch
* CMOS output
5V Pch
G
Nch
5V Pch
* CMOS I/O Input is for test.
H
Nch
TEST signal
Input (TEST) * Analog I/O CMOS analog SW
I
Control signal
11
MB90050
s BLOCK DIAGRAM
SIN SCLK CS VIN YIN CIN HSYNCI VSYNCI FLDI SYNCST VOUT YOUT COUT
Serial input control
Each block
Analog switch
Sync control
Video signal generator circuit
HSYNCO DCOL5 to DCOL0 VSYNCO CSYNCO FLDO VBLKO
NTSC/PAL signal generator circuit
Output control Pallete (4 bits6 bits)
DB DH
BUSY
Display Memmory control
VRAM (35 characters x 16 lines)
EXS XS FSC4O
Font ROM (512 characters)
Font RAM (8 characters)
4FSC clock oscillation circuit
PO3
Each block
Port control
PO2 PO1 PO0
EXD XD DCLKO RESET
Dot clock oscillation circuit
Each block
All reset
12
MB90050
s ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Power supply voltage Input voltage Output voltage Power consumption Operating temperature Storage temperature Symbol VDD VIN VOUT Pd Ta Tstg Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 -40 -55 Max VSS + 7.0 VDD + 0.5 VDD + 0.5 500 +85 +125 Unit V V V mW C C Remarks
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(VSS = 0 V) Parameter Power supply voltage "H" level input voltage Symbol VDD VIH1 VIH1S VIH2S VIL1 "L" level input voltage Analog input voltage Operating temperature VIL1S VIL2S AVIN Ta Value Min 4.5 0.7 x VDD 0.8 x VDD 0.6 x VDD VSS-0.3 VSS-0.3 VSS-0.3 0 -40 Max 5.5 VDD + 0.3 VDD + 0.3 VDD + 0.3 0.3 x VDD 0.2 0.6 VDD +85 Unit V V V V V V V V C G D, E C G D, E C Remarks (circuit type)
Notes : * Do not make a potential difference between AVSS (AVSS1/2) and VSS. * It is possible to set AVCC1 = AVSS when not using composite video signal (VIN-VOUT pins) . * It is possible to set AVCC2 = AVSS when not using Y/C separated video signals (YIN-YOUT and CIN-COUT pins) . WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
13
MB90050
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Symbol VOH VOL RP IDD (Ta = -40 C to +85 C, VSS = 0 V) Pin name All output pins All output pins E, F VCC Conditions VCC = 4.5 V, IOH = -4.0 mA VCC = 4.5 V, IOL = 4.0 mA VCC = 5.5V VCC = 5.5 V, 4FSC = 20 MHz, DCLK = 20 MHz VCC = AVCC1 = AVCC2 = 5.5 V, 4FSC = 0 MHz, VIN, YIN, CIN = 1.65V, No load Value Min 4.0 25 Typ 50 35 Max 0.4 200 45 Unit V V k mA
Parameter "H" level output voltage "L" level output voltage Pull-up resistor Power supply current
Analog power supply current
IA
AVCC1, AVCC2
22
40
mA
ON resistor
RON
VIN-VOUT, VCC = AVCC1 = AVCC2 = 4.5 V, YIN-YOUT, IOL = 100 A CIN-COUT VIN, YIN, CIN VOUT, YOUT, COUT VCC = AVCC1 = AVCC2 = 5.5 V, VIN, YIN, CIN = 5.5V VCC = AVCC1 = AVCC2 = 4.5 V, IOL = 100 A
215
310
OFF leak current
IOFF
0.1
10
A
Output resistor
ROUT
100
1800
14
MB90050
Analog Ladder Voltage Symbol VOHR0 VOHR1 VOHR2 VOHR3 VOHR4 VOHR5 VOHR6 VOHR7 VOHR8 VOHR9 VOHR10 VOHR11 VOHR12 VOHR13 VOHR14 VOHR15 VOHR16 VOHR17 VOHR18 VOHR19 VOHR20 VOHR21 VOHR22 VOHR23 VOHR24 VOHR25 VOHR26 VOHR27 VOHR28 VOHR29 VOHR30 VOHR31 VOHR32 VOHR33 VOHR34 VOHR35 Parameter Resistance ladder voltage 00 (-40 IRE) Resistance ladder voltage 01 (-36 IRE) Resistance ladder voltage 02 (-32 IRE) Resistance ladder voltage 03 (-28 IRE) Resistance ladder voltage 04 (-24 IRE) Resistance ladder voltage 05 (-20 IRE) Resistance ladder voltage 06 (-16 IRE) Resistance ladder voltage 07 (-12 IRE) Resistance ladder voltage 08 (-8 IRE) Resistance ladder voltage 09 (-4 IRE) Resistance ladder voltage 10 (0 IRE) Resistance ladder voltage 11 (4 IRE) Resistance ladder voltage 12 (8 IRE) Resistance ladder voltage 13 (12 IRE) Resistance ladder voltage 14 (16 IRE) Resistance ladder voltage 15 (20 IRE) Resistance ladder voltage 16 (24 IRE) Resistance ladder voltage 17 (28 IRE) Resistance ladder voltage 18 (32 IRE) Resistance ladder voltage 19 (36 IRE) Resistance ladder voltage 20 (40 IRE) Resistance ladder voltage 21 (44 IRE) Resistance ladder voltage 22 (48 IRE) Resistance ladder voltage 23 (52 IRE) Resistance ladder voltage 24 (56 IRE) Resistance ladder voltage 25 (60 IRE) Resistance ladder voltage 26 (64 IRE) Resistance ladder voltage 27 (68 IRE) Resistance ladder voltage 28 (72 IRE) Resistance ladder voltage 29 (76 IRE) Resistance ladder voltage 30 (80 IRE) Resistance ladder voltage 31 (84 IRE) Resistance ladder voltage 32 (88 IRE) Resistance ladder voltage 33 (92 IRE) Resistance ladder voltage 34 (96 IRE) Resistance ladder voltage 35 (100 IRE)
Min 930 988 1046 1104 1162 1220 1278 1336 1394 1452 1510 1568 1626 1684 1742 1800 1858 1916 1974 2032 2090 2148 2206 2264 2322 2380 2438 2496 2554 2612 2670 2728 2786 2844 2902 2960
(AVCC = AVCC1 = AVCC2 = 5.0 V) Value Unit Typ Max 1000 1057 1114 1171 1229 1286 1343 1400 1457 1514 1571 1629 1686 1743 1800 1857 1914 1971 2029 2086 2143 2200 2257 2314 2371 2429 2486 2543 2600 2657 2714 2771 2829 2886 2943 3000 1040 1098 1156 1214 1272 1330 1388 1446 1504 1562 1620 1678 1736 1794 1852 1910 1968 2026 2084 2142 2200 2258 2316 2374 2432 2490 2548 2606 2664 2722 2780 2838 2896 2954 3012 3070 mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV
Note : Refer to "VOUT Output", "YOUT Output" and "COUT Output" about output waveform images. 15
MB90050
MB90050 Palette Initial Value * Pedestal level Color code Comment Pedestal Relative value PED (IRE) 0 Absolute value PED (IRE) 40 Register setting value PED (HEX) 0A
* Sink chip level Color code Comment Sink chip Relative value SYN (IRE) -40 Absolute value SYN (IRE) 0 Register setting value SYN (HEX) 00
* Translucence level Color code Comment translucence Relative value HAN (IRE) 32 Absolute value HAN (IRE) 72 Register setting value HAN (HEX) 12
* Color burst level Relative value Color code * Y (COLOR) Color code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 Comment White-1 Yellow-1 Cyan-1 Green-1 Magenta-1 Red-1 Blue-1 Black-1 White-0 Yellow-0 Cyan-0 Green-0 Magenta-0 Red-0 Blue-0 Black-0 Relative value Luminance (IRE) 100 72 64 56 40 32 24 16 92 64 56 48 32 24 16 8 Absolute value YD (IRE) 140 112 104 96 80 72 64 56 132 104 96 88 72 64 56 48 Register setting value YD (HEX) 23 1C 1A 18 14 12 10 0E 21 1A 18 16 12 10 0E 0C Comment Burst Absolute value Register setting value
BST0 BST1 BST2 BST3 BST0 BST1 BST2 BST3 BST0 BST1 BST2 BST3 (IRE) (IRE) (IRE) (IRE) (IRE) (IRE) (IRE) (IRE) (HEX) (HEX) (HEX) (HEX)
0
-24
0
24
40
16
40
64
0A
04
0A
10
MB90050
* C (COLOR) Relative value Color code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * V (COLOR) Absolute value Color code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Comment White-1 Yellow-1 Cyan-1 Green-1 Magenta-1 Red-1 Blue-1 Black-1 White-0 Yellow-0 Cyan-0 Green-0 Magenta-0 Red-0 Blue-0 Black-0 0 140 107 69 70 106 107 69 56 132 99 61 62 98 99 61 48 90 140 93 113 81 95 63 83 56 132 85 105 73 87 55 75 48 180 140 117 139 122 54 37 59 56 132 109 131 114 46 29 51 48 270 140 131 95 111 65 81 45 56 132 123 87 103 57 73 37 48 Register setting value VD0 (HEX) 23 1B 11 11 1B 1B 11 0E 21 19 0F 0F 19 19 0F 0C VD1 (HEX) 23 17 1C 14 18 10 15 0E 21 15 1A 12 16 0E 13 0C VD2 (HEX) 23 1D 23 1F 0D 09 0F 0E 21 1B 21 1D 0B 07 0D 0C VD3 (HEX) 23 21 18 1C 10 14 0B 0E 21 1F 16 1A 0E 12 09 0C 17 Comment White-1 Yellow-1 Cyan-1 Green-1 Magenta-1 Red-1 Blue-1 Black-1 White-0 Yellow-0 Cyan-0 Green-0 Magenta-0 Red-0 Blue-0 Black-0 Phase
(degrees)
Absolute value 0 40 35 5 14 66 75 45 40 40 35 5 14 66 75 45 40 90 40 21 49 25 55 31 59 40 40 21 49 25 55 31 59 40 180 40 45 75 66 14 5 35 40 40 45 75 66 14 5 35 40 270 40 59 31 55 25 49 21 40 40 59 31 55 25 49 21 40
Register setting value CD0 CD1 CD2 CD3 (HEX) (HEX) (HEX) (HEX) 0A 09 01 03 11 13 0B 0A 0A 09 01 03 11 13 0B 0A 0A 05 0C 06 0E 08 0F 0A 0A 05 0C 06 0E 08 0F 0A 0A 0B 13 11 03 01 09 0A 0A 0B 13 11 03 01 09 0A 0A 0F 08 0E 06 0C 05 0A 0A 0F 08 0E 06 0C 05 0A
Amplitude (IRE) 0 20 36 30 30 36 20 0 0 20 36 30 30 36 20 0
0 195 284 241 61 104 15 0 0 195 284 241 61 104 15 0
MB90050
* M (MONO) Color code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Comment Level-17 Level-16 Level-15 Level-14 Level-13 Level-12 Level-11 Level-10 Level-07 Level-06 Level-05 Level-04 Level-03 Level-02 Level-01 Level-00 Relative value Luminance (IRE) 100 80 68 60 44 36 24 16 92 72 60 52 36 28 16 8 Absolute value MD (IRE) 140 120 108 100 84 76 64 56 132 112 100 92 76 68 56 48 Register setting value MD (HEX) 23 1E 1B 19 15 13 10 0E 21 1C 19 17 13 11 0E 0C
Note : Minimum value for absolute value of IRE is 0. Maximum value for absolute value of IRE is 140. Relative value is the value when the pedestal level is 0IRE. * D (DIGITAL) Color code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18 Comment Level-15 Level-14 Level-13 Level-12 Level-11 Level-10 Level-09 Level-08 Level-07 Level-06 Level-05 Level-04 Level-03 Level-02 Level-01 Level-00 Display color signal output pin DCOL5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCOL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCOL3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 DCOL2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 DCOL1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 DCOL0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Register setting value DD (HEX) 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00
MB90050
* VOUT Output
VYELH
VWHT0
VCYAH VGREH VMAGH VREDH VBLUH
VGRY6 VGRY5 VGRY4 VYELL VBSTH VPED VBSTL VSYN VCYAL VGREL
VGRY3 VGRY2 VGRY1 VBLK0 VMAGL VREDL VBLUL
* YOUT Output
YWHT0 YGRY6 YGRY5 YGRY4 YGRY3 YGRY2 YGRY1 YBLK0
YPED
YSYN
* COUT Output
CCYAH CGREH CMAGH CREDH CYELH CBSTH CPED CBSTL CYELL CCYAL CGREL CMAGL CREDL CBLUL CBLUH
Note : Voltage of each output depends on Pallete setting value.
19
MB90050
2. AC Characteristics
Parameter Shift clock cycle time Shift clock pulse width Shift clock signal rise/fall time Shift clock start time Data setup time Data hold time Chip select end time Chip select signal rise/fall time Horizontal sync signal rise time Horizontal sync signal fall time Vertical sync signal rise time Vertical sync signal fall time Horizontal sync signal pulse width Vertical sync signal pulse width Symbol tCYC tWCH tWCL tCR tCF tSS tSU tH tEC tCRC tCPC tHR tHF tVR tVF tWH tWV
(Ta = -40 C to +85 C, VCC = 5.0 V10 %, VSS = 0 V) Value Pin name Unit Remarks Min Max SCLK SCLK SCLK SCLK SIN SIN CS CS HSYNCI HSYNCI VSYNCI VSYNCI HSYNCI VSYNCI 250 100 100 100 100 50 100 4.0 1 200 200 200 200 200 200 200 200 8.0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s H* Refer to "Field Signal Input Timing" Refer to "Reset Signal Input Timing" Refer to "Vertical* Horizontal Sync Signal Input Timing" Refer to "Serial Input Timing"
Field signal pulse width
tWF
FLDI
1
H*
Reset input pulse width
tWR
RESET
10
s
* : 1 H is assumed to be one horizontal sync signal period.
20
MB90050
* Serial Input Timing
CS
0.8 VCC 0.2 VCC tSS tCFC
0.8 VCC 0.2 VCC tCRC
tCYC
tEC 0.8 VCC
SCLK
tWCH tCR tCF tWCL
0.2 VCC
tH tSU
0.8 VCC
SIN
0.2 VCC
* Vertical*Horizontal Sync Signal Input Timing *
HSYNCI
0.8 VCC 0.2 VCC tHF tWH
0.8 VCC 0.2 VCC tHR
VSYNCI
0.8 VCC 0.2 VCC tVF tWV
0.8 VCC 0.2 VCC tVR
21
MB90050
* Field Signal Input Timing
FLDI
0.8 VCC 0.2 VCC tWF 0.2 VCC tWF
0.8 VCC
* Reset Signal Input Timing
RESET
0.2 VCC tWR 0.2 VCC
22
MB90050
3. Recommended Input Timings
H/V-separated sync signal input timing Parameter Vertical sync signal frequency Vertical sync signal pulse width Horizontal sync signal period Horizontal sync signal pulse width NTSC 60 (59.94) 1 to 5 63.492 (63.5555) 4.19 to 5.71 (4.70.1) PAL 30 1 to 4 64 4.5 to 4.9 Unit Hz H s s Remaeks *1 *2 *1 *1
*1 : Parenthesized values are specifications for color information display. *2 : 1 H is assumed to be one horizontal sync signal period.
4. Clock Timing
Parameter Dot clock for display* Clock for color burst (NTSC) * Clock for color burst (PAL) * Symbol fDC Pin EXD XD EXS XS Value Min 8 Typ 14.318185 17.734475 Max 20 Unit MHz MHz MHz Remarks
4 fSC
* : Input the signal with a duty cycle of 50%.
23
MB90050
5. Output Timings
(1) Horizontal timing Symbol HPS EQP1E HPE BSTS BSTE HBLKE SEP1S EQP2S EQP2E SEP2S HBLKS IHCLR NTSC (or simple PAL) 0 34 68 76 112 143 388 455 489 842 888 910 PAL (or simple NTSC) 0 42 84 100 140 186 484 568 610 1050 1106 1135 (1137) * Refer to "NTSC/PAL Horizontal Timing". Remarks
* : Parenthesized values assume the last raster in each V cycle (field) . Note : The values in the above list are 4 fsc count values. (2) Verticl timing Symbol VPS VPE EQPE VBLKE VBLKS VPS NTSC (or simple NTSC) Interlaced 0 6 12 36 519 525 Non interlaced 0 6 12 36 519 526 PAL (or simple PAL) Interlaced 0 5 10 45 620 625 Non interlaced 0 5 10 45 620 624 Remarks Refer to "NTSC Vertical Timing" and "PAL Vertical Timing".
Note : The values in the about list are 1/2 H count values. (1 H is assumed to be one horizontal sync signal period.)
24
MB90050
* NTSC/PAL Horizontal Timing
Video signal
Horizontal sync signal
Horizontal retrace blanking interval
Burst flag Equalizing pulse
Cut-in pulse
EQP2E EQP2S SEP1S HBLKE BSTE BSTS HPE EQP1E HPS HBLKS
IHCLR HBLKS SEP2S
25
26
MB90050
* NTSC Vertical Timing
Even-numbered field
521 522 523 524 525 1 2 3 4 5 6 7 ** 18 19 20 ** 258 259 260 261 262 263
Composite video signal Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Equalizing pulse interval
VBLKS VPS VPE EQPE VBLKE VBLKS VPS
Odd-numbered field
259 260 261 262 263 264 265 266 267 268 269 270 ** 280 281 282 ** 521 522 523 524 525 1
Composite video signal Horizontal scanning line No.
Vertical sync interval
Vertical retrace blanking interval
Equalizing pulse interval
VBLKS VPS VPE EQPE VBLKE VBLKS VPS
First field
* PAL Vertical Timing
Color burst phase Composite video signal Horizontal scanning line No. Vertical sync interval Vertical retrace blanking interval Equalizing pulse interval
621 622 623 624 625 1 2 3 4 5 6 7 ** 22 23 24 ** 308 309 310 311 312 313 BSTE VBLKS VPS VPE EQPE BSTS VBLKE BSTE VBLKS VPS
Second field
Color burst phase Composite video signal 309 310 311 Horizontal scanning line No. Vertical sync interval Vertical retrace blanking interval Equalizing pulse interval
312 313 314 315 316 317 318 319 320 ** 335 336 337 ** BSTE VBLKS VPS VPE EQPE BSTS VBLKE BSTE
621 622
623 624 625
1
VBLKS
Third field
621 622 623 624 625 1 2 3 4 5 6 7 ** 22 23 24 ** 308 309 310 311
VPS
Color burst phase Composite video signal Horizontal scanning line No. Vertical sync interval Vertical retrace blanking interval Equalizing pulse interval
BSTE VBLKS VPS VPE EQPE, BSTS
312
313
VBLKE
BSTS, VBLKS
VPS
Fourth field
312 313 314 315 316 317 318 319 320 ** 335 336 337 ** 621 622 623 624 625 1
Color burst phase 309 310 311 Composite video signal Horizontal scanning line No. Vertical sync interval Vertical retrace blanking interval Equalizing pulse interval
BSTE, VBLKS VPS VPE
EQPE
BSTS
VBLKE
BSTE VBLKS
VPS
MB90050
Notes : * x indicates the HSYNC positions in the equalizing pulse intends. * The arrows marks indicate the phase of color subcarrier. ( : +135, : -135)
27
MB90050
s COMMAND LIST
Command no. 15 to 12
Command code/data 11 10 9 8 7 FL 6 0 5 4 3 2 1 0
Function VRAM write address setting Character data setting 1 Character data setting 2 Line control data setting 1 Line control data setting 2 Screen output control 1 Screen output control 1 Vertical display position control Horizontal display position control Character vertical size control
0 1 2 3 4 5-0 5-1 5-2 5-3 6-0
0000 0001 0010 0011 0100 0101 0101 0101 0101 0110
AY3 AY2 AY1 AY0
AX5 AX4 AX3 AX2 AX1 AX0
MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0 MR MG MBL M8 M7 M6 M5 M4 M3 M2 LF2 L2 0 0 Y2 X2 M1 LF1 L1 0 0 Y1 X1 M0 LF0 L0 0 0 Y0 X0 HA
LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LDS 0 0 1 1 0 0 0 1 0 1 0 LG1 LG0 0 0 LD LE LM1 LM0 0 DSP L3 0 0 Y3 X3 0
SDS UDS
FM1 FM0 BT1 BT0 BD1 BD0 0 0 0 Y8 X8 0 Y7 X7 0 Y6 X6 Y5 X5 Y4 X4
HB2 HB1 HB0
HA2 HA1
6-1
0110
0
1
0
0
Shaded BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0 background frame color control Transparent/semiTC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0 transparent colors control GF3 GF2 GF1 GF0 GC3 GC2 GC1 GC0 0 0 0 0 U3 U2 U1 U0 Graphic color control Screen background control Sprite character control 1 Sprite character control 2 Sprite character control 3 Sprite character control 4
6-2
0110
1
0
TC
HC
6-3 7-3 8-1 8-2 9-0 9-1
0110 0111 1000 1000 1001 1001
1 1 0 1 0 1
1 1 1 0 0 0
GF 1
GC 0
SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0 1 SBL 0 SH2 SH1 SH0 0 0 0 0
SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0
(Continued)
28
MB90050
(Continued)
Command no. 15 to 12 11
Command code/data 10 0 1 1 0 1 0 1 0 0 1 9 0 0 8 0 0 7 VIX 0 6 HIX H2 5 0 H1 4 0 H0 3 IN1 VHE 0 2 IN0 HE F2 1 IE1 0 F1 0 0 F0 FDS FDC MC NP2 NP1 NP0
Function
11-0 11-1 11-3 12-0 12-1 12-2 12-3 13-0 13-1 14-0 14-1
1011 1011 1011 1100 1100 1100 1100 1101 1101 1110 1110
0 0 1 0 0 1 1 0 1 0 0
IE0 Sync control 1 Sync control 2 Sync detection control
STO BUO VSO HSO CSO VBO FDO DHO DBO DCO Output pin control 1 STX BUX VOX HOX COX VBX FDX DHX DBX DCX Output pin control 2 STU BUU VSU HSU CSU VBU FDU CKO FSO CKS FSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Output pin control 3 PO3 PO2 PO1 PO0 Output pin control 4
PLV PLY PLC PLM PLD PL3 PL2 PL1 PL0 Color palette setting AD5 AD4 AD3 AD2 AD1 AD0 Analog level control 0 0 FRS 0 0 0 0 FA1 FA0 Font RAM setting 1 FR2 FR1 FR0 Font RAM setting 2 0 0
AA2 AA1 AA0
Note : When a reset signal is input (L level signal input to RESET pin) , the screen output control 1 (command 5 to command 0) bits (SDS, UDS and DSP) and the output pin control 1 to 4 (command 12-0 to command 123) bits are initialized to "0".The color palette setting (command 13-0) and analog level control (command 13-1) bits are internally set to their predetermined initial values.The contents of other register bits, VRAM and font RAM are undefined. After reset input (release) is completed, set all command and font RAM settings.
29
MB90050
s SAMPLE CIRCUIT
MB90050
Composite IN Composite OUT
Video amplifier & clamp circuit
Y/C IN
VIN
VOUT
Buffer circuit
Y/C OUT
Video amplifier & clamp circuit Sync separation circuit
YIN CIN
YOUT COUT
Buffer circuit
VSYNCI HSYNCI
CS
Control microcontroller
SCLK SIN BUSY
+5V AVCC1 + AVCC2 AVSS1 AVSS2 +5V + VCC VSS
XD 3.3 H EXD
EXS XS
20 pF
20 pF
(Approx. 14 MHz)
NTSC: 14.31818 MHz PAL : 17.734475 MHz
30
MB90050
s MB90050-001 FONT DATA (MB90050-001 is typical product. )
000
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
01E
01F
020
021
022
023
024
025
026
027
028
029
02A
02B
02C
02D
02E
02F
030
031
032
033
034
035
036
037
038
039
03A
03B
03C
03D
03E
03F
(Continued) 31
MB90050
040
041
042
043
044
045
046
047
048
049
04A
04B
04C
04D
04E
04F
050
051
052
053
054
055
056
057
058
059
05A
05B
05C
05D
05E
05F
060
061
062
063
064
065
066
067
068
069
06A
06B
06C
06D
06E
06F
070
071
072
073
074
075
076
077
078
079
07A
07B
07C
07D
07E
07F
(Continued)
32
MB90050
080
081
082
083
084
085
086
087
088
089
08A
08B
08C
08D
08E
08F
090
091
092
093
094
095
096
097
098
099
09A
09B
09C
09D
09E
09F
0A0
0A1
0A2
0A3
0A4
0A5
0A6
0A7
0A8
0A9
0AA
0AB
0AC
0AD
0AE
0AF
0B0
0B1
0B2
0B3
0B4
0B5
0B6
0B7
0B8
0B9
0BA
0BB
0BC
0BD
0BE
0BF
(Continued)
33
MB90050
0C0
0C1
0C2
0C3
0C4
0C5
0C6
0C7
0C8
0C9
0CA
0CB
0CC
0CD
0CE
0CF
0D0
0D1
0D2
0D3
0D4
0D5
0D6
0D7
0D8
0D9
0DA
0DB
0DC
0DD
0DE
0DF
0E0
0E1
0E2
0E3
0E4
0E5
0E6
0E7
0E8
0E9
0EA
0EB
0EC
0ED
0EE
0EF
0F0
0F1
0F2
0F3
0F4
0F5
0F6
0F7
0F8
0F9
0FA
0FB
0FC
0FD
0FE
0FF
(Continued)
34
MB90050
100
101
102
103
104
105
106
107
108
109
10A
10B
10C
10D
10E
10F
110
111
112
113
114
115
116
117
118
119
11A
11B
11C
11D
11E
11F
120
121
122
123
124
125
126
127
128
129
12A
12B
12C
12D
12E
12F
130
131
132
133
134
135
136
137
138
139
13A
13B
13C
13D
13E
13F
(Continued)
35
MB90050
140
141
142
143
144
145
146
147
148
149
14A
14B
14C
14D
14E
14F
150
151
152
153
154
155
156
157
158
159
15A
15B
15C
15D
15E
15F
160
161
162
163
164
165
166
167
168
169
16A
16B
16C
16D
16E
16F
170
171
172
173
174
175
176
177
178
179
17A
17B
17C
17D
17E
17F
(Continued)
36
MB90050
180
181
182
183
184
185
186
187
188
189
18A
18B
18C
18D
18E
18F
190
191
192
193
194
195
196
197
198
199
19A
19B
19C
19D
19E
19F
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1AA
1AB
1AC
1AD
1AE
1AF
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1BA
1BB
1BC
1BD
1BE
1BF
(Continued)
37
MB90050
(Continued)
1C0
1C1
1C2
1C3
1C4
1C5
1C6
1C7
1C8
1C9
1CA
1CB
1CC
1CD
1CE
1CF
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1DA
1DB
1DC
1DD
1DE
1DF
1E0
1E1
1E2
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1EA
1EB
1EC
1ED
1EE
1EF
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
1F8
1F9
1FA
1FB
1FC
1FD
1FE
1FF
38
MB90050
s ORDERING INFORMATION
Part number MB90050PF Package 48-pin, plstic QFP (FPT-48P-M15) Remarks
39
MB90050
s PACKAGE DIMENSION
48-pin, plstic QFP (FPT-48P-M15) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
15.300.40(.602.016)SQ
* 12.000.10(.472.004)SQ
36 25
0.170.06 (.007.002)
37
24
Details of "A" part 2.40 -0.20 .094 -.008 0.10(.004)
+0.30 +.012
(Mounting height)
INDEX 0~8
48 13
1
12
"A"
0.850.30 (.033.012)
0.25 -0.20
+0.10 +.004
0.80(.031)
.010 -.008 (Stand off)
0.320.05 (.013.002)
0.20(.008)
M
C
2003 FUJITSU LIMITED F48025S-c-3-4
Dimensions in mm (inches)
40
MB90050
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any thirdpartyAfs intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0302 (c) FUJITSU LIMITED Printed in Japan

▲Up To Search▲

Price & Availability of MB90050

	To Download MB90050 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .