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PCK946
Low voltage 1 : 10 CMOS clock driver
Rev. 01 -- 13 December 2005 Product data sheet
1. General description
The PCK946 is a low voltage CMOS 1 : 10 clock buffer. The 10 outputs can be configured into a standard fan-out buffer or into 1x and 12x combinations. The ten outputs were designed and optimized to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 350 ps, the PCK946 is ideal as a clock distribution chip for synchronous systems which need a tight level of skew from a large number of outputs. With an output impedance of approximately 7 , in both the HIGH and LOW logic states, the output buffers of the PCK946 are ideal for driving series terminated transmission lines. More specifically, each of the 10 PCK946 outputs can drive two series terminated transmission lines. With this capability, the PCK946 has an effective fan-out of 1 : 20 in applications using point-to-point distribution schemes. The PCK946 has the capability of generating 1x and 12x signals from a 1x source. The design is fully static; the signals are generated and re-timed inside the chip to ensure minimal skew between the 1x and 12x signals. The device features selectability to allow the user to select the ratio of 1x outputs to 12x outputs. Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_SEL input pulled HIGH, the TCLK1 input is selected. All of the control inputs are LVCMOS/LVTTL compatible. The DSELn pins choose between 1x and 12x outputs. A LOW on the DSELn pins will select the 1x output. The MR/OE input will reset the internal flip-flops and 3-state the outputs when it is forced HIGH. The PCK946 is fully 3.3 V compatible. The 32-lead LQFP package was chosen to optimize performance, board space, and cost of the device. The 32-lead LQFP package has a 7 mm x 7 mm body size with a conservative 0.8 mm pin spacing.
2. Features
s s s s s s s 2 selectable LVCMOS/LVTTL clock inputs 350 ps output-to-output skew Drives up to 20 series terminated independent clock lines Maximum input/output frequency of 150 MHz 3-stateable outputs 32-lead LQFP packaging 3.3 V VCC supply voltage
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
3. Ordering information
Table 1: Ordering information Package Name PCK946BD LQFP32 Description plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm Version SOT358-1 Type number
4. Functional diagram
TCLK_SEL TCLK0
(internal pull-down) (internal pull-up) /1 /2 1 R
PCK946
0
3
0
TCLK1
(internal pull-up)
QA[0:2]
1
DSELA
(internal pull-down)
0
3
QB[0:2]
1 DSELB (internal pull-down)
0
4
QC[0:3]
1 DSELC MR/OE (internal pull-down) (internal pull-down)
002aaa676
Fig 1. Functional diagram of PCK946
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(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 13 December 2005
2 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
5. Pinning information
5.1 Pinning
32 MR/OE
31 GND
27 GND
30 QA0
26 QA2
28 QA1
29 VCC
TCLK_SEL VCCI TCLK0 TCLK1 DSELA DSELB DSELC GNDI
1 2 3 4 5 6 7 8 QC0 10 GND 11 QC1 12 VCC 13 QC2 14 GND 15 QC3 16 9
25 VCC 24 GND 23 QB0 22 VCC 21 QB1 20 GND 19 QB2 18 VCC 17 VCC
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PCK946BD
Fig 2. Pin configuration for LQFP32
5.2 Pin description
Table 2: Symbol DSELA, DSELB, DSELC GND GNDI MR/OE QA0, QA1, QA2 QB0, QB1, QB2 QC0, QC1, QC2, QC3 TCLK_SEL TCLK0, TCLK1 VCC VCCI Pin description Pin 5, 6, 7 11, 15, 20, 24, 27, 31 8 32 30, 28, 26 23, 21, 19 10, 12, 14, 16 1 3, 4 9, 13, 17, 18, 22, 25, 29 2 Description output bank divide select input ground ground internal reset and output (high-impedance) control bank A outputs bank B outputs bank C outputs CMOS clock select input CMOS clock inputs supply voltage supply voltage
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Product data sheet
Rev. 01 -- 13 December 2005
VCC
3 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
6. Functional description
6.1 Function table
Table 3: 0 1 Table 4: DSELn 0 1 Table 5: MR/OE 0 1 TCLK_SEL function table Input TCLK0 TCLK1 DSELn function table Outputs 1x
1 x 2
TCLK_SEL
MR/OE function table Outputs enabled high-impedance
7. Limiting values
Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI II Tstg Parameter supply voltage input voltage input current storage temperature CMOS inputs Conditions Min -0.3 -0.3 -40 Max +4.6 VCC + 0.3 20 +125 Unit V V mA C
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(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 13 December 2005
4 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
8. Static characteristics
Table 7: Static characteristics Tamb = 0 C to +70 C; VCC = 3.3 V 0.3 V Symbol VIH VIL VOH VOL II Ci CPD Iq(max)
[1] [2]
Parameter HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage input current input capacitance power dissipation capacitance maximum quiescent supply current
Conditions
Min 2.0 -
Typ 25 1
Max 3.6 0.8 0.4 120 4 2
Unit V V V V A pF pF mA
IOH = -20 mA IOL = 20 mA
[1] [1] [2]
2.5 -
per output
The PCK946 can drive 50 transmission lines on the incident edge. Each output can drive one 50 parallel terminated transmission line to the termination voltage of VT = 0.5VCC. Alternately, the device drives up to two 50 series terminated transmission lines. II current is a result of internal pull-up/pull-down resistors.
9. Dynamic characteristics
Table 8: Symbol fmax tPLH tPHL tsk(o) Dynamic characteristics Parameter maximum input clock frequency LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay output skew time TCLK to Qn TCLK to Qn output-to-output fmax < 100 MHz; same frequency outputs fmax < 100 MHz; different frequency outputs fmax > 100 MHz; same frequency outputs fmax > 100 MHz; different frequency outputs tsk(pr) tPZL tPZH tPLZ tPHZ tr tf
[1] [2] [3]
Conditions
[1] [1] [2] [1] [2] [1] [2]
Min 150 4.5 4.5 [3] [2] [2] [2] [2]
Typ 7.5 7.5 2.0 3 3 3 3 0.5 0.5
Max 11.5 11.5 350 350 350 450 4.5 11 11 11 11 1.0 1.0
Unit MHz ns ns ps ps ps ps ns ns ns ns ns ns ns
process skew time OFF-state to LOW propagation delay OFF-state to HIGH propagation delay LOW to OFF-state propagation delay HIGH to OFF-state propagation delay rise time fall time
part-to-part
0.1 0.1
output; 0.8 V to 2.0 V output; 2.0 V to 0.8 V
[2] [2]
Driving 50 transmission lines. Termination is 50 to 0.5VCC. Part-to-part skew at a given temperature and voltage.
9397 750 12296
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 13 December 2005
5 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
10. Application information
10.1 Driving transmission lines
The PCK946 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of approximately 10 the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to 0.5VCC. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCK946 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3, illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fan-out of the PCK946 clock driver is effectively doubled due to its capability to drive multiple lines.
PCK946
OUTPUT BUFFER
Ro Rs = 43 Zo = 50
IN
7
OutA
PCK946
OUTPUT BUFFER IN
Ro 7
Rs = 43
Zo = 50
OutB0
Rs = 43
Zo = 50
OutB1
002aaa678
Fig 3. Single versus dual transmission lines
The waveform plots of Figure 4 show simulation results of an output driving a single line versus two lines. In both cases the drive capability of the PCK946 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCK946. The output waveform in Figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Zo 25 V L = V S ------------------------------ = 3.0 --------- = 1.40 V R s + R o + Z o 53.5
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Product data sheet
Rev. 01 -- 13 December 2005
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Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns).
002aaa679
3.0 voltage (V) 2.0 IN
OutA td = 3.8956 ns OutB td = 3.9386 ns
1.0
0 -0.5 0 4 8 12 time (ns) 16
Fig 4. Single versus dual waveforms
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
PCK946
OUTPUT BUFFER IN
Ro 7
Rs = 36
Zo = 50
Rs = 36
Zo = 50
002aaa680
7 + 36 || 36 = 50 || 50 25 = 25
Fig 5. Optimized dual line termination
SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use.
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Product data sheet
Rev. 01 -- 13 December 2005
7 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
11. Package outline
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1
c
y X
24 25
17 16 ZE
A
e E HE wM bp pin 1 index 32 1 e bp D HD wM B vM B 8 ZD vM A 9 detail X L Lp A A2 A 1 (A 3)
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.4 0.3 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.8 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.25 y 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT358 -1 REFERENCES IEC 136E03 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-02-25 05-11-09
Fig 6. Package outline SOT358-1 (LQFP32)
9397 750 12296 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 13 December 2005
8 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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Product data sheet
Rev. 01 -- 13 December 2005
9 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
12.5 Package related soldering information
Table 9: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Product data sheet
Rev. 01 -- 13 December 2005
10 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
13. Abbreviations
Table 10: Acronym CMOS LVCMOS LVTTL Abbreviations Description Complementary Metal Oxide Silicon Low Voltage Complementary Metal Oxide Silicon Low Voltage Transistor-Transistor Logic
14. Revision history
Table 11: PCK946_1 Revision history Release date 20051213 Data sheet status Product data sheet Change notice Doc. number 9397 750 12296 Supersedes Document ID
9397 750 12296
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 13 December 2005
11 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 12296
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 13 December 2005
12 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
20. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 10.1 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Application information. . . . . . . . . . . . . . . . . . . 6 Driving transmission lines . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . 9 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . 9 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 10 Package related soldering information . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information . . . . . . . . . . . . . . . . . . . . 12
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 13 December 2005 Document number: 9397 750 12296
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