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| 027252/$ SEMICONDUCTOR TECHNICAL DATA Order this document by MC149570/D REV 2 0& Advance Information 0XOWL6WDQGDUG 9LGHR 3URFHVVRU 7KH 0& PXOWLVWDQGDUG YLGHR SURFHVVRU SURYLGHV WKH YLGHR FRPSUHVVLRQ GHFRPSUHVVLRQ DQG VFDOLQJ IXQFWLRQV IRU 4RUXV YLGHR FRPPXQLFDWLRQ V\VWHP DSSOLFDWLRQV 7R VXSSRUW WZRZD\ YLGHR FRPPXQLFDWLRQV WKH YLGHR SURFHVVRU FDQ GHFRGH DQG HQFRGH + DQGRU + YLGHR ELWVWUHDP VLPXOWDQHRXVO\ 7KH SURFHVVRU KDV D GLUHFW LQWHUIDFH WR D 176&3$/ GHFRGHU DQG HQFRGHU ,W UHTXLUHV 0E\WH ('2 '5$0V IRU IUDPH VWRULQJ 7KH 0& YLGHR SURFHVVRU SHUIRUPV ILYH PDMRU LQGHSHQGHQW YLGHR IXQFWLRQV 9LGHR 3UH3URFHVVLQJ 9LGHR 3RVW3URFHVVLQJ 9LGHR (QFRGLQJ 9LGHR 'HFRGLQJ DQG 3LFWXUH,Q3LFWXUH 3,3 3URFHVVLQJ 7KH IXQFWLRQDO EORFN GLDJUDP LQ )LJXUH VKRZV WKH PDMRU IXQFWLRQDO PRGXOHV WKDW HQDEOH WKH 0& WR SHUIRUP WKHVH IXQFWLRQV Video In (16) PreProcessor DCT/iDCT/ Quantizer Motion Estimator Rate Control System Bus Control (16) Video Out PostProcessor Bitstream Decoder Host Interface Bitstream Encoder Data (8), Address (5), Interrupt (2) DSP/CONTROLLER (32) EDO DRAM Figure 1. MC149570 Functional Block Diagram 4RUXV LV D UHJLVWHUHG WUDGHPDUN RI 0RWRUROD ,QF This document contains information on a new product. Specifications and information herein are subject to change without notice. Advance Information (c) 1999 MOTOROLA, INC. MC149570 Table of Contents Section 1 Section 2 Section 3 Section 4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Signal and Packaging Information . . . . . . . . . . . . . . . . 2-1 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 FOR TECHNICAL ASSISTANCE: 7HOHSKRQH ,QWHUQHW KWWSZZZPRWVSVFRPVXSSRUWWHFKQLFDO Data Sheet Conventions 7KLV GDWD VKHHW XVHV WKH IROORZLQJ FRQYHQWLRQV PIN_L asserted deasserted Examples: Used to indicate a signal that is active when pulled low. (For example, the DCS_L pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN_L PIN_L PIN PIN Note: Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. ii MC149570 Advance Information MOTOROLA MC149570 FEATURES 0XOWLSOH ,78 9LGHR 6WDQGDUG VXSSRUW | ,78 + | ,78 + ,QGHSHQGHQW YLGHR HQFRGH DQG GHFRGH HQJLQHV | (QFRGHV &,) x DQG 4&,) x VL]HG LPDJHV | 'HFRGHV &,) 4&,) DQG 64&,) x VL]HG LPDJHV | (QFRGHVGHFRGHV &,) XS WR IUDPHV SHU VHFRQG DQG 4&,) XS WR IUDPHV SHU VHFRQG 6XSSRUWV IURP NESV WR NESV YLGHR ELW UDWHV +DV YLGHR E\SDVV PRGH IRU VHOI YLHZ 9LGHR 3UH3URFHVVLQJ | $FFHSWV 176& RU 3$/ LQSXW YLGHR VLJQDOV | 1RQOLQHDU WHPSRUDO QRLVH FRUH ILOWHU UHGXFHV QRLVH DQG LPSURYHV FRGLQJ HIILFLHQF\ | 'DWD LQSXW VWUHDP FRPSOLDQW ZLWK ELW &&,5 VWDQGDUG | *OXHOHVV LQWHUIDFH WR LQGXVWU\ VWDQGDUG 176&3$/ YLGHR GHFRGHUV 9LGHR 3RVW3URFHVVLQJ | 6FDOHV &,)4&,)64&,) YLGHR WR VWDQGDUG 176&3$/ | 'HEORFNLQJ )LOWHULQJ DQG 0RVTXLWR )LOWHULQJ|5HGXFHV YLVLEOH DUWLIDFWV IURP YLGHR FRPSUHVVLRQ | )RXU SRVLWLRQV IRU 3LFWXUH,Q3LFWXUH 3,3 ZLWK PLUURU RSWLRQ WKDW DOORZV GLUHFW GLVSOD\ RI LQSXW YLGHR | 'DWD RXWSXW VWUHDP FRPSOLDQW ZLWK ELW &&,5 VWDQGDUG | /RFDO GLVSOD\ VFDOLQJ IURP &,) 4&,) DQG 64&,) WR GLIIHUHQW LQWHUODFHG GLVSOD\ VL]HV VHH 7DEOH Table 1. Display Scaling Type NTSC Input Resolution CIF QCIF SubQCIF Scaled Display Image 704 x 480 528 x 360 352 x 288 -- -- -- 704 x 480 528 x 360 352 x 240 264 x 180 176 x 288 176 x 144 512 x 320 384 x 240 256 x 160 192 x 120 128 x 192 704 x 576 528 x 432 352 x 576 352 x 288 -- 128 x 96 -- PAL CIF QCIF SubQCIF 704 x 576 528 x 432 352 x 288 264 x 216 176 x 288 176 x 144 512 x 384 384 x 288 256 x 192 192 x 144 128 x 192 128 x 96 MOTOROLA MC149570 Advance Information iii MC149570 | *OXHOHVV LQWHUIDFH WR LQGXVWU\ VWDQGDUG 176&3$/ YLGHR HQFRGHUV | &RPSHQVDWLRQ FLUFXLWU\ IRU GLVSOD\ RYHUVFDQ | )RXU VHOHFWDEOH FRORUV IRU ERUGHUEDFNJURXQG 0RWLRQ (VWLPDWLRQ | )XOO\ VXSSRUWV + $QQH[ ) $GYDQFHG 3UHGLFWLRQ 0RGH | )RXU PRWLRQ YHFWRUV SHU PDFUREORFN JHQHUDWHG VXSSRUWV RYHUODSSHG EORFN PRWLRQ FRPSUHVVLRQ IRU EHWWHU SLFWXUH TXDOLW\ DW ORZHU ELW UDWHV | 8QUHVWULFWHG PRWLRQ YHFWRUV FDQ H[WHQG SDVW SLFWXUH ERXQGDULHV WR LPSURYH SHUIRUPDQFH | 0RWLRQ HVWLPDWLRQ YHFWRU UDQJH H[WHQGV WR WR YHUWLFDO DQG KRUL]RQWDO SL[HOV | IXOO SHO PRWLRQ YHFWRU FDQGLGDWHV | +DOISL[HO VHDUFK PRWLRQ HVWLPDWLRQ 5DWH &RQWURO | ,QWHOOLJHQW IUDPH UDWH FRQWURO | '\QDPLF WUDGHRII EHWZHHQ WHPSRUDOVSDWLDO TXDOLW\ DQG ORZ ODWHQF\ IUDPH UDWH DGMXVWPHQW RQ XVHU LQSXW GXULQJ YLGHR FDOOV | 0LQLPXP GHOD\ GXH WR IXOO\ SLSHOLQHG SURFHVVLQJ 2WKHU IHDWXUHV | + DQG + PRGHV LQGHSHQGHQWO\ FRQILJXUDEOH IRU HQFRGHU DQG GHFRGHU | 176&3$/ ,2 PRGHV LQGHSHQGHQWO\ FRQILJXUDEOH | ELW +RVW ,QWHUIDFH SURYLGHV FKLS FRQWURO DQG ELWVWUHDP LQWHUIDFH | 7KLUW\ 2QFKLS UHJLVWHUV DOORZ WKH XVHU WR SURJUDP YLGHR SDUDPHWHUV | 2QFKLS '5$0 FRQWUROOHU LQWHUIDFHV ('2 '5$0 WKURXJK D ELW 'DWD %XV | 3URJUDPPDEOH RQFKLS 3KDVH /RFN /RRS 3// WKDW FDQ EH SURJUDPPHG WR UXQ IURP 0+] WR 0+] | 2SHUDWLQJ IUHTXHQF\ RI 0+] ZLWK YLGHR LQSXWRXWSXW IUHTXHQF\ RI 0+] | $OO LQSXWV DUH 9 WROHUDQW | 2SWLPL]HG IRU 9 RSHUDWLRQ IURP & WR & DPELHQW WHPSHUDWXUH | EDOO 3%*$ SDFNDJH ZLWK PLO EDOO SLWFK iv MC149570 Advance Information MOTOROLA 6LJQDO 'HVFULSWLRQV 6LJQDO *URXSLQJV 7KH LQSXW DQG RXWSXW VLJQDOV RI WKH 0& DUH RUJDQL]HG LQWR IXQFWLRQDO JURXSV DV VKRZQ LQ 7DEOH DQG DV LOOXVWUDWHG LQ )LJXUH 7KH 0& LV RSHUDWHG IURP D 9 VXSSO\ KRZHYHU DOO WKH LQSXW DQG ELGLUHFWLRQDO SLQV FDQ WROHUDWH 9 Table 1-1. MC149570 Functional Signal Groupings Functional Group Power (VCC_x) and Ground (GND_x) Reset Phase Lock Loop (PLL) and Clock Operation Mode Select Host Interface Video Input Video Output DRAM Interface Number of Signals 29 1 2 3 18 19 19 45 Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 1-9 MOTOROLA MC149570 Advance Information 1-1 MC149570 MC149570 VCC_IO VCC_Q GND_IO/Q VCC_A GND_A VCC_D GND_D GND/T 6 6 13 Power/Ground Video In 36 8 8 Reset VOPIXCLK VOCBLANK VOODDFIELD 8 MODESEL0 MODESEL1 MODESEL2 DCS_L DRD_L DWR_L DADDR4-DADDR0 DDATA7-DDATA0 DBSEIT_L DINT_L 5 8 Host Interface DRAM Interface 9 32 8 Operation Mode Select VOY7-VOY0 VOC7-VOC0 VIPIXCLK VICBLANK VIVSYNC VIY7-VIY0 VIC7-VIC0 SYSRESET CLOCKIN SYSPLLBP PLL/Clock Video Out RRAS_L RCAS_L RWR_L ROE_L RADDR8- RADDR0 RDATA31- RDATA0 Figure 1-1. MC149570 Signals Identified by Functional Group 1-2 MC149570 Advance Information MOTOROLA MC149570 3RZHU DQG *URXQG 6LJQDOV Table 1-2. MC149570 Power and Ground Signals Signal Name VCC_IO VCC_Q GND_IO/Q VCC_A GND_A VCC_D GND_D GND/T I/O Power Core Power I/O and Core Ground PLL Analog Power PLL Analog Ground PLL Digital Power PLL Digital Ground Thermal Ground Description Notes: 1. VCC_IQ, VCC_Q and VCC_D should be connected together on the PCB to a low impedance power source (i.e., a 3.3V power plane). 2. GND_IO, GND_Q, GND_A, GND_D, and GND/T should be connected together on the PCB to a low impedance path to ground (i.e., a ground plane). 3. VCC_A requires special treatment at the PCB level. The power should be connected thru a small resistor or ferrite bead to minimize coupling of digital noise into this pin. In addition, dedicated decoupling caps should be placed as close to the pin as possible. The PCB trace should be wider than normal (e.g., 40 mil) to minimize inductance. Refer to the schematic below: VCC 3V R1 4.7 C1 47F + C2 0.1 F C3 0.01 F !! VCC_A Place components as close to VCC_A pin as possible. 5HVHW 6LJQDOV Table 1-3. MC149570 Reset Signal Signal Name SYSRESET Signal Type Input1 Chip reset Detailed Description Notes: 1. All inputs are 5 V tolerant. MOTOROLA MC149570 Advance Information 1-3 MC149570 3// DQG &ORFN 6LJQDOV Table 1-4. MC149570 PLL and Clock Signals Signal Name CLOCKIN SYSPLLBP Signal Type Input2 Input1,2 Detailed Description Clock input to the on-chip PLL (default = 20 MHz) Asserting this signal bypasses the on-chip PLL. This pin must be asserted to bypass the PLL before changing the Operation Mode from Normal to the PLL Programming Mode. Notes: 1. See Section 1.5 for information about selecting the Operation Mode and its effect on PLL operation. 2. All inputs are 5 V tolerant. 2SHUDWLRQ 0RGH 6LJQDOV Table 1-5. MC149570 Operation Mode Signals Signal Name MODESEL0- MODESEL2 Signal Type Input1 Detailed Description The MODESEL signals combine to define eight operational modes for normal operations and diagnostics.2,3,4 Notes: 1. All inputs are 5 V tolerant. 2. Two operation modes are available to users: * Normal Operation Mode (all three signals = 0), and * PLL Programming Mode (all three signals = 1). 3. In the Normal Operation Mode, the PLL generates a default internal clock frequency of 2.2 times CLOCKIN. For example, if CLOCKIN = 20 MHz, the internal clock frequency is 44 MHz. 4. To change the ratio between CLOCKIN and the internal clock, select the PLL Programming Mode. See the MC149570 Programming Manual for information about programming the PLL ratio. 1-4 MC149570 Advance Information MOTOROLA MC149570 +RVW ,QWHUIDFH 6LJQDOV Table 1-6. MC149570 Host Interface Signals Signal Name DCS_L DRD_L DWR_L DADDR4-DADDR0 DDATA7-DDATA0 DBSEIT_L DINT_L Signal Type Input1 Input1 Input 1 Detailed Description Chip select from DSP/controller Read enable from DSP/controller Write enable from DSP/controller DSP/Controller Address bus DSP/Controller Interface data bus DSP/Controller BSE Interrupt DSP/Controller Interrupt Input1 Bidirectional2 Output Output Notes: 1. All inputs are 5 V tolerant. 2. Bidirectional inputs are 5 V tolerant; bidirectional outputs conform to Table 3-3. 9LGHR ,QSXW 6LJQDOV Table 1-7. MC149570 Video Input Signals Signal Name VIPIXCLK VICBLANK VIVSYNC VIY7-VIY0 VIC7-VIC0 Signal Type Input1 Input1 Input 1 Detailed Description Pixel clock Composite BLANK Vertical Sync Luma data Y in 4:2:2 Chroma data Cb/Cr Input1 Input 1 Notes: 1. All inputs are 5 V tolerant. MOTOROLA MC149570 Advance Information 1-5 MC149570 9LGHR 2XWSXW 6LJQDOV Table 1-8. MC149570 Video Output Signals Signal Name VOPIXCLK VOCBLANK VOODDFIELD VOY7-VOY0 VOC7-VOC0 Signal Type Input1 Input1 Input 1 Detailed Description Pixel clock Composite BLANK Odd field select Luma data Y in 4:2:2 Chroma data in 4:2:2 Output Output Notes: 1. All inputs are 5 V tolerant. '5$0 ,QWHUIDFH 6LJQDOV Table 1-9. MC149570 DRAM Interface Signals Signal Name RRAS_L RCAS_L RWR_L ROE_L RADDR8-RADDR0 RDATA31-RDATA0 Signal Type Output Output Output Output Output Bidirectional1 Detailed Description Row address strobe to EDO DRAMs Column address strobe to EDO DRAMs Write enable to EDO DRAMs Output enable for EDO DRAMs Address bus to EDO DRAMs Memory data bus Notes: 1. Bidirectional inputs are 5 V tolerant; bidirectional outputs conform to Table 3-3. 1-6 MC149570 Advance Information MOTOROLA 6LJQDO DQG 3DFNDJLQJ ,QIRUPDWLRQ ,QWURGXFWLRQ 7KLV VHFWLRQ SURYLGHV LQIRUPDWLRQ RQ SDFNDJLQJ LQFOXGLQJ D GLDJUDP RI WKH SDFNDJH ZLWK VLJQDOV DQG D WDEOH VKRZLQJ KRZ WKH VLJQDOV GHVFULEHG LQ 6HFWLRQ DUH DOORFDWHG 6HH )LJXUH IRU WKH VLJQDO QDPH DQG ORFDWLRQ LQIRUPDWLRQ 7KH 0& LV DYDLODEOH LQ D SRVLWLRQ 3ODVWLF %DOO *ULG $UUD\ 3%*$ SDFNDJH 6HH )LJXUH IRU SDFNDJH GHWDLOV 'HWDLOHG SDFNDJH GUDZLQJ IRU WKLV GHYLFH LV DOVR DYDLODEOH RQ WKH 0RWRUROD ZHE SDJH DW http://mot-sps.com/cgi-bin/cases 8VH SDFNDJH & IRU WKH VHDUFK MOTOROLA MC149570 Advance Information 2-1 MC149570 3%*$ 3DFNDJH 'HVFULSWLRQ $ 3%*$ SDFNDJH WRS YLHZ LV VKRZQ LQ )LJXUH ZLWK VLJQDO DQG ORFDWLRQ GHVLJQDWRUV 1 A 2 3 4 SYS RESET 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MODE SEL1 GND_IO/ VIVSYNC Q reserved reserved reserved nc reserved reserved VCC_A GND_A reserved nc reserved reserved reserved reserved reserved nc B nc VIPIXCLK reserved SYS PLLBP nc reserved nc reserved reserved CLOCKIN reserved reserved nc reserved nc reserved MODE SEL2 nc RDATA31 RDATA30 C VIY2 nc VICBLANK reserved reserved MODE SEL0 reserved reserved reserved VCC_D reserved reserved reserved reserved reserved reserved reserved reserved RDATA29 RDATA26 D VIY3 nc VIY0 GND_IO/ Q reserved VCC_IO reserved GND_IO/ Q reserved GND_D VCC_Q reserved GND_IO/ Q nc VCC_IO reserved GND_IO/ RDATA28 RDATA25 Q nc E VIY4 nc nc VIY1 RDATA27 nc RDATA24 reserved F nc VIY7 VIY5 VCC_IO VCC_Q RDATA23 RDATA21 nc G nc nc nc VIY6 RDATA22 RDATA20 nc RDATA19 H VIC2 VIC1 VIC0 GND_IO/ Q GND/T GND/T GND/T GND/T GND/T GND/T GND_IO/ RDATA18 RDATA17 RDATA16 Q J VIC6 VIC5 VIC4 VIC3 GND/T GND/T GND/T GND/T GND/T GND/T nc nc RCAS_L RDATA15 K nc VIC7 nc VCC_Q GND/T GND/T GND/T GND/T GND/T GND/T RDATA14 RDATA13 RDATA12 RDATA11 L nc nc reserved reserved GND/T GND/T GND/T GND/T GND/T GND/T VCC_Q RDATA9 RDATA8 RDATA10 M reserved reserved VOC0 VOC1 GND/T GND/T GND/T GND/T GND/T GND/T nc nc nc nc N P nc nc VOC2 GND_IO/ Q GND/T GND/T GND/T GND/T GND/T GND/T GND_IO/Q RDATA5 RDATA6 RDATA7 VOC3 VOC4 VOC6 nc RDATA1 nc RDATA3 RDATA4 R VOC5 VOC7 nc VCC_IO VCC_Q RDATA0 RDATA2 nc T nc nc VOY1 nc RADDR5 RADDR8 nc nc U VOY0 VOY2 nc GND_IO/ Q reserved VCC_Q DADDR1 GND_IO/ Q DDATA3 VCC_IO nc nc GND_IO/ Q nc VCC_IO ROE_L GND_IO/Q RADDR4 RADDR3 RADDR7 V VOY3 VOY4 VOY6 VOODD FIELD nc DADDR0 DADDR4 DDATA0 nc DDATA6 nc nc DCS_L DRD_L nc reserved RWR_L nc RADDR2 RADDR6 W VOY5 VOY7 nc VOC BLANK nc DADDR2 nc DDATA1 nc DDATA5 nc nc DINT_L nc reserved reserved nc RRAS_L RADDR0 RADDR1 Y nc VOPIXCL reserved nc nc DADDR3 nc DDATA2 DDATA4 DDATA7 nc nc DBSEIT_L nc DWR_L reserved reserved nc nc nc Figure 2-1. MC149570 292-Position PBGA Diagram NOTE: Locations marked as reserved must not be connected. 2-2 MC149570 Advance Information MOTOROLA MC149570 Table 2-1. MC149570 292-Position PBGA Package Signal List Location A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Signal Name GND_IO/Q VIVSYNC reserved SYSRESET reserved reserved nc reserved reserved VCC_A GND_A reserved nc reserved reserved reserved reserved reserved nc MODESEL1 Location B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 Signal Name nc VIPIXCLK reserved SYSPLLBP nc reserved nc reserved reserved CLOCKIN reserved reserved nc reserved nc reserved MODESEL2 nc RDATA31 RDATA30 Location C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 Signal Name VIY2 nc VICBLANK reserved reserved MODESEL0 reserved reserved reserved VCC_D reserved reserved reserved reserved reserved reserved reserved reserved RDATA29 RDATA26 Location D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 Signal Name VIY3 nc VIY0 GND_IO/Q reserved VCC_IO reserved GND_IO/Q reserved GND_D VCC_Q reserved GND_IO/Q nc VCC_IO reserved GND_IO/Q RDATA28 RDATA25 nc MOTOROLA MC149570 Advance Informationt 2-3 MC149570 Table 2-1. MC149570 292-Position PBGA Package Signal List (Continued) Location E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H8 Signal Name VIY4 nc nc VIY1 RDATA27 nc RDATA24 reserved nc VIY7 VIY5 VCC_IO VCC_Q RDATA23 RDATA21 nc nc nc nc VIY6 RDATA22 RDATA20 nc RDATA19 VIC2 VIC1 VIC0 GND_IO/Q GND/T Location H9 H10 H11 H12 H13 H17 H18 H19 H20 J1 J2 J3 J4 J8 J9 J10 J11 J12 J13 J17 J18 J19 J20 K1 K2 K3 K4 K8 K9 Signal Name GND/T GND/T GND/T GND/T GND/T GND_IO/Q RDATA18 RDATA17 RDATA16 VIC6 VIC5 VIC4 VIC3 GND/T GND/T GND/T GND/T GND/T GND/T nc nc RCAS_L RDATA15 nc VIC7 nc VCC_Q GND/T GND/T Location K10 K11 K12 K13 K17 K18 K19 K20 L1 L2 L3 L4 L8 L9 L10 L11 L12 L13 L17 L18 L19 L20 M1 M2 M3 M4 M8 M9 M10 Signal Name GND/T GND/T GND/T GND/T RDATA14 RDATA18 RDATA12 RDATA11 nc nc reserved reserved GND/T GND/T GND/T GND/T GND/T GND/T VCC_Q RDATA9 RDATA8 RDATA10 reserved reserved VOC0 VOC1 GND/T GND/T GND/T Location M11 M12 M13 M17 M18 M19 M20 N1 N2 N3 N4 N8 N9 N10 N11 N12 N13 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 Signal Name GND/T GND/T GND/T nc nc nc nc nc nc VOC2 GND_IO/Q GND/T GND/T GND/T GND/T GND/T GND/T GND_IO/Q RDATA5 RDATA6 RDATA7 VOC3 VOC4 VOC6 nc RDATA1 nc RDATA3 RDATA4 2-4 MC149570 Advance Information MOTOROLA MC149570 Table 2-1. MC149570 292-Position PBGA Package Signal List (Continued) Location R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 Signal Name VOC5 VOC7 nc VCC_IO VCC_Q RDATA0 RDATA2 nc nc nc VOY1 nc RADDR5 RADDR8 nc nc VOY0 VOY2 nc GND_IO/Q reserved VCC_Q DADDR1 GND_IO/Q Location U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 Signal Name DDATA3 VCC_IO nc nc GND_IO/Q nc VCC_IO ROE_L GND_IO/Q RADDR4 RADDR3 RADDR7 VOY3 VOY4 VOY6 VOODD FIELD nc DADDR0 DADDR4 DDATA0 nc DDATA6 nc nc Location V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 Signal Name DCS_L DRD_L nc reserved RWR_L nc RADDR2 RADDR6 VOY5 VOY7 nc VOCBLANK nc DADDR2 nc DDATA1 nc DDATA5 nc nc DINT_L nc reserved reserved Location W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name nc RRAS_L RADDR0 RADDR1 nc VOPIXCL reserved nc nc DADDR3 nc DDATA2 DDATA4 DDATA7 nc nc DBSEIT_L nc DWR_L reserved reserved nc nc nc MOTOROLA MC149570 Advance Informationt 2-5 MC149570 PIN A1 INDEX D C 4X 0.2 A 292X 0.2 A E E2 0.35 A D2 B TOP VIEW (D1) 19X 0.2 M ABC NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A. 4. PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. e Y W V U T R P N M L K J H G F E D C B A 19X e MILLIMETERS DIM MIN MAX A 2.05 2.65 A1 0.50 0.70 A2 0.50 0.70 A3 1.05 1.25 b 0.60 0.90 D 27.00 BSC D1 24.13 REF D2 23.30 24.70 E 27.00 BSC E1 24.13 REF E2 23.30 24.70 e 1.27 BSC (E1) 4X A1 A3 A2 A SIDE VIEW 282X e /2 1 2 3 4 5 6 7 8 9 10111213141516171819 20 b3 M BOTTOM VIEW 0.3 ABC A 0.15 M CASE 1135C-01 ISSUE O DATE 11/06/97 Figure 2-2. 292-Pin PBGA Package Details 2-6 MC149570 Advance Information MOTOROLA 6SHFLILFDWLRQV ,QWURGXFWLRQ 7KH 0& VSHFLILFDWLRQV DUH SUHOLPLQDU\ DQG DUH IURP GHVLJQ VLPXODWLRQV 7KH\ PD\ QRW EH IXOO\ WHVWHG RU JXDUDQWHHG DW WKLV HDUO\ VWDJH RI WKH SURGXFW OLIH F\FOH )LQDOL]HG VSHFLILFDWLRQV ZLOO EH SXEOLVKHG DIWHU IXOO FKDUDFWHUL]DWLRQ DQG GHYLFH TXDOLILFDWLRQV DUH FRPSOHWH 0D[LPXP 5DWLQJV Table 3-1. Power and Temperature Ratings Rating Symbol VCC VIN TA TSTG Value -0.3 to +4.0 0 to 5.5 0 to +70 -55 to +150 Unit V V C C Supply voltage All input voltage Operating Temperature Range Storage Temperature Note: Absolute maximum ratings are stress ratings only and functional operation at the maximum limits is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 7KHUPDO &KDUDFWHULVWLFV Table 3-2. Package Thermal Characteristics Characteristic Symbol JA Value 24 Unit C/W Junction to Ambient Thermal Resistance MOTOROLA MC149570 Advance Information 3-1 MC149570 '& (OHFWULFDO &KDUDFWHULVWLFV Table 3-3. DC Electrical Characteristics Characteristics Symbol VCC VIH VIL VOH Min 3.0 2.0 0 2.4 Typ 3.3 -- -- -- Max 3.6 5.5 0.8 VCC Unit V V V V Supply Voltage Input High Voltage Input Low Voltage Output High Voltage * DDATA7-DDATA0, RCAS_L (IOH = 8mA) * RDATA31-RDATA0, RADDR8- RADDR0, ROE_L, RRAS_L, RWR_L (IOH = -4 mA) * VOC7-VOC0, VOY7-VOY0, DBSEIT_L, DINT_L (IOH = -2 mA) Output Low Voltage * DDATA7-DDATA0, RCAS_L (IOL = 8mA) * RDATA31-RDATA0, RADDR8- RADDR0, ROE_L, RRAS_L, RWR_L (IOL = 4 mA) * VOC7-VOC0, VOY7-VOY0, DBSEIT_L, DINT_L (IOL = 2 mA) Input Leakage Current (@ 5.5V / Maximum VCC / 0.0V) Input Leakage Current (2)(@ Maximum VCC / 0.0V) High Impedance Input Current Icc in Normal Operation Mode Input Capacitance VOL 0 -- 0.4 V IIN IIN -10 -10 -- -- 10(1) 100 A A A Itsi ICC -- -10 -- -- -- -- 9 10 450 mA pF Notes: 1. Not including the following 5 input pins with internal pull down resistor: Mode Select 0, Mode Select 1, Mode Select 2, SYSRESET, SYSPLLBP 2. Input Leakage Current for: Mode Select 0, Mode Select 1, Mode Select 2, SYSRESET, SYSPLLBP 3-2 MC149570 Advance Information MOTOROLA MC149570 $& (OHFWULFDO &KDUDFWHULVWLFV 7KH WLPLQJ ZDYHIRUPV VKRZQ LQ WKLV VHFWLRQ DUH WHVWHG ZLWK D 9LO PD[LPXP RI 9 DQG 9LK PLQLPXP RI 9 IRU DOO SLQV $& WLPLQJ VSHFLILFDWLRQV ZKLFK DUH UHIHUHQFHG WR D GHYLFH LQSXW VLJQDO DUH PHDVXUHG LQ SURGXFWLRQ ZLWK UHVSHFW WR WKH SRLQW RI WKH UHVSHFWLYH LQSXW VLJQDOV WUDQVLWLRQ 2XWSXW OHYHOV DUH PHDVXUHG ZLWK WKH SURGXFWLRQ WHVW PDFKLQH 9RO DQG 9RK UHIHUHQFH OHYHOV VHW DW 9 DQG 9 UHVSHFWLYHO\ 0& &KLS 5HVHW 0& VXSSRUWV D OHYHOVHQVLWLYH UHVHW 7R JHQHUDWH D FKLSOHYHO UHVHW DVVHUW WKH 6<65(6(7 VLJQDO 7KLV UHVHWV WKH UHJLVWHUV DVVRFLDWHG ZLWK WKH 3// FRQWURO 7KHQ PV ODWHU GHDVVHUW 6<65(6(7 *LYHQ D 0+] &/2&.,1 DQG WKH GHIDXOW VHWWLQJ IRU WKH 3// SURJUDPPLQJ UHJLVWHU )5 UHJLVWHU WKH 0& DFFHSWV SURJUDPPHG YDOXHV &/2&.,1 F\FOHV DIWHU WKH IDOOLQJ HGJH RI 6<65(6(7 CLOCKIN SYSRESET 1 ms 22 Cycles (CLOCKIN) Figure 3-1. Reset Timing 3// 3URJUDPPLQJ 0RGH 0& HQWHUV WKH 3// 3URJUDPPLQJ PRGH ZKHQ WKH WKUHH PRGH SLQV 02'(6(/ 02'(/6(/ DQG 02'(6(/ DUH VHW WR DOO RQHV ,Q WKH 3// SURJUDPPLQJ PRGH WKH RQFKLS 3// LV DXWRPDWLFDOO\ E\SDVVHG DQG WKH 0& UXQV DW KDOI WKH IUHTXHQF\ RI &/2&.,1 7KH RQFKLS 3// FDQ WKHQ EH SURJUDPPHG E\ ZULWLQJ D GHVLUHG UDWLR YDOXH LQWR WKH 3//B5B) UHJLVWHU ) 1RWH WKDW WKH UDWLR RI )5 FDQ QRW EH OHVV WKDQ 'XH WR D VHWWOH WLPH UHTXLUHPHQW IRU WKH 3// WKH 3// PXVW VWD\ LQ WKLV PRGH IRU DW OHDVW P6HF DIWHU ZULWLQJ WR WKH 3//B5B) UHJLVWHU $Q LQWHUQDO UHVHW LV WULJJHUHG DV VRRQ DV 0& H[LWV WKH 3// 3URJUDPPLQJ PRGH 7KH LQWHUQDO UHVHW SHUIRUPV WKH VDPH IXQFWLRQ DV WKH QRUPDO V\VWHP UHVHW ZKLOH UHVHUYLQJ WKH QHZ 5 DQG ) YDOXHV :DUQLQJ 3HUIRUPLQJ D QRUPDO V\VWHP UHVHW DIWHU H[LWLQJ WKH 3// SURJUDPPLQJ PRGH UHWXUQV WKH 0& WR WKH GHIDXOW YDOXHV MODESEL0- 000 MODESEL2 DDATA7- DDATA0 111 000 PLL_R_F Value 1 ms or longer Figure 3-2. PLL ProgrammingTiming MOTOROLA MC149570 Advance Information 3-3 MC149570 +RVW ,QWHUIDFH :ULWH 7LPLQJV Table 3-4. Host Interface Write Timings (Host Writes to MC149570) No. 1 2 3 4 5 6 7 8 9 Characteristics Address valid to Write Enable Deassertion Write Enable Cycle Time Write Enable Deassertion Time Write Data Setup Time w.r.t Write Enable Deassertion Write Data Hold Time w.r.t. Write Enable Deassertion Previous Read Enable Deassertion to Write Enable Deassertion Write Enable Deassertion to Address Not Valid Chip Select to Write Enable Assertion Write Enable Deassertion to Chip Select Inactive Min Delay 9 35 3 5 2 35 2 0.1 2 Max Delay - Units ns ns ns ns ns ns ns ns ns 8 9 DCS_L DADDR Write Address 7 1 DWR_L 3 2 DRD_L 4 5 DDATA 6 Write Data Figure 3-3. Host Interface Write Timings 3-4 MC149570 Advance Information MOTOROLA MC149570 +RVW ,QWHUIDFH 5HDG 7LPLQJV Table 3-5. Host Interface Read Timings (Host Read from MC149570) No. 10 11 12 13 14 15 16 17 18 Characteristics Address valid to Data Active Read Enable Cycle Time Read Enable Deassertion Time Read Enable Assertion to Data Active Read Data Hold Time w.r.t. Read Enable Deassertion Previous Write Enable Deassertion to Read Enable Deassertion Read Enable Deassertion to Address Invalid Chip Select to Read Enable Assertion Read Enable De-assertion to Chip Select Inactive Min Max 9 Units ns ns ns ns ns ns ns ns ns 35 3 8 1 35 2 0.1 2 6 - 17 18 DCS_L DADDR 10 Read Address 16 DRD_L 12 11 DWR_L 13 14 DDATA 15 Read Data Figure 3-4. Host Interface Read Timings MOTOROLA MC149570 Advance Information 3-5 MC149570 ,QWHUUXSW 7LPLQJV Table 3-6. Periodic Interrupt Latency Timings Max. Host Response Time after an Interrupt Request 9 1 not limited Periodical Interrupts Minimum Time Between Interrupts 25.7 33 25.7 Units Request for transmit of encoded bitstream (DBSEIT_L) Request for bits transmitted over channel (DINT_L) Request for incoming bitstream(DINT_L) s ms s 7KHUH DUH QR GHILQHG OLPLWV IRU QRQSHULRGLF LQWHUUXSWV VXFK DV 8QVXSSRUWHG + RSWLRQV | 8QUHVWULFWHG PRWLRQ 9HFWRUV | &30 | 3% IUDPH | $ULWKPHWLF FRGLQJ ++ HUURUV | ,QYDOLG 3LFWXUH 7\SH | ,OOHJDO 9DULDEOH /HQJWK &RGH | 0RUH WKDQ FRHIILFLHQWV IRU UXQOHQJWK GHFRGH | 8QH[SHFWHG VWDUW FRGH | ,QFRUUHFW 0DFUREORFNV %XIIHU 8QGHUIORZ2YHUIORZ | %LWVWUHDP UHFHLYH EXIIHU | %LWVWUHDP WUDQVPLW EXIIHU 3-6 MC149570 Advance Information MOTOROLA MC149570 9LGHR 6LJQDO 7LPLQJ Table 3-7. Video Timing Clock Signals Frequency 13.5 Units MHz VIPIXCLK, VOPIXCLK Table 3-8. Video Input Timings No. 19 20 21 22 23 24 Characteristics VIVSYNCH Set-up Time VIVSYNCH Hold Time VICBLANK Active and Inactive Set-upTime VICBLANK Hold Time Data Set-up Time Data Hold Time Min 3 3 6 3 3 3 Max -- -- -- -- -- -- Units ns ns ns ns ns ns VIPIXCLK 20 ... 19 VIVSYNCH VICBLANK 21 21 22 VIY7-VIY0 VIC7-VIC0 23 Y0 Cb0 Y1 Cr0 Y2 Cb1 Cr1 24 Figure 3-5. Input Video Signals MOTOROLA MC149570 Advance Information 3-7 MC149570 Table 3-9. Video Output Timings No. 25 26 27 28 29 30 Characteristics VOODDFIELD Set-up Time VOODDFIELD Hold Time VOCBLANK Active and Inactive Set-up Time VOCBLANK Hold Time Video Out Data Delay Video Out Data Hold Time Min Delay 13 3 9 3 4 Max Delay - Units ns ns ns 22 - ns ns ns VOPIXCLK ... 26 25 25 VOODDFIELD (Active High) VOCBLANK 27 27 28 VOY7-VOY0 VOC7-VOC0 29 Y0 Cb0 Y1 Cr0 Y2 Cb1 Cr1 30 Figure 3-6. Output Video Signals 3-8 MC149570 Advance Information MOTOROLA MC149570 Table 3-10. NTSC/PAL Decode Parameters Characteristic VIVSYNC minimum pulse width VICBLANK active video width NTSC line width PAL line width NTSC active lines PAL active lines Value 1 VIPIXCLK 720 VIPIXCLKs 858 VIPIXCLKs 864 VIPIXCLKs 240 lines 288 lines Table 3-11. NTSC/PAL Encoder Parameters Characteristic VOCBLANK active video width NTSC active lines PAL active lines Value 720 VOPIXCLKs 240 lines 288 lines MOTOROLA MC149570 Advance Information 3-9 MC149570 3-10 MC149570 Advance Information MOTOROLA 3URJUDPPDELOLW\ 3URJUDPPLQJ 5HJLVWHUV 0& KDV SURJUDPPDEOH UHJLVWHUV DV VKRZQ LQ )LJXUH 7KH UHJLVWHUV SURYLGH V\VWHP FRQILJXUDELOLW\ IRU WKH VXSSRUWHG PDMRU YLGHR IXQFWLRQV Device ID BSD_Config RC_Config Pre_Config Post_Config Enc_Par1 Enc_Par2 Enc_Par3 BSE_BPP RC_BitXMT RC_FDTM RC_TBOVR RC_AVGQ RC_QOVR RC_Rate Reset Decode_PSize BSE_Num_Bytes BSE_Data BSD_Num_Bytes BSD_Data Int_Status Int_Mask Err_Status Err_Mask RESERVED RESERVED RC_Scale RC_ABPF RC_MBPF Post_Loc PLL_R_F 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f ID Register Decode Register Encode Register Pre-Processor Register Post-Processor Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Control Register Decode Register Encode Register Encode Register Decode Register Decode Register Control Register Control Register Control Register Control Register Control Register Control Register Encode Register Encode Register Encode Register Post-Processor Register Control Register For information on programming details, refer to the MC149570 Programming Manual Figure 4-1. MC149570 Configuration Register Layout MOTOROLA MC149570 Advance Informaition 4-1 MC149570 3URJUDPPDEOH )HDWXUHV Table 4-1. MC149570 Programmable Features Video Processing Pre-Processing Feature Noise Core Filtering Picture Format to be captured On or Off NTSC or PAL NTSC or PAL Value Post-Processing Display Format Picture Size NTSC resolutions: * CIF: 704 x 480, 528 x 360, 352 x 288 * QCIF: 704 x 480, 528 x 360, 352 x 240, 264 x 180, 176 x 288, 176 x 144 * SubQCIF: 512 x 320, 384 x 240, 256 x 160, 192 x 120, 128 x 192, 128 x 96 PAL resolutions: * CIF: 704 x 576, 528 x 432, 352 x 576, 352 x 288 * QCIF: 704 x 576, 528 x 432, 352 x 288, 264 x 216, 176 x 288, 176 x 144 * SubQCIF: 512 x 384, 384 x 288, 256 x 192, 192 x 144, 128 x 192, 128 x 96 0-7 On or Off 0-126 pixels move horizontally to the left or right in increments of 2 0-62 pixels move vertically up or down in increments of 2 Four locations: upper right, upper left, lower left, and lower right Four Options: Black, Green, Blue, and Purple On or Off On or Off Mosquito Filter Threshold Deblocking Filter Picture Location Horizontal Adjustment Picture Location Vertical Adjustment PIP Location Background Color PIP mirror Video Bypass/Selfview 4-2 MC149570 Advance Informaition MOTOROLA MC149570 Table 4-1. MC149570 Programmable Features (Continued) Video Processing Encoding Feature Encode Resolution Bitstream Syntax BCH Framing Advanced Prediction Mode (APM) Freeze Picture Release Number of GOB Headers Adjusted Quantization Target Minimum Picture Interval Intraframe Count Channel Bit Rate CIF or QCIF H.261 or H.263 On or Off On or Off On or Off Value Four options: every other, every fourth, all, and none 1-31 0-31 0-31 (0-8191) * 64 CIF, QCIF, or SubQCIF H.261 or H.263 Decoding Decoded Picture Resolution1 Decoded Picture Bitstream Syntax1 Stop Display on Error Picture Freeze On or Off On or Off 27 MHz-44 MHz PLL Programming Clock Scalability Notes: 1. Determined by incoming encoded video bitstream MOTOROLA MC149570 Advance Informaition 4-3 4RUXV DQG 0ID[ DUH UHJLVWHUHG WUDGHPDUNV RI 0RWRUROD ,QF Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such are claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1 (800) 441-2447 1 (303) 675-2140 Customer Focus Center: 1 (800) 521-6274 Internet: www.motorola.com/qorus www.mot-sps.com/sps/general/sales.html MfaxTM: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 USA and Canada ONLY: 1 (800) 774-1848 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office, 141 4-32-1, Nishi- Gotanda Shinagawa-ku, Tokyo, Japan 81-3-5487-8488 |
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