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MIC1832 P Supervisory Circuit
MIC1832
P Supervisory Circuit
Description
The MIC1832 is a multifunction circuit which monitors microprocessor activity, external reset and power supplies in microprocessor based systems. The circuit functions include a watchdog timer, power supply monitor, microprocessor reset, and manual pushbutton reset input. The power supply line is monitored with a comparator and an internal voltage reference. RST is forced low when an out-of-tolerance condition exists and remains asserted for at least 250ms after VCC rises above the threshold voltage (2.55V or 2.88V). The RST pin will remain logic low with VCC as low as 1.4V. The Watchdog input (ST) monitors P activity and will assert RST if no P activity has occurred within the watchdog timeout period. The watchdog timeout period is selectable with a nominal periods of 150, 600, or 1200 milliseconds.
Pin Configuration
Top View
PBRST TD TOL GND
1 2 3 4
8
VCC ST RST RST
MIC1832
7 6 5
MIC1832N - 8 Lead Plastic DIP Package MIC1832M - 8 Lead Plastic SOIC Package
Features
Typical Applications
* Automotive Systems * Intelligent Instruments * Critical Microprocessor Power Monitoring * Battery Powered Computers * Controllers
Ordering Information
Part MIC1832N MIC1832M Package 8-Lead PDIP 8-Lead SOIC Temp. Range -40C to +85C -40C to +85C
* Power OK/Reset Time Delay, 250ms min. * Watchdog Timer, 150ms, 600ms, or 1.2s typical Supply Voltage Monitor, Select * Precision 5% or 10% of Supply Voltage Between * Available in 8-pin Surface Mount (SO) * Debounced External Reset Input * Low Supply Current, < 18A Typ.
Typical Operating Circuit
VCC
VCC
TD
VCC
MIC1832
PBRST ST RST TOL GND I/O
P
RESET
1
MIC1832 P Supervisory Circuit
Absolute Maximum Ratings
Terminal Voltage VCC, . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.0V All Other Inputs . . . . . . . . . . . . -0.3V to (VCC + 0.3V) Input Current VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mA Gnd, All Other Inputs . . . . . . . . . . . . . . . . . . . . 25mA
Operating Temperature Range MIC1832_ . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage Temperature Range . . . . . . . . . . . . .-65C to 150C Lead Temperature (Soldering - 10 sec.) . . . . . . . . . . . 300C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 700mW
Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Operating ranges define those limits between which the functionality of the device is guaranteed.
Electrical Characteristics
VCC = 3 to 5.5 V, TA = Operating Temperature Range, unless otherwise noted. Parameter Supply Voltage Range Supply Current Conditions VCC ICC @ VCC = 5V (See Note 1) ICC @ VCC = 3.3V (See Note 1) VIH (See Note 2) VIH (See Note 3) VIL Input Leakage, ST (See Note 4) Output Voltage, RST, RST Output Voltage, RST, RST Output Voltage, RST VCC 5% Trip Point (Reset Threshold Voltage) VCC 10% Trip Point (Reset Threshold Voltage) Input Capacitance, ST, TOL Output Capacitance, RST, RST IIL ISOURCE = 350A, VCC = 3.3V ISINK = 10mA, VCC = 3.3V VCC = 1.4V, ISINK = 50A TOL = Gnd TOL = VCC CIN (See Note 5) COUT (See Note 5) 2.80 2.47 2.88 2.55 2.4 0.4 0.3 2.97 2.64 5 7 2.0 VCC - 0.4 -0.3 18 15 Min Typ Max 5.5 30 25 VCC + 0.3 VCC + 0.3 0.5 1 Units V A A V V
ST and PBRST Input Levels
A V V V V V pF pF
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MIC1832 P Supervisory Circuit
A.C. Electrical Characteristics
VCC = 3 to 5.5 V, TA = Operating Temperature Range, unless otherwise noted. Parameter PBRST Min. Pulse Width, tPB PBRST Delay, tPBD Reset Active Time, tRST ST Pulse Width, tST ST Timeout Period, tTD TD = 0V TD = Open TD = VCC Conditions PBRST = VIL (see note 6) Min 20 1 250 20 62.5 250 500 40 0 VCC Falling (see note 7) VCC Rising 250 5 8 150 600 1200 250 1000 2000 4 610 20 1000 Typ Max Units ms ms ms ns ms
VCC Fall Time, tF VCC Rise Time, tR VCC Detect to RST Low and RST High, tRPD VCC Detect to RST High and RST Low, tRPU Note Note Note Note Note Note Note 1: 2: 3: 4: 5: 6: 7:
s ns s ms
610
1000
ICC is measured with PBRST and all outputs open and inputs within 0.5V of supply rails. Measured with VCC 2.7V. Measured with VCC < 2.7V. PBRST has an internal pull-up resistor to VCC (typ. 40k). Guaranteed by design at TA = 25C. PBRST must be held low for a minimum of 20ms to guarantee a reset. VCC falling at 8.5mv/s.
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MIC1832 P Supervisory Circuit
Pin Functions
Pin 1: PBRST - Pushbutton reset input. This input is debounced and can be driven with external logic signals or by means of a mechanical pushbutton to actively force a reset. All pulses less than 1ms in duration on the PBRST pin are ignored, whereas, any pulse with a duration of 20ms or greater is guaranteed to cause a reset. PBRST has an internal pull-up resistor to VCC of 40k typical. Pin 2: TD - Time delay input. This input selects the timebase used by the watchdog timer. When TD = 0V, the watchdog timeout period is set to a nominal value of 150ms and when TD = open, the watchdog timeout period is set to a nominal value of 600ms and when TD = VCC, the watchdog timeout period is 1.2sec nominally. Pin 3: TOL - Tolerance select input. Selects whether 5% or 10% of VCC is used as the reset threshold voltage. When TOL = 0V, the 5% tolerance level is selected and when TOL = VCC, a 10% tolerance level is selected. Pin 4: GND - IC ground pin, 0V reference. Pin 5: RST - RST is asserted high if either VCC goes below the reset threshold, the watchdog times out or PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period after VCC exceeds the reset threshold or after the watchdog times out or after PBRST goes high. Pin 6: RST - RST is asserted low if either VCC goes below the reset threshold, the watchdog times out or PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period after VCC exceeds the reset threshold or after the watchdog times out or after PBRST goes high. Pin 7: ST - Input to the watchdog timer. If ST does not see a transition from high to low within the watchdog timeout period, RST and RST will be asserted. Pin 8: VCC - Primary supply input.
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MIC1832 P Supervisory Circuit
Block Diagram
VCC (8)
TRIP POINT SELECT
+
RESET
TOL (3) REF
GENERATOR
RST (6)
PBRST (1)
MANUAL RESET DEBOUNCE
RST (5)
ST (7)
WATCHDOG TIMER TIMEOUT SELECT GND (4)
TD (2)
Circuit Description
TD Pin Gnd Open VCC
Min. 62.5ms 250ms 500ms
tTD Typ.
150ms 600ms 1200ms
Max. 250ms 1000ms 2000ms
Table 1. Watchdog Timeout Period
5
MIC1832 P Supervisory Circuit
Circuit Description
Power Monitor The RST and RST pins are asserted whenever VCC falls below the reset threshold voltage as determined by the TOL pin. A 5% tolerance level (2.88V reset threshold voltage) can be selected by connecting the TOL pin to ground and a 10% tolerance (2.55V reset threshold voltage) can be selected by connecting the TOL pin to VCC. The reset pins will remain asserted for a period of 250ms after VCC has risen above the reset threshold voltage. The reset function ensures the microprocessor is properly reset and powers up into a known condition after a power failure. RST will remain valid with VCC as low as 1.4V.
8++ 456 456
8++62 J42,
8++62
J427
Figure 1. Power-Up/Power-Down Sequence
J56 56 J6,
Note: The maximum time between high-to-low transitions (tTD) on the watchdog input (ST) is determined by the voltage applied to the TD pin. If the watchdog input sees a high-to-low transition prior to the timeout period, the watchdog timer will be reset.
Figure 2. Watchdog Input
Watchdog Timer The microprocessor can be monitored by connecting the ST pin (watchdog input) to a bus line or I/O line. If a high-to-low transition doesn't occur on the ST pin within the watchdog timeout period (determined by TD pin, see Table 1), the RST and RST pins will be asserted resulting in a microprocessor reset. RST and RST will remain asserted for at least 250ms when this occurs. A minimum pulse of 75ns or any transition high-to-low on the ST pin will reset the watchdog timer. The watchdog timer will be reset if ST sees a valid transition within the watchdog timeout period.
tPB
Pushbutton Reset Input The PBRST input can be driven with a manual pushbutton switch or with external logic signals. The input is internally debounced and requires an active low signal to force the reset outputs into their active states. The PBRST input will recognize any pulse that is 20ms in duration or greater and will ignore all pulses that are less than 1ms in duration.
tPDLY PBRST RST RST tRST
Figure 3. Pushbutton Reset
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MIC1832 P Supervisory Circuit
Alternate Source Cross Reference Guide
MIC Direct Replacement MIC1832NC MIC1832MC
Industry P/N DS1832 DS1832S
7
MIC1832 P Supervisory Circuit
Packaging Information
M Package, 8-Pin Small Outline
0.197 0.190
Pin 1 Identifier
0.155 0.150
0.244 0.228
0.069 0.053 0.060 0.019 0.013 0.040 0.011 0.004
0.012 0.009 0-81/4
0.050 0.016
N Package, 8-Pin Plastic Dual-In-Line
0.400 0.370
0.260 0.240
0.310 0.290 0.150 0.120
0.035 0.015 0.150 0.125 0.110 0.090
0.023 0.015
0.370 0.300
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