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| 64-Bit TX System RISC Family The TX49 Family of RISC microprocessors for embedded use is an original Toshiba 64-bit processor family and is based on the RISC architecture designed by the MIPS Group in the U.S.A. The TX49 Family processors can also be used as ASSPs or as the CPU core for gate arrays and cell-based ICs, allowing you to attain a higher level of integration in your system than has ever been possible before. 64-bit RISC architecture 64-bit operation Thirty-two 64-bit general-purpose registers Optimized 5-stage pipelining Upward-compatible instruction set including MIPS I, MIPS II and MIPS III instruction set architectures (ISAs) s Built-in high-capacity primary cache Instruction cache: 8/16/32 KB (selectable) s s 4-way set-associative Supports lock function. Data cache: 8/16/32 KB (selectable) 4-way set-associative Supports lock function. s Write-back/write-through (every page) s Supports snoop function. s s Multiply/add instructions and debugging instructions added Built-in 48 double entry TLB Useful as CPU core for gate arrays / cell-based ICs TX49/H: TC240C process technology TX49: TC220C process technology Low power consumption design Low power consumption modes (Doze/Halt) Supply voltage: 3.3 V s Numerous optional functions Debug support unit Supports EJTAG. Single- or double-precision floating-point unit s TX49 processor block diagram Integer Arithmetic Unit 64-Bit General-purpose Registers Pipeline Control System Control Coprocessor Coprocessor Register Floating-Point Coprocessor (optional) Integer Data Path Memory Management Unit (MMU) 48 Double Entry TLB 32-Bit Single-/Double-Precision Floating-Point General-Purpose Register Multiply / Add Arithmetic Unit Exception Handling Unit Floating-Point Data Path 8-/16-/32-KB Instruction Cache (4-way set-associative) Cache Controller 8-/16-/32-KB Data Cache (4-way set-associative) Write Buffer 14 General-purpose MPU TMPR4901F-133 The TMPR4901F is the first product in the TX49 Family. Built around the TX49 processor core, it incorporates a clock generator and a debug support unit. This microprocessor is not just a general-purpose MPU; it can also be used to verify functions and evaluate device performance during the development of ASICs which feature the TX49 processor core. Under development s 64-bit general-purpose RISC microprocessor based on the TX49 processor core q TX49 processor core q Instruction cache: 16 Kbytes built in q Data cache: 16 Kbytes built in q Separate 36-bit address bus and 64-bit data bus q Clock generator with 16 PLL q Low power consumption modes (Doze/Halt) q Built-in debug support unit s TMPR4901F block diagram PLL TX49 Processor Core Data Cache Bus Interface Unit (16 Kbytes) q Maximum internal operating frequency: 133 MHz q Maximum external operating frequency: 66 MHz q Supply voltage: 3.3 V q Package: 208-pin QFP Instruction Cache (16 Kbytes) Debug Support Unit Write Buffer s System block diagram 64-bit data bus Memory Controller 36-bit address bus ROM DRAM I/O Controller TMPR4901F s Target applications Office equipment Laserprinters 4215/MRP Home electronics DVD players Network equipment & peripherals Set-top boxes Networks Digital PPCs Game machines 15 Floating-point unit built-in TMPR4955F-167/4955F-200 The TMPR4955F is built around a TX49/H processor core with improved cache size and operating frequency. Incorporating a floating-point unit (FPU) and a 32-bit SysAD interface, the TMPR4955F is ideal for a wide range of applications, including laser beam printers (LBPs), network equipment and set-top boxes (STBs). In addition, a built-in debug support unit (DSU) allows smooth debugging. TX49/H Processor Core Integer Arithmetic Unit 64-Bit GeneralPurpose Registers Under development s 64-bit general-purpose RISC microcomputer with floating-point unit q TX49/H 64-bit RISC core q Five-stage pipeline q On-chip caching 4-way set-associative caches Instruction cache: 32 KB built in Data cache: 32 KB built in Cache lock function q Prefetch instruction Clock Generator q 48 double entry TLB q 32-bit system interface bus (SysAD bus) q Single-/Double-precision FPU q Low power consumption mode q Supply voltage Internal: 2.5 V External: 3.3 V q Built-in debug support unit (DSU) q Maximum operating frequency: 167 MHz / 200 MHz Write Buffer System Control Processor Coprocessor Registers Memory Management Unit (MMU) 48 Double Entry TLB Exception Handling Unit Floating-Point Unit Coprocessor Floating-Point Unit Registers Sync. Circuit Pipeline Integer Arithmetic Data Path Control Debug Support Unit (EJTAG) Multiply/ Add Arithmetic Unit Floating-Point Unit Data Path 32-Bit SysAD Bus Interface 32-KB 4-Way Set-Associative Instruction Cache Cache Controller 32-KB 4-Way Set-Associative Data Cache q Package: 160-pin QFP Floating-point unit built-in TMPR4956F-167/4956F-200 The TMPR4956F 64-bit microcomputer is the SysAD busextended version of the TMPR4955F. The TMPR4956F incorporates a floating-point unit (FPU) as well as a TX49/H processor core, and is ideal for a wide range of applications including laser beam printers (LBPs), network equipment and set-top boxes (STBs). In addition, a built-in debug support unit (DSU) allows smooth debugging. Clock Generator Under development s SysAD bus-extended 64-bit RISC microcomputer with floating-point unit q TX49/H 64-bit RISC core q Five-stage pipeline q On-chip caching 4-way set-associative caches Instruction cache: 32 KB built in Data cache: 32 KB built in Cache lock function q Prefetch instruction TX49/H Processor Core Memory Integer Arithmetic Unit 64-Bit GeneralPurpose Registers q 48 double entry TLB q 64-bit system interface bus (SysAD bus) q Single-/Double-precision FPU q Low power consumption mode q Supply voltage Internal: 2.5 V External: 3.3 V q Built-in debug support unit (DSU) q Maximum operating frequency: 167 MHz / 200 MHz System Control Processor Coprocessor Registers Memory Management Unit (MMU) 48 Double Entry TLB Exception Handling Unit Floating-Point Unit Coprocessor Floating-Point Unit Registers Sync. Circuit Pipeline Integer Arithmetic Data Path Control Debug Support Unit (EJTAG) Multiply/ Add Arithmetic Unit Floating-Point Unit Data Path 64-Bit SysAD Bus Interface 32-KB 4-Way Set-Associative Instruction Cache Cache Controller 32-KB 4-Way Set-Associative Data Cache Write Buffer q Package: 208-pin QFP 16 64-Bit TX System RISC Series 64-bit superscalar RISC processors for workstations and servers Compatible with the R10000 RISC processors available from MIPS Technologies, Inc. 64-bit superscalar architecture Capable of operating at 200 MHz Built-in 32-Kbyte instruction and data caches Product No. Internal Frequency Supply Voltage Package Features Superscalar architecture Built-in primary cache memory (64 KB) Built-in secondary cache memory controller TC86R10000 200 MHz 3.3 V LGA 599 64-Bit TX System RISC Series The TX44 Series is comprised of 64-bit RISC microprocessors that are compatible with the R4000/R4400 microprocessors from MIPS Technologies, Inc. The microprocessors in this series are suited to a wide variety of applications, ranging from personal computers to high-end workstations. In addition to the internal operating frequency of 200 MHz, 8-stage superpipeline and 32 Kbytes of primary cache memory, the microprocessors in this series contain an FPU based on the ANSI/IEEE-754-1985 standard, enhancing their integer and floating-point arithmetic capability. Integer arithmetic performance: 141 SPECint92 (at 200 MHz) Floating-point arithmetic performance: 143 SPECfp92 (at 200 MHz) 8-stage super-pipeline Product No. Internal Frequency 200 MHz 200 MHz 150 MHz Supply Voltage 3.3 V 3.3 V 3.3 V Built-in secondary cache memory controller Multiprocessing capability Package: 447-pin PGA Operating Temperature Range 0 to 70C 0 to 85C 0 to 85C Package PGA447 PGA447 PGA447 TC86R4400 - 200 (L) TC86R4400 - 200 (SB) TC86R4400 - 150 (S) 64-Bit TX System RISC Series Product No. Internal Frequency 100 MHz Supply Voltage 3.3 V Operating Temperature Range 0 to 85C Package QFP120 17 TC86R4300F - 100 |
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