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HCTS161AMS
September 1995
Radiation Hardened Synchronous Counter
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW
MR CP P0 P1 P2 P3 PE GND 1 2 3 4 5 6 7 8 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 TE 9 SPE
Features
* 3 Micron Radiation Hardened CMOS SOS * Total Dose 200K RAD (Si) * Minimum LET for SEU Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ) * Dose Rate Survivability: >1 x 1012 RAD (Si)/s * Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse * Latch-Up Free Under Any Conditions * Military Temperature Range: -55oC to +125oC * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * Input Logic Levels -VIL = 0.8V Max -VIH = VCC/2V Min * Input Current Levels Ii 5A at VOL, VOH
Description
The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous counter features asynchronous reset and look-ahead carry logic. The HCTS161AMS has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (P0 - P3) to load the counter. The data is latched to the outputs on the positive edge of the clock input, CP. The HCTS161AMS has two count enable pins, PE and TE. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count. The HCTS161AMS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS161AMS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW
MR CP P0 P1 P2 P3 PE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 TE SPE
Ordering Information
PART NUMBER HCTS161ADMSR HCTS161AKMSR HCTS161AD/Sample HCTS161AK/Sample HCTS161AHMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 16 Lead SBDIP 16 Lead Ceramic Flatpack 16 Lead SBDIP 16 Lead Ceramic Flatpack Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518888 2144.2
Specifications HCTS161AMS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . .100ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V , (Note 2) VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 2.25V, IOL = 50A, VIL = 0.8V VCC = 5.5V, VIH = 2.75V, IOL = 50A, VIL = 0.8V Output Voltage High VOH VCC = 4.5V, VIH = 2.25V, IOH = -50A, VIL = 0.8V VCC = 5.5V, VIH = 2.75V, IOH = -50A, VIL = 0.8V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MIN 4.8 4.0 -4.8 -4.0 MAX 40 750 0.1 UNITS A A mA mA mA mA V
PARAMETER Supply Current
SYMBOL ICC
(NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND
Output Current (Source)
IOH
Output Voltage Low
VOL
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1 VCC -0.1 -
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
V
1 2, 3
+25oC +125oC, -55oC +25oC, +125oC, -55oC
0.5 5.0 -
A A V
Noise Immunity Functional Test NOTES:
FN
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, (Note 3)
7, 8A, 8B
1. All voltages reference to device GND. 2. Force/measure functions may be interchanged. 3. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 2
518888
Specifications HCTS161AMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MAX 27 29 27 29 28 31 29 33 20 21 25 29 38 45 44 51 ns ns ns ns UNITS ns ns ns ns ns ns ns ns ns ns
PARAMETER Propagation Delay CP to Qn
SYMBOL TPLH1
(NOTES 1, 2) CONDITIONS VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V
TPHL1
Propagation Delay CP to TC
TPLH2
TPHL2
Propagation Delay TE to TC
TPLH3
TPHL3
Propagation Delay MR to Q Propagation Delay MR to TC NOTES:
TPHL4
TPHL5
1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) CONDITIONS VCC = 5.0V, VIH = 5.0, VIL = 0.0V, f = 1MHz VCC = 5.0V, VIH = 5.0, VIL = 0.0V, f = 1MHz VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, LIMITS TEMPERATURE +25oC +125oC, -55oC MIN 16 24 20 30 10 15 13 20 12 18 5 5 MAX 231 285 10 10 UNITS pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER Capacitance Power Dissipation Input Capacitance
SYMBOL CPD
CIN
+25oC +125oC, -55oC
Pulse Width Time CP
TW
+25oC +125oC, -55oC
Pulse Width Time MR
TW
+25oC +125oC, -55oC
Setup Time Pn to CP
TSU
+25oC +125oC, -55oC
Setup Time PE to CP or TE
TSU
+25oC +125oC, -55oC
Setup Time SPE to CP
TSU
+25oC +125oC, -55oC
Hold Time Pn to CP
TSU
+25oC +125oC, -55oC
Spec Number 3
518888
Specifications HCTS161AMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) (NOTE 1) CONDITIONS VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, VCC = 4.5V, VIH = 4.5, VIL = 0.0V, LIMITS TEMPERATURE +25oC +125oC, -55oC C MIN 3 3 3 3 15
o
PARAMETER Hold Time TE or PE to CP
SYMBOL TSU
MAX 30 20
UNITS ns ns ns ns ns ns MHz MHz
Hold Time SPE to CP
TSU
+25o +125oC,
-55oC
Recovery Time
TREC
+25 C +125 C, -55 C +25oC +125o C, -55 C
o o
o
22 0 0
Maximum Frequency
FMAX
NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 4.0 -4.0 VCC -0.1 VCC -0.1 2 2 2 2 2 2 2 2 MAX 0.75 0.1 0.1 UNITS mA mA mA V V V
PARAMETER Supply Current Output Current (Sink) Output Current (Source) Output Voltage Low
SYMBOL ICC IOL IOH VOL
(NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 4.5, VIL = 0V, VOUT = 0.4V VCC = 4.5V, VIH = 4.5, VIL = 0V, VOUT = VCC -0.4V VCC = 4.5V, VIH = 2.25V, VIL = 0.8V , IOL = 50A VCC = 5.5V, VIH = 2.75V, VIL = 0.8V , IOL = 50A
Output Voltage High
VOH
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, IOH = -50A VCC = 5.5V, VIH = 2.75V, VIL = 0.8V, IOH = -50A
5 29 29 33 31 29 21 45 51
V A V ns ns ns ns ns ns ns ns
Input Leakage Current Noise Immunity Functional Test Propagation Delay CP to Qn Propagation Delay CP to TC Propagation Delay TE to TC Propagation Delay MR to Q Propagation Delay MR to TC NOTES:
IIN FN TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 TPHL5
VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 2.25V, VIL = 0.8V , (Note 2) VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V
1. All voltages referenced to device GND. 2. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 4
518888
Specifications HCTS161AMS
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP 5 5
PARAMETER ICC IOL/IOH
DELTA LIMIT 12A -15% of 0 Hour
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. METHOD 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 Sample/5005 Sample/5005 Sample/5005 Sample/5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11 ICC, IOL/H READ AND RECORD ICC, IOL/H ICC, IOL/H ICC, IOL/H
TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. METHOD 5005 PRE RAD 1, 7, 9 POST RAD Table 4 READ AND RECORD PRE RAD 1, 9 POST RAD Table 4 (Note 1)
Spec Number 5
518888
HCTS161AMS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V 50kHz 25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 1) 11 - 15 1 - 10 16 -
STATIC BURN-IN II TEST CONNECTIONS (Note 1) 11 - 15 8 1 - 7, 9, 10, 16 -
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) NOTES: 1. Each pin except VCC and GND will have a resistor of 10k 5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 1k 5% for dynamic burn-in 4, 6, 8 11 - 15 1, 3, 5, 7, 9, 10, 16 2 -
TABLE 9. IRRADIATION TEST CONNECTIONS OPEN 11 - 15 GROUND 8 VCC = 5V 0.5V 1 - 7, 9, 10, 16
NOTE: Each pin except VCC and GND will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 6
518888
HCTS161AMS Intersil Space Level Product Flow - `MS'
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5)
NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 7
518888
HCTS161AMS Propagation Delay Timing Diagram
VIH VS VSS TPLH TPHL VOH VS VOL OUTPUT CL = 50pF RL = 500 INPUT CL RL
Propagation Delay Load Circuit
DUT TEST POINT
AC VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCTS 4.50 3.00 1.30 0 0 UNITS V V V V V
Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger
INPUT VIH VS VIL TH TSU INPUT CP VIH VS VIL TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH TW TW
AC Load Circuit
DUT TEST POINT CL RL
CL = 50pF RL = 500
VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCTS 4.50 3.00 1.30 0 0 UNITS V V V V V
Spec Number 8
518888
HCTS161AMS Die Characteristics
DIE DIMENSIONS: 86 x 104mils 2.19 x 2.65mm METALLIZATION: Type: AlSi Metal Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 x 4 mils
Metallization Mask Layout
HCTS161AMS
CP (2) MR (1) VCC (16)
(15) TC P0 (3)
(14) Q0 P1 (4)
(13) Q1
P2 (5)
(12) Q2 P3 (6)
(11) Q3
PE (7)
(8) GND
(9) SPE
(10) TE
NOTE: The die diagram is a generic plot form a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS161A is TA14446A.
Spec Number 9
518888

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