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Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
FEATURES
* 2 differential 2.5V/3.3V LVPECL / ECL outputs * 1 CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 1GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 15ps (maximum) * Part-to-part skew: 100ps (maximum) * Propagation delay: 1.4ns (maximum) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS85311 is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V ECL/ HiPerClockSTM LVPECL Fanout Buffer and a member of the HiPerClockSTM family of High Perfor mance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.T h e ICS85311 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par tto-par t skew characteristics make the ICS85311 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
CLK nCLK Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 Vcc CLK nCLK VEE
ICS85311
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Type Output Output Power Input Input Power Pullup Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Inver ting differential clock input. Positive supply pin. Pulldown Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 VEE nCLK CLK VCC
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 112C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VCC VCC IEE Parameter Positive Supply Voltage Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 25 Units V V mA
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol IIH IIL V PP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V or 2.625V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2625V, VIN = 0V VCC = 3.465V or 2.625V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltag for CLK, nCLK is VCC + 0.3V.
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.65 Typical Maximum VCC - 1.0 VCC - 1.7 0.9 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Test Conditions 1GHz Minimum 0.9 Typical Maximum 1 1.4 15 100 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 700 700 52 Units GHz ns ps ps ps ps %
TABLE 4. AC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol fMAX Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time
t PD tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle 48 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
2V
V CC
Qx
SCOPE
V CC
Qx
SCOPE
LVPECL
VEE
nQx
LVPECL
VEE
nQx
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
V CC
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx nCLK V CLK0
PP
Qx Cross Points V
CMR
nQy Qy
VEE
tsk(o)
DIFFERENTIAL INPUT LEVEL
PART 1 nQx
OUTPUT SKEW
80%
Qx PART 2 nQy Qy
tsk(pp)
80% VSW I N G
Clock Outputs
20% tR tF
20%
PART-TO-PART SKEW
nCLK
OUTPUT RISE/FALL TIME
nQx Qx
CLK0 nQ0, nQ1 Q0, Q1
tPD
Pulse Width t
PERIOD
odc =
t PW t PERIOD
PROPAGATION DELAY
ICS85311AM
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
ICS85311AM
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. B JUNE 17, 2004
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Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
VCC=2.5V
2.5V
VCC=2.5V
R1 250
Zo = 50 Ohm
R3 250
Zo = 50 Ohm
+
+
Zo = 50 Ohm
2,5V LVPECL Driv er
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
R2 62.5
R4 62.5
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85311. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85311 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.147W * 103.3C/W = 85.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE JA FOR 8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85311 is: 225
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ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Marking 85311AM 85311AM Package 8 lead SOIC 8 lead SOIC on Tape and Reel 8 lead "Lead Free" SOIC 8 lead "Lead Free" SOIC on Tape and Reel Count 96 per tube 2500 96 per tube 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85311AM ICS85311AMT ICS85311AMLF ICS85311AMLFT
85311AMLF 85311AMLF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS85311AM
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REV. B JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85311
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Added Termination for LVPECL Outputs section. 3.3V Output Load Test Circuit Diagram - corrected VEE equation to read -1.3V 0.165V from 0.135V. Updated Output Rise/Fall Time Diagram. Add Lead-Free bullet in Features section. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Outputs rating. Combined 3.3V & 2.5V Power tables and Differential DC Characteristics tables. Updated Parameter Measurement Information. Updated Single Ended Signal Driving Differential Input diagram. Added Termination for 2.5V LVPECL Output section. Added Differential Clock Input Interface section. Ordering Information table - added Lead Free par t number. Date 5/30/02 9/23/02
Rev A A
Table
Page 8 5 7 1 2 3 3 5 6 7 8 13
T2
B
6/17/04
T8
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