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FEATURES 44 V Supply Maximum Ratings V SS to VDD Analog Signal Range Low On Resistance (60 typ) Low Power Consumption (1.6 mW max) Low Charge Injection (<4 pC typ) Fast Switching Break-Before-Make Switching Action Plug-In Replacement for DG428/DG429 APPLICATIONS Automatic Test Equipment Data Acquisition Systems Communication Systems Avionics and Military Systems Microprocessor Controlled Analog Systems Medical Instrumentation
LC2MOS Latchable 4-/8-Channel High Performance Analog Multiplexers ADG428/ADG429
FUNCTIONAL BLOCK DIAGRAMS
ADG428
S1 S1A DA S4A D S1B DB S8 S4B
ADG429
DECODERS/DRIVERS LATCHES WR A2 A1 A0 EN RS WR
DECODERS/DRIVERS LATCHES RS A1 A0 EN
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG428 and ADG429 are monolithic CMOS analog multiplexers comprising eight single channels and four differential channels respectively. On-chip address and control latches facilitate microprocessor interfacing. The ADG428 switches one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1 and A2. The ADG429 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched OFF. All the control inputs, address and enable inputs are TTL compatible over the full specified operating temperature range. This makes the part suitable for bus-controlled systems such as data acquisition systems, process controls, avionics and ATEs because the TTLcompatible address latches simplify the digital interface design and reduce the board space required. The ADG428/ADG429 are designed on an enhanced LC2MOS process that provides low power dissipation yet gives high switching speed and low on resistance. Each channel conducts equally well in both directions when ON and has an input signal range that extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. All channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. The ADG428/ADG429 are improved replacements for the DG428/DG429 Analog Multiplexers. REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
1. Extended Signal Range The ADG428/ADG429 are fabricated on an enhanced LC2MOS process, giving an increased signal range that extends to the supply rails. 2. Low Power Dissipation 3. Low RON 4. Single/Dual Supply Operation 5. Single Supply Operation For applications where the analog signal is unipolar, the ADG428/ADG429 can be operated from a single rail power supply. The parts are fully specified with a single +12 V power supply and will remain functional with single supplies as low as +5 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADG428/ADG429-SPECIFICATIONS
DUAL SUPPLY1 (V
Parameter ANALOG SWITCH Analog Signal Range RON RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) ADG428 ADG429 Channel ON Leakage ID, IS (ON) ADG428 ADG429 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or I INH CIN, Digital Input Capacitance
DD
= +15 V, VSS = -15 V, GND = 0 V, WR = 0 V, RS = 2.4 V unless otherwise noted)
B Version -40 C to +25 C +85 C VSS to VDD 60 100 10 125 60 100 10 T Version -55 C to +25 C +125 C VSS to VDD 125
Units V typ max % max nA typ nA max nA typ nA max nA typ nA max nA max nA max V min V max A max pF typ ns typ ns max ns min ns typ ns max ns typ ns max ns min ns min ns min ns min pC typ dB typ dB min dB typ pF typ pF typ pF typ
Test Conditions/Comments
VD = 10 V, IS = -1 mA -10 V < VS < 10 V, IS = -1 mA VD = 10 V, VS = Test Circuit 2 VD = 10 V, VS = Test Circuit 3 10 V; 10 V;
0.03 0.3 0.5 50 0.07 1 0.05 1 1 1 0.7 100 0.5 50 100 50 2.4 0.8 0.1 8 1
0.03 0.3 0.5 50 0.07 1 0.05 1 1 1 0.7 100 0.5 50 100 50 2.4 0.8 0.1 8 110 250 1
VS = VD = 10 V; Test Circuit 4
VIN = 0 or VDD f = 1 MHz RL = 1 M, CL = 35 pF; VS1 = 10 V, VS8 = 10 V; Test Circuit 5 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 6 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 7 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 7
DYNAMIC CHARACTERISTICS2 tTRANSITION 110 250 tOPEN tON (EN, WR) tOFF (EN, RS) tW, Write Pulsewidth tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulsewidth Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) ADG428 ADG429 CD, CS (ON) ADG428 ADG429 POWER REQUIREMENTS IDD ISS 115 150 105 150
300 10 225 300 100 100 10 100
300 10
115 150 105 150
225 300 100 100 10 100
4 -75 -60 85 11 40 20 54 34 20 100 0.001 5
4 -75 -60 85 11 40 20 54 34 20 100 0.001 5
VS = +5 V VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 10 RL = 1 k, CL = 15 pF, f = 100 kHz; VS = 7 V rms, VEN = 0 V; Test Circuit 11 RL = 1 k, CL = 15 pF, f = 100 kHz; Test Circuit 12 f = 1 MHz f = 1 MHz f = 1 MHz
pF typ pF typ A typ A max A typ A max VIN = 0 V, VEN = 0 V
NOTES 1 Temperature ranges are as follows: B Version: -40C to +85C; T Version: -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-2-
REV. C
ADG428/ADG429 SINGLE
Parameter ANALOG SWITCH Analog Signal Range RON RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) ADG428 ADG429 Channel ON Leakage ID, IS (ON) ADG428 ADG429 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or I INH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS2 tTRANSITION tOPEN tON (EN, WR) tOFF (EN, RS) tW, Write Pulsewidth tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulsewidth Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) ADG428 ADG429 CD, CS (ON) ADG428 ADG429 POWER REQUIREMENTS IDD
SUPPLY1 (VDD = +12 V, VSS = 0 V, GND = 0 V, WR = 0 V, RS = 2.4 V unless otherwise noted)
B Version -40 C to +25 C +85 C 0 to VDD 90 200 10 0.005 0.5 50 0.015 1 100 0.008 1 50 0.02 1 0.01 1 100 50 2.4 0.8 1 8 250 350 25 200 300 80 300 8 250 350 25 200 300 80 300 10 0.005 0.5 0.015 1 0.008 1 0.02 1 0.01 1 90 200 T Version -55 C to +25 C +125 C 0 to VDD Units V typ max % max nA typ nA max nA typ nA max nA typ nA max nA typ nA max nA max nA max V min V max A max pF typ ns typ ns max ns min ns typ ns max ns typ ns max ns min ns min ns min ns min pC typ dB typ dB min dB typ pF typ pF typ pF typ f = 1 MHz 54 34 20 100 54 34 20 100 pF typ pF typ A typ A max VIN = 0 V, VEN = 0 V VIN = 0 or VDD f = 1 MHz RL = 1 M, CL = 35 pF; VS1 = 10 V/0 V, V S8 = 0 V/10 V; Test Circuit 5 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 6 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 7 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 7 Test Conditions/Comments
VD = +10 V, IS = -500 A 0 V < VS < 10 V, IS = -1 mA VD = 10 V/0 V, VS = 0 V/10 V; Test Circuit 2 VD = 10 V/0 V, VS = 0 V/10 V; Test Circuit 3
50 100 50 100 50 2.4 0.8 1
VS = VD = 10 V/0 V; Test Circuit 4
450 10 400 400 100 100 10 100
450 10 400 400 100 100 10 100
4 -75 -60 85 11 40 20
4 -75 -60 85 11 40 20
VS = +5 V VS = 6 V, RS = 0 , CL = 10 nF; Test Circuit 10 RL = 1 k, CL = 15 pF, f = 100 kHz; VS = 7 V rms, VEN = 0 V; Test Circuit 11 RL = 1 k, CL = 15 pF, f = 100 kHz; Test Circuit 12 f = 1 MHz f = 1 MHz
NOTES 1 Temperature ranges are as follows: B Version: -40C to +85C; T Version: -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
REV. C
-3-
ADG428/ADG429
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted.)
ADG428 PIN CONFIGURATIONS DIP/SOIC
A0 WR 1 A0
2 18 17 16
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -25 V Analog, Digital Inputs2 . . . . . . . . . . VSS - 2 V to V DD + 2 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 73C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300C Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C PLCC Package, Power Dissipation . . . . . . . . . . . . . . . 800 mW JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at A, EN, WR, RS, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.
PLCC
WR NC RS
20
RS A1 A2 GND EN 4 VSS 5 S1 6 S2 7 S3 8
3
2
1
A1
19 18 17 16 15 14
EN 3 VSS
4
PIN 1 IDENTIFIER
A2 GND VDD S5 S6
ADG428
15
ADG428
TOP VIEW (Not to Scale)
TOP VIEW 14 VDD (Not to Scale) 13 S5 6 S2 S3 7 S4 8 D9
12 11 10
S1 5
S6 S7 S8
9 10 11 12 13
S4
NC
S8 RS
20
NC = NO CONNECT
ADG429 PIN CONFIGURATIONS DIP
A0 WR 1 A0 2 EN 3 VSS 4 S1A 5
18 17 16
PLCC
WR NC RS A1 GND VDD EN 4 VSS 5 S1A 6 S2A 7 S3A 8
PIN 1 IDENTIFIER 18 17 16 15 14 9 10 11 12 13
3
2
1
A1
19
S7
D
GND VDD S1B S2B S3B
ADG429
15
ADG429
TOP VIEW (Not to Scale)
TOP VIEW 14 S1B (Not to Scale) 13 S2B S2A 6 S3A 7 S4A 8 DA 9
12 11 10
S3B S4B DB DA NC S4A DB S4B
NC = NO CONNECT
ORDERING GUIDE
Model1 ADG428BN ADG428BP ADG428BR ADG428TQ ADG429BN ADG429BP ADG429TQ
Temperature Range -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -55C to +125C
Package Options2 N-18 P-20A R-18 Q-18 N-18 P-20A Q-18
NOTES 1 For availability of MIL-STD-883, Class B processed parts, contact factory. 2 N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC (SOIC).
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG428/ADG429 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. C
ADG428/ADG429
TERMINOLOGY ADG428 Truth Table
VDD VSS
Most positive power supply potential. Most negative power supply potential in dual supplies. In single supply applications, it may be connected to ground. Ground (0 V) reference. Ohmic resistance between D and S. Difference between the RON of any two channels. Source leakage current when the switch is off. Drain leakage current when the switch is off. Channel leakage current when the switch is on. Analog voltage on terminals D, S. Channel input capacitance for "OFF" condition. Channel output capacitance for "OFF" condition. "ON" switch capacitance. Digital input capacitance. Delay time between the 50% and 90% points of the digital input and switch "ON" condition. Delay time between the 50% and 90% points of the digital input and switch "OFF" condition. Delay time between the 50% and 90% points of the digital inputs and the switch "ON" condition when switching from one address state to another. "OFF" time measured between 80% points of both switches when switching from one address state to another. Maximum input voltage for Logic "0." Minimum input voltage for Logic "1." Input current of the digital input. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. A measure of unwanted signal coupling through an "OFF" channel. A measure of the glitch impulse transferred from the digital input to the analog output during switching. Positive supply current. Negative supply current.
A2
A1
A0
EN
WR
RS
ON SWITCH
Latching X Reset X X X X X 0 NONE (Latches Cleared) X X X
g
1
GND RON RON IS (OFF) ID (OFF) ID, IS (ON) VD (VS ) CS (OFF) CD (OFF) CD, CS (ON) CIN tON (EN)
Maintains Previous Switch Condition
Transparent Operation X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 NONE 1 2 3 4 5 6 7 8
ADG429 Truth Table
A1
A0
EN
WR
RS
ON SWITCH PAIR
Latching X Reset X X X X 0 NONE (Latches Cleared) X X
tOFF (EN)
g
1
Maintains Previous Switch Condition
tTRANSITlON
Transparent Operation X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 NONE 1 2 3 4
tOPEN
VINL VINH IINL (IINH) Crosstalk
Off Isolation Charge Injection IDD ISS
REV. C
-5-
ADG428/ADG429
TIMING DIAGRAMS
3V 3V
WR
0V
50%
50%
RS
0V
50%
50%
tW tS
3V 2V
tRS tH
VO
tOFF (RS)
A0, A1, (A2) EN
0V
0.8V
SWITCH OUTPUT
0V
0.8VO
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff Time, tOFF, (RS). Note: All digital input signals rise and fall times are measured from 10% to 90% of 3 V. tr = tf = 20 ns.
Typical Characteristics
140 TA = +25 C 130 120 110 100
RON - 600 550 500 VDD = +5V VSS = 0V TA = +25 C
VDD = +5V VSS = -5V
450 400 350 RON - 300 250 200 150 100 50
90 80 VDD = +15V 70 VSS = -15V 60 50 40 -15 -10 -5 0 VD (VS) - Volts 5 10 15
VDD = +12V VSS = -12V
VDD = +10V VSS = -10V
VDD = +10V VSS = 0V VDD = +15V VSS = 0V
VDD = +12V VSS = 0V
0
0
3
6
9
12
15
VD (VS) - Volts
Figure 3. RON as a Function of VD (VS ): Dual Supply Voltage
Figure 5. R ON as a Function of VD (V S): Single Supply Voltage
80 75 70 VDD = +15V VSS = -15V
160 150 140 130 VDD = +12V VSS = 0V
65 RON - 60 55 50 +125 C +85 C RON -
120 +125 C 110 100 90 +25 C 80 +25 C 70 -10 -5 0 VD (VS) - Volts 5 10 15 60 0 2 4 6 VD (VS) - Volts 8 10 15 +85 C
45 40 -15
Figure 4. RON as a Function of VD (VS ) for Different Temperatures
Figure 6. R ON as a Function of VD (V S) for Different Temperatures
-6-
REV. C
ADG428/ADG429
6000 5500 5000 4500 4000 IDD - A ISS - A 3500 3000 2500 2000 1500 1000 500 0 10 100 1k 10k 100k SWITCHING FREQUENCY - Hz 1M 10M 0.1 10 100 1k 10k 100k SWITCHING FREQUENCY - Hz 1M 10M EN = 2.4V EN = 0V 1 100 VDD = +15V VSS = -15V 1000 VDD = +15V VSS = -15V
10 EN = 2.4V EN = 0V
Figure 7. Positive Supply Current vs. Switching Frequency
Figure 10. Negative Supply Current vs. Switching Frequency
130 120 110 100 t - ns 90 80 70 60 50 tOFF (EN) tON (EN) t - ns VDD = +15V VSS = -15V tTRANSITION
200 180 160 140 120 100 80 60 40 1 tOFF (EN) VDD = +12V VSS = 0V tTRANSITION
tON (EN)
1
3
5
7 9 VIN - Volts
11
13
15
3
5
7 VIN - Volts
9
11
13
Figure 8. Switching Time vs. V IN (Bipolar Supply)
Figure 11. Switching Time vs. VIN (Single Supply)
300 275 250 225 200 175 t - ns t - ns 150 125 100 75 50 25 0 5 7 11 VSUPPLY - Volts 9 13 15 tOFF (EN) tON (EN) tTRANSITION VIN = +5V
500 VIN = +5V 450 400 350 300 250 200 150 100 50 0 5 6 7 8 9 10 11 VSUPPLY - Volts 12 13 14 15 tOFF (EN) tON (EN)
tTRANSITION
Figure 9. Switching Time vs. Bipolar Supply
Figure 12. Switching Time vs. Single Supply
REV. C
-7-
ADG428/ADG429
100 95 90 85 OFF ISOLATION - dB 80 75 70 65 60 55 50 45 40 100 1k 10k 100k FREQUENCY - Hz 1M 10M CROSSTALK - dB VDD = +15V VSS = -15V 110 105 100 95 90 85 80 75 70 65 60 55 50 1k 10k 100k FREQUENCY - Hz 1M 10M VDD = +15V VSS = -15V
Figure 13. OFF Isolation vs. Frequency
Figure 15. Crosstalk vs. Frequency
0.2 VDD = +15V VSS = -15V TA = +25 C LEAKAGE CURRENT - nA 0.1 ID (ON) LEAKAGE CURRENT - nA
0.04 0.03 0.02 0.01 ID (OFF) 0 IS (OFF) -0.01 -0.02 -0.03 VDD = +12V VSS = 0V TA = +25 C
ID (ON)
IS (OFF) 0 ID (OFF)
-0.1 -15
-10
-5
0 VD (VS) - Volts
5
10
15
-0.04 0 2 4 6 VD (VS) - Volts 8 10 12
Figure 14. Leakage Currents as a Function of VD (V S)
Figure 16. Leakage Currents as a Function of VD (VS)
-8-
REV. C
ADG428/ADG429
TEST CIRCUITS
I DS VDD VSS
V1
S1 S2
VDD
VSS
D EN +0.8V VD A ID (OFF)
S VS RON = V1/I DS
D VS
S8 GND
Test Circuit 1. On Resistance
Test Circuit 3. I D (OFF)
VDD
VSS
VDD
VSS
S1 S2 S8 VS VD
VDD
VSS S1
VDD
VSS D A VD ID (ON)
IS (OFF)
A
D EN +0.8V VS S8 GND EN 2.4V
GND
Test Circuit 2. IS (OFF)
Test Circuit 4. I D (ON)
VDD 3V ENABLE DRIVE - VIN 0V VDD 50% 50% VIN 50 A0
VSS
VSS S1 VS1
A1 S2-S7 A2
tTRANSITION
tTRANSITION
90% 2.4V EN RS
ADG428*
S8 OUTPUT D GND WR 1M 35pF VS8
OUTPUT 90%
*SIMILAR CONNECTION FOR ADG429
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
VDD VSS
3V ADDRESS DRIVE - VIN 0V A0
VDD
VSS S1 VS
VIN
50
A1 S2-S7 A2
ADG428*
2.4V 80% OUTPUT GND WR 1k 35pF 80% EN RS S8 OUTPUT D
tOPEN
*SIMILAR CONNECTION FOR ADG429
Test Circuit 6. Break-Before-Make Delay, tOPEN
REV. C
-9-
ADG428/ADG429
VDD VSS 3V ENABLE DRIVE -VIN 0V 50% 50% A0 S1 A1 S2-S8 A2 VS VDD VSS
tON (EN)
VO OUTPUT (VO) 0V 0.9VO
tOFF (EN)
0.9VO VIN
ADG428*
2.4V RS D EN 50 GND 1k WR 35pF OUTPUT
*SIMILAR CONNECTION FOR ADG429
Test Circuit 7. Enable Delay, t ON (EN), t OFF (EN)
VDD 3V VDD WR 0V 50% A0 A1 A2
VSS
VSS S1 S2-S8 VS
VO OUTPUT 0V
tON (WR)
2.4V
EN RS WR
ADG428*
OUTPUT D 1k GND 35pF
0.2VO VRS VWR
*SIMILAR CONNECTION FOR ADG429
Test Circuit 8. Write Turn-On Time, tON (WR)
VDD 3V RS 0V A0 50% A1 A2
VSS
VDD
VSS S1 S2-S8 VS
tOFF (RS)
VO 0.8VO OUTPUT VIN 0V
ADG428*
2.4V EN D RS GND WR 1k 35pF OUTPUT
*SIMILAR CONNECTION FOR ADG429
Test Circuit 9. Reset Turn-Off Time, tOFF (RS)
-10-
REV. C
ADG428/ADG429
VDD VSS 3V EN A0 A1 A2 S VOUT QINJ = CL VOUT VIN VOUT VS RS EN GND WR VDD VSS RS 2.4V
ADG428*
D VOUT CL 10nF
*SIMILAR CONNECTION FOR ADG429
Test Circuit 10. Charge Injection
VDD
VSS
VDD
VSS
VDD A0 A1 A2
VSS RS A0 2.4V A1 A2 S1 D 1k VOUT 1k S2 S8
VDD
VSS EN RS 2.4V
ADG428
S1 S8 0V EN GND WR
ADG428
D 1k VOUT
VS
VS
GND
WR
Test Circuit 11. OFF Isolation
Test Circuit 12. Crosstalk
REV. C
-11-
ADG428/ADG429
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
PLCC (P-20A)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
18
Cerdip (Q-18)
10
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
0.310 (7.87) 0.220 (5.59)
1 9
3 4
19 18 PIN 1 IDENTIFIER
PIN 1 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.022 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.78) SEATING 0.030 (0.76) PLANE
0.320 (8.13) 0.290 (7.37)
TOP VIEW
(PINS DOWN) 8 9 14 13
0.050 (1.27) BSC
0.020 (0.50) R
0.015 (0.381) 0.008 (0.204)
0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78)
Plastic DIP (N-18)
0.910 (23.12) 0.890 (22.61)
18 1 10 9
SOIC (R-18)
0.4625 (11.75) 0.4469 (11.35)
PIN 1 0.180 (4.48) MAX 0.175 (4.45) 0.120 (3.05) 0.020 (0.508) 0.105 (2.67) 0.065 (1.66) SEATING PLANE 0.015 (0.381) 0.095 (2.42) 0.045 (1.15)
0.306 (7.78) 0.294 (7.47) 0.140 (3.56) 0.120 (3.05)
1
9
0.120 (0.305) 0.008 (0.203)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.260 (6.61) 0.240 (6.10)
18
10
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
8 0.0500 0.0192 (0.49) 0 (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-12-
REV. C
PRINTED IN U.S.A.
C1825c-0-5/99

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