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CXG1117K
Power Amplifier Module for JCDMA
Description The CXG1117K is the power amplifier module which operates at a single power supply. This IC is designed using the Sony's original p-Gate HFET process. Features * Single power supply operation: VDD1 = VDD2 = 3.5V (High mode), 1.7V (Low mode), VGG = 2.95V * Ultrasmall package: 0.065cc (6.2mm x 6.2mm x 1.7mm) * High efficiency: add = 36.5% (@900MHz, POUT = 27.5dBm) * Output power (high/low mode switching supported): POUT 19dBm: Low mode (VDD1 = VDD2 = 1.7V) POUT = 19 to 27.5dBm: High mode (VDD1 = VDD2 = 3.5V) * Gain: Gp = 26dB (@900MHz) Applications Power amplifier for JCDMA system cellular phones Structure p-Gate HFET module Recommended Operating Conditions VDD = 3.3 to 4.2V (High Mode) 1.7V (Low Mode) VGG = 2.95V1% Absolute Maximum Ratings * Operating case temperature * Storage temperature * Bias voltage * Bias voltage * Input power 8 pin LCC (Ceramic)
Tcase Tstg VDD1, VDD2 VGG PIN
-30 to +85 -30 to +125
C C
6 V 3.3 V (VDD1 = VDD2 = 3.5V) 8 dBm
GaAs module is ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E01304A25-PS
CXG1117K
package Outline/Pin Configuration Front
7 GND
PIN
1
6
VGG
VDD1
2
5
GND
VDD2
3
4
POUT
8
GND
Back
7 GND
VGG
6
1
PIN
GND
5
9
GND
2
VDD1
POUT
4
3
VDD2
8
GND
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CXG1117K
Electrical Characteristics Item Frequency Current consumption 1 Current consumption 2 Gain ACPR1 (High mode) ACPR2 (High mode) ACPR1 (Low mode) ACPR2 (Low mode) 2nd, 3rd harmonics Input VSWR Gate current Gain deviation for bias variation Gain deviation within band
(ZS = ZL = 50, IS-95 Modulation, Ta = 25C) Conditions POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V POUT = 14dBm, VDD = 1.7V, VGG = 2.95V POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V, 900kHz offset, 30kHz band width POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V, 1.98MHz offset, 30kHz band width POUT = 19dBm, VDD = 1.7V, VGG = 2.95V, 900kHz offset, 30kHz band width POUT = 19dBm, VDD = 1.7V, VGG = 2.95V, 1.98MHz offset, 30kHz band width POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V VDD = 3.5V, VGG = 2.95V VGG = 2.95V, POUT 27.5dBm VDD = 3.5V 1.7V VGG = 2.95V, POUT = 17dBm POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V 24 Min. 887 440 105 26 -51 -59 -53 -60 -40 1.3 2.5 3 1.2 -45 -56 -45 -56 -30 2.5 5 4.5 2 mA dB dB Typ. Max. Unit 925 MHz 475 125 mA mA dB dBc dBc dBc dBc dBc
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CXG1117K
Recommended External Circuit
C1: 0.1F C2: 1F C3: 10F R: 5.1 L: 6.8nH
GND
R PIN
L VGG C1 C2 C3
VDD1 C3 C2 C1 GND VDD2 C3 C2 C1 GND
POUT
GND
Recommended Evaluation Board Board material: Glass fabric-base epoxy Size: 40mm x 50mm x 0.6mm Relative dielectric constant: 4.6 Front
VGG GND
C3
Back
GND
PIN
C1 C2
RL
C2 C1 C1 C2
POUT
VDD1
C3 C3
GND VDD2
GND
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CXG1117K
Example of Representative Characteristics Conditions: f = 900MHz VDD1 = VDD2 = 3.5V, VGG = 2.95V Ta = 25C
POUT vs. PIN
34 32 30 28 26
POUT [dBm]
24 22 20 18 16 14 12 10 8 6 -18 -16-14 -12 -10 -8 -6 -4 -2 0 PIN [dBm] 2 46 8 10
IDD vs. POUT
650 600 550 500 450 350 300 250 200 150 100 50 0 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm]
Gain [dB]
Gain vs. POUT
28.0 27.5 27.0 26.5 26.0 25.5 25.0 24.5 24.0 23.5 23.0 22.5 22.0 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm]
400
IDD [mA]
ACPR1 vs. POUT
-34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -56 -58 -60 -62 -64
ACPR2 [dBc]
ACPR2 vs. POUT
ACPR1 [dBc]
-66 -68 -70 -72 -74 -76 -78
8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm]
-80
8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm]
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CXG1117K
Package Outline
Unit: mm
8PIN LCC (Ceramic)
6.2 0.3 6.0 SOLDERING POINT 1.9MAX
PIN 1 INDEX YY
SOLDERING POINT
6.7MAX
C0.1 0.15 3.8 1.6 0.9 1.7 8 3 0.15 DETAIL X X
R0.2 0.6 0.2
4 5 6
0.015MAX
DETAIL Y-Y
2 1
1.7 0.1
3.4 0.15 5.3
S
5.8
0.1
COAT
R0.2
TERMINAL
0.2
7
PACKAGE STRUCTURE
Dimension " "dose not inculude cutting burr.
SONY CODE EIAJ CODE JEDEC CODE LCC-8C-601 PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS CERAMIC SUBSTRATE GOLD PLATING NICKEL PLATING 0.8g
1.1 0.2
0.1 S
0.15
COAT TERMINAL
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Sony Corporation

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