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1CY M14 81
fax id: 2006
CYM1471 CYM1481
1024K x 8 SRAM Module 2048K x 8 SRAM Module
Features
* High-density 8-/16-megabit SRAM modules * High-speed CMOS SRAMs -- Access time of 70 ns * Low active power -- 605 mW (max.), 2M x 8 * Double-sided SMD technology * TTL-compatible inputs and outputs * Small footprint SIP -- PCB layout area of 0.72 sq. in. * 2V data retention (L version) are constructed from eight (1471) or sixteen (1481) 128K x 8 SRAMs in plastic surface-mount packages on an epoxy laminate board with pins. On-board decoding selects one of the SRAMs from the high-order address lines, keeping the remaining devices in standby mode for minimum power consumption. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When MS and WE inputs are both LOW, data on the eight data input/output pins is written into the memory location specified on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs MS and OE active LOW while WE remains inactive or HIGH. Under these conditions, the content of the location addressed by the information on the address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Functional Description
The CYM1471 and CYM1481 are high-performance 8-megabit and 16-megabit static RAM modules organized as 1024K words (1471) or 2048K words (1481) by 8 bits. These modules
Logic Block Diagram
A0-A 16
Pin Configuration SIP
A19 VCC WE I/O2 I/O3 I/O0 A1 A2 A3 A4 GND I/O5 A10 A11 A5 A13 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1471-2
Top View
17 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM
OE WE A 17-A 20 CYM1471
4 1 of 8 DECODER 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM
MS
A20 (1481) 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM MS (1471)
1 of 8 DECODER
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
8 1471-1
MS A15 A16 A12 A18 A6 I/O1 GND A0 A7 A8 A9 I/O7 I/O4 I/O6 A17 I/O0-I/O 7 VCC OE
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Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 October 1990 - Revised January 2, 1997
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CYM1471 CYM1481
Selection Guide
CYM1471 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 70 95 32 85 95 32 100 95 32 120 95 32 70 110 64 CYM1481 85 110 64 100 110 64 120 110 64
Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied................................................... 0C to +70C Supply Voltage to Ground Potential ............... -0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.3V to +7.0V Range Commercial DC Input Voltage ............................................-0.3V to +7.0V Output Current into Outputs (LOW)............................. 20 mA
Operating Range
Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
1471 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic MS Power-Down Current Automatic MS Power-Down Current GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., MS < VIL, IOUT = 0 mA Max. VCC, MS > VIH, Min. Duty Cycle = 100% Max. VCC, MS > VCC - 0.2V, VIN > VCC - 0.2V, or VIN < 0.2V Standard L Version -100, -120 L Version -85 Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.0 mA 2.2 -0.3 -20 -20 Min. 2.4 0.4 VCC + 0.3 0.8 +20 +20 95 32 16 250 800 2.2 -0.3 -20 -20 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +20 +20 110 64 32 500 1600 1481 Max. Unit V V V V A A mA mA mA A A
Capacitance[1]
Parameter CINA CINB COUT Description Input Capacitance (A0-16, OE, WE) Input Capacitance (A17-20, MS) Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V CYM1471 Max. 75 25 95 CYM1481 Max. 125 25 165 Unit pF pF pF
Note: 1. Tested on a sample basis.
2
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CYM1471 CYM1481
AC Test Loads and Waveforms
R1 2530 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 2830 R2 2830 R1 2530 3.0V 90% 5 pF GND < 10 ns 10% 90% 10% < 10 ns ALL INPUT PULSES
INCLUDING JIG AND SCOPE
(a)
Equivalent to: OUTPUT
1471-5
(b)
1471-3
1471-4
THEVENIN EQUIVALENT 1340 2.64V
Switching Characteristics Over the Operating Range[2]
1471-70 1481-70 Parameter READ CYCLE tRC tAA tOHA tAMS tDOE tLZOE tHZOE tLZMS tHZMS tWC tSMS tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change MS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High MS LOW to Low MS HIGH to High Write Cycle Time MS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[3] 5 WE HIGH to Low Z Z[3] 5 30 70 65 65 5 0 65 30 0 30 5 85 75 75 7 5 65 35 5 30 5 Z[3, 4] Z[4] 5 30 10 30 100 90 90 7 5 75 40 5 35 5 5 70 40 5 30 10 35 120 100 100 7 5 85 45 5 40 70 70 10 85 45 5 35 10 45 85 85 10 100 50 5 45 100 100 10 120 60 120 120 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min Max 1471-85 1481-85 Min. Max. 1471-100 1481-100 Min. Max. 1471-120 1481-120 Min. Max. Unit
WRITE CYCLE[5]
Notes: 2. Test conditions assume signal transition time of 10 s or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of 1 TTL load, and 100-pF load capacitance. 3. tHZOE , tHZMS , and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 4. At any given temperature and voltage condition, tHZMS is less than tLZMS for any given device. These parameters are guaranteed and not 100% tested. 5. The internal write time of the memory is defined by the overlap of MS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
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CYM1471 CYM1481
Data Retention Characteristics (L Version Only)
1471-70 Parameter VDR ICCDR tCDR[6] Description VCC for Retention Data Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VDR = 3.0V, MS > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 2 400 0 0 1471-100 1471-85 1471-120 2 400 0 2 125 0 1481-70 2 800 0 1481-100 1481-85 1481-120 2 800 0 2 250 V A ns
Test Conditions Min. Max Min. Max Min Max Min Max Min Max Min Max Unit
tR
5
5
5
5
5
5
ns
Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR VDR CS VIH VIH
1471-6
VDR > 2V
4.5V tR
Switching Waveforms
Read Cycle No. 1[7, 8]
tRC ADDRESS tAA tOHA DATAOUT PREVIOUS DATA VALID DATA VALID
1471-7
Notes: 6. Guaranteed, not tested. 7. Device is continuously selected. OE, MS = V IL. 8. Address valid prior to or coincident with MS transition LOW
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CYM1471 CYM1481
Switching Waveforms (continued)
Read Cycle No. 2 [8, 9]
tRC MS tAMS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZMS DATA VALID
1471-8
tHZOE tHZMS HIGH IMPEDANCE
Write Cycle No. 1[5, 10]
tWC ADDRESS tSMS MS tAW tSA WE tSD DATA IN DATA VALID tHZWE DATA I/O DATA UNDEFINED
1471-9
tHA tPWE
tHD
tLZWE HIGH IMPEDANCE
Notes: 9. WE is HIGH for read cycle. 10. Data I/O is high impedance if OE = VIH.
5
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CYM1471 CYM1481
Switching Waveforms (continued)
Write Cycle No. 2 [5, 10, 11]
tWC ADDRESS tSA MS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED
1471-10
tSMS
tHA
tHD
Note: 11. If MS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
6
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CYM1471 CYM1481
Truth Table
MS H L L L WE X H L H OE X L X H Input/Outputs High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
Ordering Information
Speed (ns) 70 85 100 120 Ordering Code CYM1471PS-70C CYM1471LPS-70C CYM1471PS-85C CYM1471LPS-85C CYM1471PS-100C CYM1471LPS-100C CYM1471PS-120C CYM1471LPS-120C Speed (ns) 70 85 100 120 Ordering Code CYM1481PS-70C CYM1481LPS-70C CYM1481PS-85C CYM1481LPS-85C CYM1481PS-100C CYM1481LPS-100C CYM1481PS-120C CYM1481LPS-120C Document #: 38-M-00041-C PS06 36-Pin SIP Module Commercial PS06 36-Pin SIP Module Commercial PS06 36-Pin SIP Module Commercial Package Type PS08 Package Type 36-Pin SIP Module Operating Range Commercial PS08 36-Pin SIP Module Commercial PS08 36-Pin SIP Module Commercial PS08 36-Pin SIP Module Commercial Package Type PS08 Package Type 36-Pin SIP Module Operating Range Commercial
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CYM1471 CYM1481
Package Diagrams
36-Pin SIP Module PS06
3.755 3.765 .190 MAX.
.835 .855
.745 .755
.040 TYP .
.125-.175 PIN 1 .100 TYP .050 TYP . 3.500(36PINS) .020 TYP .
36-Pin SIP Module PS08
3.755 3.765 .120 MAX.
.835 .855
.745 .755
.040 TYP .
.125-.175 PIN 1 .100 TYP . .050 TYP 3.500(36PINS) .020 TYP .
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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