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HY64UD16322A Series
Document Title
2M x 16 bit Low Low Power 1T/1C Pseudo SRAM
Revision history
Revision No. History
1.0 1.1 Initial Change process code -B
Draft Date
Jan. 03. '03 May. 13. '03
Remark
Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.1 May. 2003 1
HY64UD16322A Series
2M x 16 bit Low Low Power 1T/1C SRAM
DESCRIPTION
The HY64UD16322A is a 32Mbit 1T/1C SRAM featured by high-speed operation and super low power consumption. The HY64UD16322A adopts one transistor memory cell and is organized as 2,097,152 words by 16bits. The HY64UD16322A operates in the extended range of temperature and supports a wide operating voltage range. The HY64UD16322A also supports the deep power down mode for a super low standby current. The HY64UD16322A delivers the high-density low power SRAM capability to the high-speed low power system.
FEATURES
* CMOS Process Technology * 2M x 16 bit Organization * TTL compatible and Tri-state outputs * Deep Power Down : Memory cell data hold invalid * Standard pin configuration : 48-FBGA(6mmX8mm) * Data mask function by /LB, /UB * Separated I/O Power Supply : Vddq
PRODUCT FAMILY
Product No.
HY64UD16322A-DF70E HY64UD16322A-DF70I
Voltage [V]
2.7~3.3 2.7~3.3
Mode
1CS with /UB,/LB:tCS1 1CS with /UB,/LB:tCS1
Power Dissipation
(ISB1,Max) (IDPD,Max) (ICC2,Max) 100A 2A 25mA 100A 2A 25mA
Speed tRC[ns]
70 70
Temp. [C]
-25~85 -40~85
Note 1. tCS - /UB,/LB=High : Chip Deselect.
PIN CONNECTION (Top View)
/LB IO9 /OE /UB A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 A2 /CS1 IO2 IO4 IO5 IO6 /WE A11 CS2 IO1 IO3 Vdd Vss IO7 IO8 A20 /CS1 CS2 /WE /OE /LB /UB A20 A0
BLOCK DIAGRAM
ROW DECODER
IO1
SENSE AMP
COLUMN DECODER
PRE DECODER
IO10 IO11 Vss IO12
IO8 IO9
ADD INPUT BUFFER
DATA I/O BUFFER
Vddq IO13 DNU IO15 IO14 IO16 A18 A19 A8 A14 A12 A9
MEMORY ARRAY 2,048K x 16 BLOCK DECODER
WRITE DRIVER
IO16
CONTROL LOGIC
PIN DESCRIPTION
Pin Name /CS1 CS2 /WE /LB /UB DNU Pin Function Chip Select Deep Power Down Write Enable Lower Byte(I/O1~I/O8) Upper Byte(I/O9~I/O16) Do Not Use Pin Name /OE IO1~IO8 IO9~IO16 A0~A20 Vdd Vddq Vss Pin Function Output Enable Lower Data Inputs/Outputs Upper Data Inputs/Outputs Address Inputs Power Supply for Internal Circuit Power Supply for I/O Ground
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.1 May. 2003 2
HY64UD16322A Series
ORDERING INFORMATION
Part Number HY64UD16322A-E HY64UD16322A-I Note 1. E : Extended Temp. (-25C ~ 85C) 2. I : Industrial Temp. (-40C ~ 85C) Speed 70 70 Power LL-Part LL-Part Temperature E1 I2 Package FBGA FBGA
ABSOLUTE MAXIMUM RATINGS 1
Symbol VIN VOUT Vdd Vddq TA TSTG PD TSOLDER Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. Parameter Input Voltage Output Voltage Core Power Supply I/O Power Supply Ambient Temperature Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating
-0.3 to Vdd+0.3 -0.3 to Vddq+0.3
-0.3 to 3.6 -0.3 to 3.6 -25 to 85 -40 to 85 -55 to 150 1.0 260*10
Unit V V V V C C C W C*sec
Remark
HY64UD16322A-E HY64UD16322A-I
TRUTH TABLE
/CS1 CS2 H X X L L L L L L L L L H L H H H H H H H H H H /WE X X X L H H L H H L H H /OE X X X X L H X L H X L H /LB X X H L L L H H H L L L /UB X X H H H H L L L L L L Mode Deselected Deselected Deselected Write Read Output Disabled Write Read Output Disabled Write Read Output Disabled I/O Pin Power I/O1~I/O8 I/O9~I/O16 High-Z High-Z Standby High-Z High-Z Deep Power Down High-Z High-Z Standby DIN High-Z Active DOUT High-Z Active High-Z High-Z Active High-Z DIN Active High-Z DOUT Active High-Z High-Z Active DIN DIN Active DOUT DOUT Active High-Z High-Z Active
Note 1. H=VIH, L=VIL, X=don't care(VIL or VIH) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O1 - I/O8. When /UB is LOW, data is written or read to the upper byte, I/O9 - I/O16.
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HY64UD16322A Series
RECOMMENDED DC OPERATING CONDITION
Symbol Vdd Vddq VSS VIH VIL Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 2.7 0 2.2 -0.21 Typ. 3.0 3.0 Max. 3.3 3.3 0 Vddq+0.3 0.6 Unit V V V V V
Note 1. VIL=-1.5V for pulse width less than 10ns Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
Sym. ILI ILO ICC Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Test Condition VSSVINVdd
VSSVOUTVddq, /CS1=VIH, CS2=VIH, /OE=VIH or /WE=VIL /CS1=VIL, CS2=VIH, VIN=VIH or VIL, II/O=0mA /CS1 0.2V, CS2 Vdd-0.2V, VIN 0.2V or VINVdd-0.2V, Cycle Time=1s. 100% Duty, II/O=0mA
/CS1=VIL, CS2=VIH, VIN=VIH or VIL, Cycle Time=Min. 100% Duty, II/O=0mA
Min. -1 -1 -
Max. 1 1 3
Unit A A mA
ICC1 Average Operating Current ICC2 ISB ISB1 IDPD VOH VOL TTL Standby Current Standby Current(CMOS Input) Deep Power Down Output High Voltage Output Low Voltage
-
5
mA
2.4
25 0.5
mA mA A A V V
/CS1,CS2=VIH or /UB,/LB= VIH
/CS1,CS2Vdd-0.2V, /UB,/LB 0.2V or /UB,/LB Vdd-0.2V, otherwise CS2,/UB,/LBVdd-0.2V, /CS10.2V or /CS1Vdd-0.2V
100 2
0.4
CS2VSS+0.2V IOH=-1.0mA IOL=2.1mA
-
CAPACITANCE
(Temp = 25C, f=1.0MHz) Symbol Parameter CIN Input Capacitance(ADD, /CS1, CS2, /WE, /OE, /UB, /LB) COUT Output Capacitance(I/O) Note : These parameters are sampled and not 100% tested Condition VIN=0V VI/O=0V Max. Unit 8 pF 10 pF
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HY64UD16322A Series
AC CHARACTERISTICS
Vdd=2.7V~3.3V, Vddq=2.7V~3.3V, TA = -25C to 85C(E) / -40C to 85C(I), unless otherwise specified -70 # Symbol Parameter Unit Min. Max. Read Cycle Read Cycle Time 1 tRC 70 ns Address Access Time 2 tAA 70 ns Chip Select Access Time 3 tACS 70 ns Output Enable to Output Valid 4 tOE 20 ns /LB, /UB Access Time 5 tBA 70 ns Chip Select to Output in Low Z 6 tCLZ 10 ns Output Enable to Output in Low Z 7 tOLZ 5 ns /LB, /UB Enable to Output in Low Z 8 tBLZ 10 ns Chip Disable to Output in High Z 9 tCHZ 0 10 ns Out Disable to Output in High Z 10 tOHZ 0 10 ns /LB, /UB Disable to Output in High Z 11 tBHZ 0 10 ns Output Hold from Address Change 12 tOH 5 ns Write Cycle Write Cycle Time 13 tWC 70 ns Chip Selection to End of Write 14 tCW 60 ns Address Valid to End of Write 15 tAW 60 ns /LB, /UB Valid to End of Write 16 tBW 60 ns Address Set-up Time 17 tAS 0 ns Write Pulse Width 18 tWP 50 ns Write Recovery Time 19 tWR 0 ns Write to Output in High Z 20 tWHZ 0 20 ns Data to Write Time Overlap 21 tDW 30 ns Data Hold from Write Time 22 tDH 0 ns Output Active from End of Write 23 tOW 5 ns
AC TEST CONDITIONS
TA = -25C to 85C(E) / -40C to 85C(I), unless otherwise specified Parameter Value Input Pulse Level 0.4V to 2.2V Input Rising and Fall Time 5ns Input Timing Reference Level 1.5V Output Timing Reference Level 0.5*Vddq Output Load See Below
AC TEST LOADS
DOUT Z0=50 Ohm RL=50 Ohm VL=0.5*Vddq CL1 =50 pF
Note 1. Including jig and scope capacitance.
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HY64UD16322A Series
Power-Up Sequence
1. Supply power with CS2 high. 2. Maintain stable power for longer than 200s.
Deep Power Down Entry Sequence
1. Keep CS2 low state. Deep power down mode is maintained while CS2 is low state.
Deep Power Down Exit Sequence
1. Keep CS2 high state. 2. Maintain stable power for longer than 200s.
STATE DIAGRAM
Power On Power On
Power-Up Sequence
CS2=VIH
Deep Power Down Exit Sequence
Wait 200s Wait 200 200s
/ CS1=VIL, CS2=VIH, /UB&/LBVIH
Active Active
CS2=VIL CS2=VIH, /CS1=VIH or /UB,/LB=VIH CS2=VIL
Standby Standby Mode Mode
Deep Power Deep Power Down Mode Down Mode
Deep Power Down Entry Sequence
STANDBY MODE CHARACTERISTICS
Mode Standby Deep Power Down Memory Cell Data Valid Invalid Standby Current[A] 100 / 70ns 2 Wait Time[s] 0 200
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HY64UD16322A Series
TIMING DIAGRAM
READ CYCLE 1 ( Note 1, 4 )
tRC ADD tAA /CS1 Vih tBA tBHZ(3) /OE tOLZ(3) tBLZ(3) tCLZ(3) Data Out High-Z Data Valid tOE tOHZ(3) tACS tCHZ(3) CS2 tOH
/UB, /LB
READ CYCLE 2 ( Note 1, 2, 4 )( CS2=Vih )
tRC ADD tAA tOH Data Out Previous Data Data Valid tOH
READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih )
/CS1 /UB, /LB tCLZ(3) Data Out High-Z Data Valid
tACS
tCHZ(3)
Notes : 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status. 2. /OE = VIL 3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output voltage levels. 4. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active.
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HY64UD16322A Series WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled )
tWC ADD tWR(2) /CS1 Vih tCW
CS2
tAW tBW
/UB, /LB
/WE High-Z
tAS
tWP tDW tDH
Data In
Data Valid tWHZ(3,8) tOW
(6) (7)
Data Out
WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled )
tWC ADD tAS /CS1 Vih tCW tWR(2)
CS2
tAW tBW
/UB, /LB
/WE High-Z
tWP tDW tDH
Data In
Data Valid
Data Out
High-Z
Notes : 1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB. 2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. /OE is continuously low (/OE=VIL) 6. Q(data out) is the invalid data. 7. Q(data out) is the read data of the next address. 8. tWHZ is defined as the time at which the outputs achieve the high impedance state. It is not referenced to output voltage levels. 9. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active. 10. Do not input data to the I/O pins while they are in the output state. Revision 1.1 May. 2003
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HY64UD16322A Series
AVOID TIMING
Hynix 1T/1C SRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal shorter than tRC during over 10us at read operation which showed in abnormal timing, Hynix 1T/1C SRAM needs a normal read timing at least during 10us which showed in avoidable timing(1) or toggle the /CS1 to high(tRC) one time at least which showed in avoidable timing(2)
ABNORMAL TIMING
/CS1
/WE < tRC ADD
10us
AVOIDABLE TIMING(1)
/CS1
/WE
10us tRC
ADD
AVOIDABLE TIMING(2)
/CS1
tRC
/WE < tRC ADD
10us
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HY64UD16322A Series
PACKAGE DIMENSION
48ball Fine Pitch Ball Grid Array Package(F)
TOP VIEW TOP VIEW BOTTOM VIEW BOTTOM VIEW
A1 CORNER INDEX AREA
B1 B A
A1 INDEX MARK
A A B C C D C1 E F G H 6 5 B/2 SIDE VIEW SIDE VIEW 5 C E E1 E2 SEATING PLANE A 3 D(DIAMETER) unit : mm Symbol A B B1 C C1 D E E1 E2 R
Revision 1.1 May. 2003
C/2
4
3
2
1
4
R
NOTE. 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION "D" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION.
Min. 5.90 7.90 0.30 0.3 0.20 -
Typ. 0.75 6.00 3.75 8.00 5.25 0.35 0.3 1.00 0.75 0.25 -
Max. 6.10 8.10 0.40 0.4 1.10 0.30 0.08
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HY64UD16322A Series
MARKING INFORMATION
Package
H Y U
Marking Example
D 1 6 3 2 2 A
FBGA
c
s
s
t
y
y
w
w
p
x
x
x
x
x
K
O
R
Index
* HYUD16322A HY U D 16 32 2 A *c * ss *t * yy * ww *p * xxxxx * KOR : Part Name : HYNIX : Power Supply : Tech. + Classification : Bit Organization : Density : Mode : Version : Power Consumption : Speed : Temperature
: Vdd=2.7V~3.3V/Vddq=2.7V~3.3V : 1T+1C : x16 : 32M : 1CS with /UB,/LB;tCS : 2nd Generation : D - Low Low Power : 70 - 70ns
: E - Extended(-25 ~ 85C) I - Industrial(-40 ~ 85C) : Year (ex : 02 = year 2002, 03= year 2003) : Work Week ( ex : 12 = work week 12 ) : Process Code :B : Lot No. : Origin Country
Note - Capital Letter - Small Letter
: Fixed Item : Non-fixed Item
Revision 1.1 May. 2003
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