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19-2484; Rev 0; 7/02
ECL/PECL Dual Differential 2:1 Multiplexer
General Description
The MAX9384 fully differential dual 2:1 multiplexer (mux) features extremely low propagation delay (560ps max) and output-to-output skew (40ps max). The device is ideal for clock and data multiplexing applications. The two 2:1 muxes are controlled individually or simultaneously through mux select inputs COM_SEL, SEL0, and SEL1. The mux select inputs are compatible with ECL/PECL logic, and are referenced to on-chip outputs VBB0 and VBB1, nominally VCC - 1.33V. The differential inputs D, D can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip supply output VBB as a reference voltage. All the differential inputs have bias and clamp circuits that force the outputs to a low default when the inputs are left open or at VEE. The single-ended mux select inputs have pulldowns to VEE, providing low default inputs when the select inputs are left open. The device operates with a wide supply range (VCC VEE) of +3.0V to +5.5V for PECL or -3.0V to -5.5V for ECL, and is pin compatible with the MC100LVEL56 and MC100EL56. The MAX9384 is offered in a 20-pin wide SO package, and is specified for operation from -40C to +85C. o 40psP-P Deterministic Jitter o 440ps Differential Propagation Delay o 12ps Output-to-Output Skew o Individual and Common Select o +3.0V to +5.5V Supplies for Differential LVPECL/PECL o -3.0V to -5.5V Supplies for Differential LVECL/ECL o Outputs Low for Inputs Open or at VEE o >2kV ESD Protection (Human Body Model) o Pin Compatible with MC100LVEL56 and MC100EL56
Features
MAX9384
Ordering Information
PART MAX9384EWP TEMP RANGE -40C to +85C PIN-PACKAGE 20 Wide SO
Applications
High-Speed Telecom, Datacom Applications Central-Office Backplane Clock Distribution Access Multiplexers (DSLAM/DLC)
Functional Diagram appears at end of data sheet. TOP VIEW
D0a 1 DOa 2 VBB0 3 D0b 4 DOb 5 D1a 6 D1a 7 VBB1 8 D1b 9 D1b 10
Pin Configuration
20 VCC 19 Q0 18 Q0 17 SEL0
MAX9384
16 COM_SEL 15 SEL1 14 VCC 13 Q1 12 Q1 11 VEE
SO
________________________________________________________________ Maxim Integrated Products
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ECL/PECL Dual Differential 2:1 Multiplexer MAX9384
ABSOLUTE MAXIMUM RATINGS
VCC - VEE .................................................................-0.3V to 6.0V Inputs (D_, D_, SEL_, COM_SEL) to VEE....-0.3V to (VCC + 0.3V) D_ to D_ ..............................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................0.65mA Junction-to-Ambient Thermal Resistance in Still Air 20-Lead Wide SO ....................................................+100C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 20-Lead Wide SO ......................................................+58C/W Junction-to-Case Thermal Resistance 20-Lead Wide SO ......................................................+20C/W Continuous Power Dissipation (TA = +70C) 20-Lead Wide SO (derate 10mW/C above +70C) ..................................800mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (D_, D_, Q_, Q_, SEL_, COM_SEL) ................................. 2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
SINGLE-ENDED INPUT SEL_, COM_SEL Input High Voltage VIH Internally referenced to VBB, Figure 1 Internally referenced to VBB, Figure 1 VIH, VIL VBB connected to the unused input, Figure 1 VBB connected to the unused input, Figure 1 Figure 1 Figure 1 Figure 1 VIH, VIL, VIHD, VILD VCC 1.165 VCC VCC 1.165 VCC VCC 1.165 VCC V
Input Low Voltage Input Current
VIL IIN
VCC 1.810 -10
VCC - VCC 1.475 1.810 +50 -10
VCC - VCC 1.475 1.810 +50 -10
VCC 1.475 +50
V A
DIFFERENTIAL INPUT (D_, D_) Single-Ended Input High Voltage Single-Ended Input Low Voltage High Voltage of Differential Input Low Voltage of Differential Input Differential Input Voltage Input Current VIH VCC 1.165 VCC VCC 1.165 VCC VCC 1.165 VCC V
VIL
VCC 1.810 VEE + 1.3 VEE 0.095 -100
VCC - VCC 1.475 1.810 VCC VCC 0.095 3.0 +100 VEE + 1.2 VEE 0.095 -100
VCC - VCC 1.475 1.810 VCC VCC 0.095 3.0 +100 VEE + 1.2 VEE 0.095 -100
VCC 1.475 VCC VCC 0.095 3.0 +100
V
VIHD VILD VIHD VILD IIN
V V V A
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ECL/PECL Dual Differential 2:1 Multiplexer
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER OUTPUT (Q_, Q_) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage VOH Figure 2 VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.085 0.998 0.880 1.025 0.947 0.880 1.025 0.929 0.880 V SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
MAX9384
VOL VOH VOL
Figure 2
VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.830 1.707 1.555 1.810 1.685 1.620 1.810 1.690 1.620 600 640 660
V
Figure 2
mV
REFERENCE OUTPUT (VBB) Reference Voltage Output SUPPLY Supply Current IEE (Note 5) 15 24 17 24 19 24 mA VBB IBB = 0.5mA (Note 4) VCC 1.38 VCC - VCC 1.322 1.26 VCC - VCC - VCC 1.38 1.330 1.26 VCC 1.38 VCC - VCC 1.335 1.26 V
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ECL/PECL Dual Differential 2:1 Multiplexer MAX9384
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN 500MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 6)
PARAMETER Differential Input-to-Output Delay Single-Ended Input-to-Output Delay SEL_ and COM_SEL to Output Delay Output-to-Output Skew Added Random Jitter Added Deterministic Jitter Switching Frequency Output Rise and Fall Time (20% to 80%) SYMBOL tPLHD, tPHLD tPLH1, tPHL1 tPLH2, tPHL2 tSKOO tRJ CONDITIONS -40C MIN 340 TYP MAX 540 MIN 350 +25C TYP MAX 550 MIN 360 +85C TYP MAX 560 UNITS
Figure 2
ps
Figure 3 (Note 7)
290
540
310
560
330
580
ps
Figure 4 (Note 7)
310
730
320
740
330
750
ps
(Note 8) fIN = 500MHz (Note 9) 1.0Gbps 223 - 1 PRBS pattern (Note 9) VOH - VOL 300mV, Figure 2 Figure 2 1.5
12 0.3
40 0.8
12 0.4
40 0.8
12 0.5
40 0.8
ps ps(RMS)
tDJ
40
70
40
70
40
70
ps(P-P)
fMAX
1.5
1.5
GHz
tR , tF
200
310
440
200
310
440
200
310
440
ps
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. DC parameters production tested at TA = +25C and guaranteed by design over the full operating temperature range. Use VBB only for inputs that are on the same device as the VBB reference. All pins open except VCC and VEE. Guaranteed by design and characterization. Limits are set at 6 sigma. Test conditions are VIH = VCC - 1.11V and VIL = VCC - 1.53V. Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal. Device jitter added to the input signal. Differential input signal.
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ECL/PECL Dual Differential 2:1 Multiplexer MAX9384
Typical Operating Characteristics
(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, COM_SEL = low, SEL_ = low, outputs loaded with 50 1% to VCC - 2V, fIN = 500MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.)
DIFFERENTIAL OUTPUT EYE PATTERN AT 1Gbps, PRBS 223 - 1, NRZ DATA PATTERN
MAX9384 toc01
DIFFERENTIAL OUTPUT EYE PATTERN AT 500Mbps, PRBS 223 - 1, NRZ DATA PATTERN
MAX9384 toc02
SUPPLY CURRENT (IEE) vs. TEMPERATURE
MAX9384 toc03
25.0 22.5 SUPPLY CURRENT (mA) 20.0 17.5 15.0 12.5 10.0
Q_ - Q_ 200mV/div
Q_ - Q_ 200mV/div
200ps/div
300ps/div
-40
-15
10
35
60
85
TEMPERATURE (C)
OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
MAX9384 toc04
TRANSITION TIME vs. TEMPERATURE
MAX9384 toc05
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
MAX9384 toc06
800 VILD = 0.5V DIFFERENTIAL OUTPUT VOLTAGE 700
350
475
TRANSITION TIME (ps)
tR 300 tF
TRANSITION TIME (ps)
325
425 tPLHD 375 tPHLD
600
500
400
275
325
300 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY (MHz)
250 -40 -15 10 35 60 85 TEMPERATURE (C)
275 -40 -15 10 35 60 85 TEMPERATURE (C)
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ECL/PECL Dual Differential 2:1 Multiplexer MAX9384
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14, 20 15 16 17 18 19 NAME D0a D0a VBB0 D0b D0b D1a D1a VBB1 D1b D1b VEE Q1 Q1 VCC SEL1 SEL0 Q0 Q0 FUNCTION Noninverting Differential Input a for MUX 0. Internal 120k pulldown to VEE. Inverting Differential Input a for MUX 0. Internal 120k pulldown to VEE and 120k pullup to VCC. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass VBB0 to VCC with a 0.01F ceramic capacitor. Otherwise leave open. VBB0 is internally connected to VBB1. Noninverting Differential Input b for MUX 0. Internal 120k pulldown to VEE. Inverting Differential Input b for MUX 0. Internal 120k pulldown to VEE and 120k pullup to VCC. Noninverting Differential Input a for MUX 1. Internal 120k pulldown to VEE. Inverting Differential Input a for MUX 1. Internal 120k pulldown to VEE and 120k pullup to VCC. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01F ceramic capacitor. Otherwise leave open. VBB1 is internally connected to VBB0. Noninverting Differential Input b for MUX 1. Internal 120k pulldown to VEE. Inverting Differential Input b for MUX 1. Internal 120k pulldown to VEE and 120k pullup to VCC. Negative Supply Voltage Inverting Output for MUX 1. Typically terminate with 50 resistor to VCC - 2V. Noninverting Output for MUX 1. Typically terminate with 50 resistor to VCC - 2V. Positive Supply Voltage. Bypass each VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Select Logic Input for MUX 1. Internal 210k pulldown to VEE. Select Logic Input for MUX 0. Internal 210k pulldown to VEE. Inverting Output for MUX 0. Typically terminate with 50 resistor to VCC - 2V. Noninverting Output for MUX 0. Typically terminate with 50 resistor to VCC - 2V.
COM_SEL Common Select Logic Input. Internal 210k pulldown to VEE.
VCC VIHD (MAX) VIHD - VILD
VCC
VIH VILD (MAX) VBB VIL VIHD (MIN) VIHD - VILD VILD (MIN) VEE VEE
DIFFERENTIAL INPUT VOLTAGE DEFINITION
SINGLE-ENDED INPUT VOLTAGE DEFINITION
Figure 1. Input Definitions 6 _______________________________________________________________________________________
ECL/PECL Dual Differential 2:1 Multiplexer MAX9384
VIHD
D_ VIHD - VILD D_ tPLHD Q_ VOH - VOL Q_ tPHLD
VILD
VOH
VOL
80% VOH - VOL DIFFERENTIAL OUTPUT WAVEFORM VOH - VOL
80%
0V (DIFFERENTIAL)
20% Q_ - Q_ tR
20%
tF
Figure 2. Differential Input-to-Output Propagation Delay Timing Diagram
D_ WHEN D_ = VBB VBB
VIH
OR
VBB D_ WHEN D_ = VBB tPLH1 tPHL1 VOH VIL
Q_ VOH - VOL
VOL Q_
Figure 3. Single-Ended Input-to-Output Propagation Delay Timing Delay
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ECL/PECL Dual Differential 2:1 Multiplexer MAX9384
VIHD
D_a AND D_b VIHD - VILD D_a AND D_b
VILD
VIH
VBB SEL_ WHEN COM_SEL = LOW OR COM_SEL WHEN SEL_ = LOW VIL tPLH2 tPHL2 VOH
Q_ VOH - VOL Q_
VOL
Figure 4. Select Inputs (COM_SEL, SEL_) to Output (Q_, Q_) Delay Timing Diagram
Detailed Description
The MAX9384 dual differential 2:1 multiplexer features extremely low propagation delay (560ps max) and outputto-output skew (40ps max). These features make the device ideal for clock and data multiplexing applications. The two differential muxes are controlled individually or simultaneously through select control inputs, SEL0, SEL1, and COM_SEL (see Table 1). The select control inputs are referenced to VBB (nominally VCC - 1.33V) and are internally pulled down to VEE through 210k resistors. By default, the select inputs are low when left open. The differential inputs D_, D_ can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference voltage VBB. The reference output voltage, pins VBB0 and VBB1, provides the input reference voltage for singleended operation for each mux. A single-ended input of at least VBB_ 95mV or a differential input of at least 95mV switches the outputs to the VOH and VOL levels
specified in the DC Electrical Characteristics. The maximum magnitude of the differential input from D_ to D_ is 3.0V. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously. The device operates over a wide supply range (VCC VEE) of +3.0V to +5.5V for PECL or -3.0V to -5.5V for ECL, and is pin compatible with the MC100LVEL56 and MC100EL56.
Single-Ended Operation
A single-ended input can be driven to VCC and VEE or by a single-ended LVPECL/LVECL signal. D_, D_ are differential inputs but can be configured to accept single-ended inputs. This is accomplished by connecting the on-chip reference voltage, VBB_, to an unused complementary input as a reference. For example, the differential D0a, D0a input is converted to a noninverting, single-ended input by connecting V BB0 to D0a and connecting the single-ended input to D0a. Similarly, an inverting input is obtained by connecting VBB0 to D0a and connecting the single-ended input to D0a. When using the VBB_ reference output, bypass it with a 0.01F ceramic capacitor to VCC. If not used, leave it open. The VBB_ reference can source or sink 0.5mA, which is sufficient to drive two inputs.
Table 1. Input Select Truth Table
CONTROL INPUT DATA INPUT COM_SEL SEL_ D_ , D_ L or open b* L or open H a H X a *Default input when COM_SEL and SEL_ are left open.
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ECL/PECL Dual Differential 2:1 Multiplexer
Applications Information
Output Termination
Terminate the outputs through 50 to VCC - 2V or use equivalent Thevenin terminations. Terminate each Q_ and Q_ output with identical termination on each for minimal distortion. When a single-ended signal is taken from the differential output, terminate both Q_ and Q_. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device's total thermal limits should be observed.
Traces
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
MAX9384
Supply Bypassing
Bypass each VCC to VEE with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors. Place the capacitors as close to the device as possible, with the 0.01F capacitor closest to the device pins. Use multiple vias when connecting the bypass capacitors to ground. When using the VBB0 or VBB1 reference outputs, bypass each one with a 0.01F ceramic capacitor to VCC. If the VBB0 or VBB1 reference outputs are not used, they can be left open.
Chip Information
TRANSISTOR COUNT: 485 PROCESS: Bipolar
Functional Diagram
VCC 120k D0a D0a MUX 0 D0b D0b VCC 120k D1a D1a MUX 1 D1b D1b 120k VEE SEL0 COM_SEL SEL1 210k MAX9384 Q1 Q1 120k VEE Q0 Q0
VEE
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ECL/PECL Dual Differential 2:1 Multiplexer MAX9384
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOICW.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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