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| ST40RA166 32-bit Embedded SuperH Device PRELIMINARY DATA Integer & FP Execution Units JT G A JT AG Debug UDI SCIF SCIF Tim (TMU er ) R Tim C eal e lk Interrupt Ctrl SuperH ay yw Clock Ctrl Flash PLLs PCI I/F 66MHz ST40 Local Mem I/F ory Cbus Bridge/ SuperH ay I/F yw EM I M MU IC ache MM U D Cache Registers PIO Interface 24 Data 5 Channel D MA C ontroller 2 Channel Control M PX C oprocessor 32 Data 32 Data PC P I eripherals 64 Data SDRAM P eripherals Overview The ST40RA166 is the first member of the ST40 family. Based on the SH-4, SuperH CPU core from SuperH Inc, the ST40RA166 is designed to work as a standalone device, or as part of a two chip solution for application specific systems. Example applications the ST40RA166 is designed for include digital consumer, embedded communications, industrial and automotive. The high connectivity of the ST40 through its PCI bus and its dual memory uses makes it a versatile device, ideal for data-intensive and high performance applications. q High throughput, low latency, split transaction packet router s Memory protection and VM system support q q 64-entry unified TLB, 4-entry instruction TLB 4 Gbytes address space s Standard ST40 peripherals q q 2 synchronous serial ports with FIFO (SCIF) Timers and a real-time clock IO devices q q Mailbox register for interprocessor communication Additional PIO System features s 32-bit SuperH CPU q q q q q Bus interfaces s Local memory interface SDRAM & DDR SDRAM q 64-bit hardware FPU (1.16 GFLOPS) 128-bit vector unit for matrix manipulations 166 MHz, 300 MIPS (Dmips 1.1) Up to 664 Mbytes/s CPU bandwidth Direct mapped, on-chip, ICache (8 Kbytes) and DCache (16 Kbytes) Up to 100 MHz (1.6 Gbytes/sec peak throughput) s PCI interface - 32-bit, 66/33 MHz, 3.3 V s Enhanced memory interface (EMI) q q q q q s High-performance 5-channel DMA engine, supporting 1D or 2D block moves and linked lists s SuperHyway internal interconnect 32-bit bus, up to 83 MHz, for attaching peripherals High-speed, sync mode, burst flash ROM support SDRAM support MPX initiator and target interface Programmable MPX bus arbiter March 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/88 ST40RA166 Table of Contents Chapter 1 Chapter 2 Scope of this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 ST40 documentation suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 CPU documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 System documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 3 3.1 3.2 3.2.1 3.2.2 3.2.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ST40 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SuperH ST40 SH-4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SuperHyway internal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standard ST40 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 3.3.1 3.3.2 3.3.3 Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 EMI/MPX interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 3.4.1 I/O devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 3.5.1 3.5.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Development systems and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Software compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 4 4.1 4.1.1 System configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 System addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 4.3 4.3.1 4.3.2 4.3.3 System identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ST40 core interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ST40 standard system interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ST40RA166 I/O device interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 4.5 4.6 4.7 4.7.1 GPDMA channel mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 EMI DACK mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 EMI address pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Memory bridge control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/88 ST40RA166 4.7.2 4.7.3 Memory bridge status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Changing control of a memory bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 EMI.GENCFG EMI general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 LMI.COC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LMI.CIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SYSCONF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SYSCONF.SYSCONF2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PCI.PERF register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chapter 5 5.1 5.2 5.3 5.3.1 5.3.2 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Clock domains and sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Recommended operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clocks and registers at start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CLOCKGENA_2x PCI (PCI_DIV_BYPASS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Division ratios on CLOCKGENA_2x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 5.4.1 5.4.2 5.4.3 5.4.4 Setting clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Programming the PLL output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Changing clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Changing the core PLL frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Changing the frequency division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 5.5.1 5.5.2 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CPU low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Module low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 Clock generation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CLOCKGENB.CLK_SELCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CPG.STBCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CLOCKGENA.STBREQCR and CLOCKGENB.STBREQCR registers . . . . . . . . . . . . . . . . . . . . . . 38 CLOCKGENA.STBREQCR_SET and CLOCKGENB.STBREQCR_SET registers . . . . . . . . . . . . . 38 CLOCKGENA.STBREQCR_CLR and CLOCKGENB.STBREQCR_CLR register CLOCKGENA.STBACKCR and CLOCKGENB.STBACKCR register . . . . . . . . . . . . 38 . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 6 6.1 6.1.1 6.1.2 6.1.3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 DC absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Fmax clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pad specific output AC characteristics 3/88 ST40RA166 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 Rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PCI interface AC specifications LMI interface (SDRAM) AC specifications LMI interface (DDR-SDRAM) AC specifications DDR bus termination (SSTL_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 General purpose peripheral bus (EMI) AC specifications . . . . . . . . . . . . . . . . . . . . . . . 51 PIO AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 System CLKIN AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Low power CLKIN AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 UDI and IEEE 1149.1 TAP AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chapter 7 7.1 7.2 7.3 7.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Function pin use selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PBGA 27 x 27 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Pin states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Chapter 8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Appendix A Interconnect architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 A.1 A.1.1 A.1.2 A.1.3 A.1.4 A.1.5 A.1.6 Arbitration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PCI arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 EMI arbiter: (CPU buffer, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LMI 1 arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PER arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LMI2 arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Return arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 A.2 A.2.1 A.2.2 A.2.3 A.2.4 A.2.5 Interconnect registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 LMI1 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LMI2 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 EMI arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 PCI arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Peripheral arbiter Appendix B Implementation restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 B.1 B.1.1 ST40 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 tas.b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4/88 ST40RA166 B.1.2 B.1.3 B.1.4 Store queue power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 UBC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 System standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 B.2 B.2.1 B.2.2 B.2.3 B.2.4 B.2.5 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Type 2 configuration accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Software visible changes between STB1HC7 and ST40RA166H8D . . . . . . . . . . . . . . . . . . . . . . . . 82 Error behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Master abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 B.3 B.3.1 B.3.2 B.3.3 EMI/EMPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 EMPI burst mode operation: ST40RA166 MPX target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 SDRAM initialization during boot from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MPX boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 B.4 B.4.1 Mailbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Test and set functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 B.5 B.5.1 B.5.2 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Module power-down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Accesses to modules in power-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 B.6 B.6.1 B.6.2 PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PIO default functionality following reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PCI/PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 B.7 B.7.1 B.7.2 B.7.3 Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Memory bridge functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Pad drive control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 B.8 B.8.1 B.8.2 B.8.3 GPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Linked list support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2-D transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Protocol signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 B.9 RTC clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 5/88 ST40RA166 1 Scope of this document 1 Scope of this document This document describes only those areas of the ST40RA166 that are device specific, for example the system address map. Information that is generic to the ST40 family of devices is contained in the ST40 documentation suite. 2 ST40 documentation suite This document references a number of other generic ST40 documents that combined together form a complete datasheet. CPU documentation The SH-4 CPU core and its instruction set are documented in the SH-4 CPU Core Architecture Manual. System documentation Devices listed in the system address map, Figure 1 on page 13 are documented in the ST40 System Architecture Manual: q q Volume 1: System, details the ST40 CPU and standard peripherals, Volume 2: Bus Interfaces, details the standard PCI, LMI and EMI bus interfaces. 6/88 3 Architecture ST40RA166 3 3.1 Architecture Overview The ST40RA166 combines an SH-4, 32-bit microprocessor with a wide range of interfaces to external peripherals. This section briefly describes each of the features of the ST40RA166. 3.2 3.2.1 ST40 system SuperH ST40 SH-4 core Figure 1 illustrates the system architecture of the ST40 SH-4 core. The following section briefly describes the features and performance of the core. CPU UBC FPU 32-bit add (instruction) 32-bit data (instruction) 32-bit address (data) 64-bit data (store) 32-bit data (load) 32-it data (store) Lower 32-bit data Lower 32-bit data ICache 8 Kbytes ITLB Cache and TLB controller UTLB DCache 16 Kbytes 29bit add Figure 1: ST40 SH-4 core architecture Central processing unit The central processing unit is built around a 32-bit RISC, two-way superscalar architecture. Operating at 166 MHz it runs with high code density using fixed length 16-bit instructions. It has a load/store architecture, delayed branch instruction capability and an on-chip multiplier. It uses a fivestage pipeline. 7/88 32bit data 32bit data Upper 32-bit data ST40RA166 Floating point unit/multiply and accumulate 3 Architecture The on-chip, floating point coprocessor executes single precision (32-bit) and double precision (64-bit) operations. It has a five-stage pipeline and supports IEEE754-compliant data types and exceptions. It has rounding modes: (round-to-nearest) and (round-to-zero), and handles denormalized numbers (truncation-to-zero) or interrupt generation for compliance with IEEE754. The floating point unit performs the following functions: q q q fmac (multiply-and-accumulate), fdiv (divide), fsqrt (square root) instructions, 3-D graphics instructions (single-precision): 4-dimensional vector conversion and matrix operations (ftrv): 4 cycles (pitch), 7 cycles (latency), 4-dimensional vector (fipr) inner product: 1 cycle (pitch), 4 cycles (latency). MMU configuration There is 4 Gbytes virtual address space with 256 address space identifiers (8-bit ASIDs), supporting single virtual and multiple virtual memory modes. Page sizes are 1 Kbyte, 4 Kbytes, 64 Kbytes or 1 Mbyte. The MMU supports four-entry, fully associative ITLB for instructions and 64-entry fully associative UTLB for instructions and operands. Software-controlled replacement and random-counter replacement algorithms are also supported. The physical address space is 512 Mbytes (29-bit), see Figure 2: System address organization on page 12. Cache 8 Kbytes of direct-mapped instruction cache are organized as 256 32-byte lines, and 16 Kbytes of direct-mapped operand cache are organized as 512 32-byte lines. RAM mode (8-Kbyte cache plus 8-Kbyte RAM) with selectable write method (copy back or write through) is supported. A single stage buffer for copy-back and a single stage buffer for write-through are available. The cache contents can be address mapped and there is a 32-byte two-entry store queue. 3.2.2 SuperHyway internal interconnect The ST40RA166 uses the SuperHyway memory mapped packet router for on-chip intermodule communication. The interconnect supports a split transaction system allowing a nonblocking high throughput, low latency system to be built. There are separate request and response packet routers. The ST40RA166 SuperHyway implementation is show in Section 4.7: Memory bridge control on page 19. The interconnect allows simultaneous requests between multiple modules and is able to ensure a very high data throughput with in many cases zero routing, arbitration and decode latencies. 3.2.3 Standard ST40 peripherals Synchronous serial channel There are two ST40 compatible full duplex communication channels (SCIF1, SCIF2). Asynchronous mode is supported. A separate 16-byte FIFO is provided for the transmitter and receiver. Interrupt controller The interrupt controller supports all of the on-chip peripheral module interrupts, and five external interrupts (NMI and IRL0 to IRL3). The priority can be set for each on-chip peripheral module interrupt. IRL0 to IRL3 are configured as four independent interrupts or encoded to provide 15 external interrupt levels. 8/88 3 Architecture Debug controller ST40RA166 Debugging is performed by break interrupts. There are two break channels. The address, data value, access type, and data size can all be set as break conditions. Sequential break functions are supported. The user debug interface (UDI) contains a five-pin serial interface conforming to JTAG, IEEE Standard TAP and boundary scan architecture. The interface provides host access to the 1 Kbyte ASERAM for emulator firmware (accessible only in ASE mode). Timers The three-channel, auto-reload, 32-bit timer has an input capture function and a choice of seven counter input clocks. Real-time clock The built-in 32-kHz crystal oscillator has a maximum 1/256 second resolution. It has dynamically programmable operating frequencies and on-chip clock and calendar functions. It has two sleep modes and one standby mode. Programmable PLLs The ST40RA166 has three programmable PLLs. The PLLs are configured by MODE pins at reset and then reconfigured by software to optimize system performance or reduce system power consumption. General-purpose DMA controller The five-channel physical address GPDMA controller has four general-purpose channels for memory-to-memory or memory-to-peripheral transfers, and one buffered multiplexed channel. Both 2-D block moves and linked lists are supported. Two sets of DMA handshake pins are available for use by external devices to support efficient transfer interdevice transfers via external interfaces such as the EMI MPX. Parallel I/O module 24 bits of parallel I/O are provided from the ST40 compatible PIO. Each bit is programmable as an output or an input. "Input compare" generates an interrupt on any change of any input bit. 3.3 3.3.1 Bus interfaces Local memory interface The LMI supports 16-, 32- and 64-bit wide bus SDRAM and DDR SDRAM, at up to 100 MHz with a maximum address space of 112 Mbytes. Devices supported include two and four bank 16-, 64-, 128- and 256-Mbit technologies in x4, x8, x16 and x32 packages. The LMI pads are dual mode pads electrically compatible with LVTTL (for standard SDRAM) and SSTL_2 (for DDR SDRAM). For full detail of the configuration options of the LMI please see ST40 Architecture Manual, Volume 2: Bus Interfaces. 3.3.2 PCI interface The PCI interface complies to the PCI v2.1 and Power Management Interface V1.0 specifications. It is 32 bits wide and operates at 33 or 66 MHz. Master and target mode are supported. A PCI arbiter and clock generator is provided inside the ST40RA166. For details on the configuration options for the PCI interface please see ST40 System Architecture Manual, Volume 2: Bus Interfaces. 9/88 ST40RA166 3.3.3 EMI/MPX interface 3 Architecture The EMI/MPX interface contains the following blocks. For full details of the configuration options of the EMI please see the ST40 System Architecture Manual, Volume 2: Bus Interfaces. EMI memory interface initiator The EMI provides access to ROMs, SDRAM, memory mapped asynchronous external peripherals and synchronous MPX bus peripherals. The EMI supports burst mode flash ROM and MPX for memory-mapped device coupling. The ST40RA166 GPDMA unit accesses external devices and two sets of DMA channels control signals are provided for this purpose. EMPI memory interface target The EMPI is a synchronous MPX target that allows for an external MPX initiator to access the ST40RA166 internal memory space. The EMPI contains a general purpose control channel and four high performance channels each of which implements a write buffer and a pair of 32-byte readahead buffers able to optimize external device burst access to and from the ST40RA166 internal memory. These buffers can be associated with memory regions within the ST40RA166 and external DMA channels. Four sets of DMA handshake signals are provided to the EMPI to optimize long burst transfers between the ST40RA166 and external initiators like the STi5514. MPX bus arbiter The ST40RA166 has an internal programmable bus arbiter to optimize utilization of the MPX bus. The ST40RA166 MPX arbiter supports one external initiator and has programmable bus priority (ST40RA166 or external device), bus parking (ST40RA166, external, idle or last user) and latency timers. The internal arbiter can be bypassed if an external arbiter supporting more initiators is required. 3.4 3.4.1 I/O devices Mailbox The ST40 and the external microprocessor communicate with each other and synchronize their activities using the memory-mapped mailbox. Processes generate interrupts to either CPU, and send and receive messages between the two CPUs. There are buffers for message queueing in both directions and interrupt bits can be set in each direction. Access to the mailbox from external devices is through the ST40RA166 EMPI or the PCI target interface. 3.5 3.5.1 Software Development systems and software The ST40RA166 supports application development, with a full range of debug features and an emulation mode (ASE). The ASE mode has a dedicated 1-Kbyte buffer for emulator firmware, supporting performance counters and branch trace. The ST40RA166, with its memory management unit, supports standard operating systems including WindowsCE and Linux. The ST40 has a wide range of development support from ST and third parties, and efficiently runs applications written in C, C++ and Java. ST's own tools include: q q q C/C++ compilers, debugger, proprietary OS. 10/88 4 System configuration Third parties include: q q q q q q ST40RA166 Microsoft: WindowsCE, Sun: JavaOS for consumers, WindRiver: VxWorks, Tornado tools, Linux, Insignia JVM, ANT browser. 3.5.2 Software compatibility SH-4 core software The ST40RA166 SH-4 core is binary code compatible with the Hitachi SH775x family. Standard peripheral driver The ST40 standard SCIF, timer, real-time clock and PIO are compatible with the ST40 SOC range of devices and the Hitachi SH775x family. Bus interface driver The PCI, LMI, and EMI interfaces are register compatible with the ST40 SOC range of devices. The ST40RA166 contains an EMPI and MPX arbiter and MPX clock control unit which are additional to the bus interface components of the ST40 SOC range of devices. I/O device driver The Mailbox is a module with no ST legacy software. 4 System configuration The ST40RA166 system address map has been designed to maintain compatibility with existing ST40 family devices and other STMicroelectronics devices. The SH-4 core and core peripherals maintain compatibility with the ST40 SOC range of devices and Hitachi SH7750 wherever possible. Devices listed in Table 1: ST40RA166 system address map on page 13, are documented in the ST40 System Architecture Manual as described in Chapter 2: ST40 documentation suite on page 6. Coherency between the cache and external memory is assured by software. The ST40 CPU has cache control instructions which enable software to do this. Details of these instructions are given in the ST40 CPU Core Architecture Manual. The ST40RA166 is run in little endian mode. The ST40RA166 power on configuration is controlled by the MODE pins as defined in Table 33: Mode selection pins for ST40RA166 on page 56. Subsystem configuration registers are usually found with the module register space. Other system level functions and the software register locations are shown in Table 9: System configuration registers on page 21. 11/88 ST40RA166 4 System configuration 4.1 System addresses The ST40 family system address organization is shown in Figure 2. 0x18000000 Reserved 0x00000000 (standard ST40 physical boot address) 0x1B000000 EMI EMI control registers 0x07F00000 0x08000000 System peripherals LMI 0x0F000000 0x10000000 LMI control registers Reserved 0x1BFFFFFF 0x1C000000 PCI 0x17000000 0x18000000 0x1C000000 PCI control registers Reserved Area 7 0x1FFFFFFF Core peripherals 0x1F000000 0x1FFFFFFF Memory address space Device control register address space Reserved address space Figure 2: System address organization 12/88 4 System configuration 4.1.1 System address map Addressa Module Base Standard bus interfaces EMI (FMI) EMI control registers LMI LMI control registers PCI PCI control registers Reserved 0x00000000 0x07F00000 0x08000000 0x0F000000 0x10000000 0x17000000 0x18000000 0x07EFFFFF 0x07FFFFFF F 0x0EFFFFFF 0x0FFFFFFF 0x16FFFFFF 0x17FFFFFF 0x1AFFFFFF ST40RA166 Reference Top ST40 System Architecture Manual Volume 2: Bus Interfaces Table 1: ST40RA166 system address map (page 1 of 2) ST40 core peripherals DMAC PIO1 PIO2 PIO3 CLOCKGEN Interconnect Reserved CLOCKGENB Reserved 0x1B000000 0x1B010000 0x1B020000 0x1B030000 0x1B040000 0x1B050000 0x1B060000 0x1B100000 0x1B110000 0x1B00FFFF 0x1B01FFFF 0x1B02FFFF 0x1B03FFFF 0x1B04FFFF 0x1B05FFFF 0x1B0FFFFF 0x1B10FFFF 0x1B12FFFF ST40 System Architecture Manual Volume 1: System EMPI MPXARB 0x1B130000 0x1B138000 0x1B137FFF 0x1B13FFFF ST40 System Architecture Manual Volume 2: Bus Interfaces ST40 System Architecture Manual Volume 2: Bus Interfaces ST40 Architecture Manual Volume 4: I/O Devices ST40RA166 additional peripherals MailBox SYSCONF Reserved 0x1B150000 0x1B190000 0x1B1A0000 0x1B15FFFF 0x1B19FFFF 0x1B1FFFFF Reserved for additional peripherals Reserved ST40 core peripherals INTC2 0x1E080000 0x1E0FFFFF 0x1B200000 0x1B3FFFFF ST40 Architecture Manual Volume 1: System 13/88 ST40RA166 4 System configuration Addressa Module Base Reserved: CPU only registers CPG RTC INTC TMU SCIF1 SCIF2 EMU Reserved 0x1E100000 0x1FC00000 0x1FC80000 0x1FD00000 0x1FD80000 0x1FE00000 0x1FE80000 0x1FF00000 0x1FF80000 Reference Top 0x1FBFFFFF 0x1FC79999 0x1FCFFFFF 0x1FD79999 0x1FDFFFFF 0x1FE79999 0x1FEFFFFF 0x1FF79999 0X1FFFFFFF Table 1: ST40RA166 system address map (page 2 of 2) a. For information about which address region to access for each module, see SH-4 32-bit CPU Core Architecture, sections 2.5 and 3.4. When operating in privilege mode, these registers should be accessed via the P2 region by adding an offset of 0xA000 0000, when operating in user mode, access should be via the U0 address. 4.2 System identifiers q q q q SH-4 core processor identity: 0x0100. SH-4 core processor version: 0x0541D. ST40RA166-HC8 TAP identity: 05141041. ST40RA166-HC8 PCI identity: Vendor: 104A, Device: 4000, Revision ID: 0x01, Class: 0x4 0000, Subsystem ID: 0x0000. 14/88 4 System configuration ST40RA166 4.3 Interrupt mapping For full details on the interrupt controller see ST40 Architecture Manual Volume 1:System. The mapping of the CPU interrupts is described in Section 4.3.1, Section 4.3.2 and Section 4.3.3. Note: Some INTEVT codes are shown as reserved in Table 2 and therefore cannot be generated by this device. 4.3.1 ST40 core interrupt allocation The allocation of core interrupts is as shown in Table 2. INTEVT code 0x1C0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 IRL3-IRL0 Interrupt priority Value 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 to 0 15 to 0 15 to 0 15 to 0 15 to 0 15 to 0 0 to 15 0 to 15 Interrupt source Initial value 13 10 7 4 0 0 0 0 IPR bit numbers IPRD[15:12] IPRD[11:8] IPRD[7:4] IPRD[3:0] IPRC[3:0] IPRA[15:12] IPRA[11:8] Priority within IPR setting unit High NMI IRL level encoding =F =E =D =C =B =A =9 =8 =7 =6 =5 =4 =3 =2 =1 0x200 0x220 0x240 0x260 0x280 0x2A0 0x2C0 0x2E0 0x300 0x320 0x340 0x360 0x380 0x3A0 0x3C0 0x240 0x2A0 0x300 0x360 0x600 0x400 0x420 0x440 IRL independent encoding IRL0 IRL1 IRL2 IRL3 H-UDI TMU0 TMU1 TMU2 H-UDI TUNI0 TUNI1 TUNI2 TICPI2 IPRA[7:4] 0x460 Low Table 2: ST40 core interrupt allocation (page 1 of 2) 15/88 ST40RA166 4 System configuration Interrupt source INTEVT code 0x480 0x4A0 0x4C0 0x4E0 0x500 Interrupt priority Value Initial value IPR bit numbers Priority within IPR setting unit High RTC ATI PRI CUI 0 to 15 0 IPRA [3:0] to low SCIF1 ERI RXI BRI TXI High 0 to 15 0 IPRB[7:4] to low 0x520 0x540 0x700 0x720 0 to 15 0 IPRC[7:4] SCIF2 ERI RXI BRI TXI High to low 0x740 0x760 0x560 0 to 15 0 IPRB[15:12] WDT ITI - Table 2: ST40 core interrupt allocation (page 2 of 2) 4.3.2 ST40 standard system interrupt allocation Standard ST40 family interrupts are mapped as shown in Table 3. INTEVT code 0xA00 0xA20 0xA40 0xA60 0 to 15 0 INTPRI00[0:3] INTPRI00[7:4] PCI_PWR_DWN Interrupt priority Value Initial value Interrupt source IPR bit numbers Priority within IPR setting unit High to low High to low PCI PCI_SERR_INT PCI_ERR_INT PCI_AD_INT Reserved DMAC DMA_INT0 DMA_INT1 DMA_INT2 DMA_INT3 DMA_INT4 0xB00 0xB20 0xB40 0xB60 0xB80 0 to 15 0 INTPRI00[11:8] High to low Reserved DMA_ERR 0xBC0 0xC00 0xC80 0xD00 0 to 15 0 to 15 0 to 15 0 0 0 INTPRI00[15:12] INTPRI00[19:16] INTPRI00[23:20] PIO0 PIO1 PIO2 PIO0 PIO1 PIO2 - Table 3: ST40 standard interrupt allocation 16/88 4 System configuration 4.3.3 ST40RA166 I/O device interrupt allocation INTEVT code 0x1000 0 to 15 Reserved Reserved EMPI INV_ADDR ST40RA166 Interrupt priority Value Initial value 0 0 0 Interrupt source IPR bit numbers Priority within IPR setting unit High to low High to low High to low Mailbox MAILBOX INTPRI04[0:3] 0 to 15 0x1380 0 to 15 Reserved INTPRI04[27:24] INTPRI04[31:28] Table 4: Mailbox and EMPI interrupt allocation 4.4 GPDMA channel mapping For full details of the GPDMA controller see ST40 Architecture Manual Volume 1: System. The ST40RA166 general purpose DMA controller channel map is shown in Table 5. Request number 0 1 Associated device External device 0 External device 1 Protocol DREQ or DREQ/DRACK DREQ or DREQ/DRACK Comment The following pins are available for external peripherals: DREQ[0:1], DACK[0:1], DRAK[0:1]. 2 and 3 4 5 6 7 8 9 and 10 11 12 13 14 15 to 31 Reserved SCIF1 transmit SCIF1 received SCIF2 transmit SCIF2 receive TMU Reserved PCI1 PCI2 PCI3 PCI4 Reserved DREQ or DREQ/DRACK DREQ or DREQ/DRACK DREQ or DREQ/DRACK DREQ or DREQ/DRACK DREQ DREQ DREQ DREQ DREQ/DRACK Typically used to trigger or pace memory transfers. This allow SCIF to memory and memory to SCIF transfer to be supported on any DMA channel. May be used to improve the efficiency of transfers to and from the PCI. Table 5: GPDMA request number allocation 17/88 ST40RA166 4 System configuration 4.5 EMI DACK mapping For full details of the EMI bank address and bank type mappings refer to ST40 Architecture Manual Volume 2: Bus Interfaces. Two DACK strobes are supported in this implementation and are mapped as follows: q DACK[0]: asserted when a transfer from GPDMA channel[1] occurs to an EMI bank configured as a MPX device, asserted when a transfer from GPDMA channel[2] occurs to an EMI bank configured as a MPX device. q DACK[1]: 4.6 EMI address pin mapping The data width of a connected device is 8, 16 or 32 bits wide. The 16-bit bank must use EDQM3 as address 1, the LSB address for the device and the 8-bit bank must use EDQM3 as address 1 and EDQM2 as address 0. See the ST40 System Architecture Manual, Volume 2: Bus Interfaces for details of setting the device type and port size using the EMI configuration registers. Device type SDRAM Peripheral Sflash 8-bit MPX EADDR[23:2] EADDR[25:2] EDQM3 EDQM2 Port size 32-bit 16-bit Device address 25 to 2 EADDR[25:2] EADDR[24:2] Device address 1 EDQM3 Device address 0 - - - Table 6: Mapping the internal address lines of a connected device 18/88 4 System configuration ST40RA166 4.7 Memory bridge control The architecture of the SuperHyway interconnect is shown in Figure 3. Initiators are shown on the left, and targets are shown on the right of the interconnect. The bit width of the initiator and target ports are shown in the diagram. 64 SH core 32 LMI EMPI Memory bridge 32 32 Memory bridge EMI PCI_ST_I Memory bridge 32 SuperHyway Interconnect 32 Memory bridge PCI_ST_T GPDMA PER 32 32 SH_PER P I Figure 3: ST40RA166 interconnect architecture The ST40RA166 architecture requires seven memory bridges on clock change boundaries. Memory bridge number 1 2 3 4 5 6 7 SuperHyway type T3 T3 T1 T2 T2 T3 T3 Subsystem EMI target EMPI initiator EMI_SS target Reserved Reserved PCI_ST_I PCI_ST_T Table 7: Memory bridges 19/88 ST40RA166 4.7.1 Memory bridge control signals Each memory bridge has seven control signals as defined in Table 8. Bridge control bit field 1:0 Control name MODE[1:0] 4 System configuration Control function 00: Sync (bypass) bridge 01: Semisync with no retime registers 10: Semisync with one retime register 11: Async with two retime registers 4:2 5 LATENCY[2:0] SW_RESET Sets FIFO latency from 0 to 7 cycles. 0: Software reset inactive 1: Software reset active 6 STROBE The above control signals are latched in the bridge on the rising edge of this strobe bit Table 8: Memory bridge control signals 4.7.2 Memory bridge status The memory bridge control signals are looped back to the ST40RA166 comms subsystem SYS_STAT1 register for test purposes. The format of this read-only register is shown in Section 4.8.4.1: SYSCONF.SYS_STAT1. on page 24. 4.7.3 Changing control of a memory bridge At reset all these bridges are set to be synchronous. After reset and boot the function of these memory bridges can be changed. See Section 4.8.4: SYSCONF registers on page 24. The procedure for changing the control of a memory bridge is given below. 1 2 3 4 Ensure no initiators are accessing the subsystem the bridge is connected to and ensure the subsystem cannot initiate any requests to the SuperHyway. Stop the clock to the subsystem. Change the memory bridge configuration using the SYS_CONF.SYS_CONF1 register as detailed in Table 8. Restart the clock to the subsystem and reinitialize the system. 20/88 4 System configuration ST40RA166 4.8 System configuration registers Table 9 outlines the ST40RA166 system configuration registers. Register EMI.GENCFG Module EMI LMI LMI SYSCONF SYSCONF SYSCONF SYSCONF SYSCONF SYSCONF SYSCONF Address offset 0x028 0x028 0x040 0x040 0x010 0x018 0x020 0x028 0x030 0x038 Type R/W R/W RO RO R/W R/W R/W R/W R/W R/W Description EMI general purpose configuration register, see page 22 LMI clock and pad control register, see page 23 LMI clock and pad status, see page 24 Memory bridge status, see page 24 System configuration register, see page 25 System configuration register, see page 25 System configuration register, see ST40 Architecture Manual Volume 4: I/O Devices System configuration register, see ST40 Architecture Manual Volume 4: I/O Devices System configuration register, see ST40 Architecture Manual Volume 4: I/O Devices System configuration register, see ST40 Architecture Manual Volume 4: I/O Devices LMI.COC LMI.CIC SYS_STAT1 SYSCONF.SYSCONF1 SYSCONF.SYSCONF2 SYSCONF.CNV_STATUS SYSCONF.CNV_SET SYSCONF.CNV_CLEAR SYSCONF.CNV_CONTROL Table 9: System configuration registers 21/88 ST40RA166 4.8.1 EMI.GENCFG EMI general configuration EMI.GENCFG EMI general configuration 4 System configuration 0x0028 The EMI provides a generic register to allow the configuration of the padlogic. ST40RA166 uses the bits detailed. 0 SOFE Strobe positioning Strobe on falling edge: 0: Disabled 1: Enabled Reset: 0 RW [5:1] SDPOS SDRAM bank location 00001: Bank 0 00011: Bank 2 00101: Bank 4 10001: Bank 0 to 1 10011: Bank 0 to 3 10101: Bank 0 to 5 10111: Bank 1 to 3 11001: Bank 1 to 5 11011: Bank 2 to 4 11101: Bank 3 to 4 11111: Bank 4 to 5 Reset: 0 00010: Bank 1 00100: Bank 3 00110: Bank 5 10010: Bank 0 to 2 10100: Bank 0 to 4 10110: Bank 1 to 2 11000: Bank 1 to 4 11010: Bank 2 to 3 11100: Bank 2 to 5 11110: Bank 3 to 5 RW 6 EWPU Pull-up on EWAIT pina 0: Disabled 1: Enabled Reset: 0 RW 7 EAPU Pull-up enable on EADDR pins 0: Disabled 1: Enabled Reset: 0 RW [31:8] Reserved 0: Ignored 1: Reserved Reset: Undefined a. If the EWAIT signal is set at the beginning of an access, and the data is to be set after the EWAIT is cleared, the parameters ACCESSTIMEREAD and LATCHPOINT in the EMI configuration registers must be set as follows: ACCESSTIME > LATCHPOINT + 3. See the ST40 System Architecture Manual, Volume 2: Bus Interfaces for details of setting the EMI configuration registers. 22/88 4 System configuration 4.8.2 LMI.COC LMI.COC LMI clock and pad control ST40RA166 0x028 LMI.COC allows modification of the glue logic. 0 DLY_SRC Delay line control source 0: DLL provides delay line control 1: LMI.CFG[5:1] provides delay line control Reset: 0 RW [5:1] DLY_NUM Number of delays (~200ps each) Reset: 0 RW [7:6] DLY_FRQ_RES External delay frequency resolution Reset: 0 RW 19:8] PLL_SETUP PLL setup Reset: 0 RW [21:20] DLL_PRO_CON DLL programmer control Reset: 0 RW 22 FRQ_RES_SRC Frequency resolution source of external delay 0: DLL provides frequency resolution 1: LMI.CFG[7:6] provides frequency resolution Reset: 0 RW 23 PLL_SETUP PLL setup Reset: 0 RW 24 DLL_PRO_SRC DLL programmer source 0: Delay programmer block provides DLL programming 1: LMI.CFG[21:20] provides DLL programming Reset: 0 RW [30:25] 31 Reserved DLL_ENB DLL enable Reset: 0 RW 23/88 ST40RA166 4.8.3 LMI.CIC LMI.CIC LMI clock and pad status 4 System configuration 0x040 LMI.CIC reflects the status of the glue logic. [4:0] 5 6 [8:7] [21:9] [24:22] [26:25] [31:27] DLY_STATE DLL_LOCK PLL_LOCK DLL_STATE PLL_SETUP_STATE DLL_SETUP_STATE DLL_BYPASS LMI_SETUP DLL delay state DLL lock signal PLL lock signal DLL state PLL setup state DLL setup state DLL bypass state LMI.CFG setup for external delay RO RO RO RO RO RO RO RO 4.8.4 SYSCONF registers All ST40 systems contain a number of general purpose configuration registers which may be used to configure system logic. The definition of the general registers and their access functions is defined in the ST40 System Architecture Manual. For ST40RA166 the bits within these registers have the following function. 4.8.4.1 SYSCONF.SYS_STAT1. SYS_STAT1 [3:0] [10:4] [17:11] [24:18] [31:25] [38:32] [45:39] [52:46] [63:53] Reserved STATUS1 STATUS2 STATUS3 STATUS4 STATUS5 STATUS6 STATUS7 Memory bridge status 0x0040 Status memory bridge 1 Status memory bridge 2 Status memory bridge 3 Status memory bridge 4 Status memory bridge 5 Status memory bridge 6 Status memory bridge 7 RO RO RO RO RO RO RO Reserved 24/88 4 System configuration 4.8.4.2 SYSCONF.SYSCONF1. SYSCONF.SYSCONF1 [3:0] [10:4] [17:11] [24:18] [38:25] [45:39] [52:46] [63:53] Reserved MB1 MB2 MB3 ST40RA166 Memory bridge control 0x010 RW Memory bridge 1 control: EMI target Memory bridge 2 control: EMPI initiator Memory bridge 3 control: EMI_SS target RW RW RW Reserved MB6 MB7 Memory bridge 6 control: PCI initiator Memory bridge 7 control: PCI target RW RW Reserved Where the two clocks are sourced from independent PLLs the bridge must be put in asynchronous mode. 4.8.5 SYSCONF.SYSCONF2. SYSCONF.SYS_CON2 Functional pin use and behavior 0x0018 The SYSCONF.SYS_CON2 register controls functional pin use and behavior LMI pad type 8 LMI_MODE RW 0: SSTL 1: LVTTL Reset: 0 Reference voltage source RW 9 LMI_ENVREF 0: internally generated reference voltage 1: external reference voltage from VREF pins Reset: 0 LMI control signal ECLK180 retime bypass RW 10 LMI_ECLK_BYPASS 0: ECLK180 flip flop not bypassed 1: ECLK180 flip flop is bypassed Reset: 0 Enable LMI 2.5 V compensation cell RW 11 LMI_NOTCOMP25_EN 0: LMI 2.5 V compensation cell enabled 1: LMI 2.5 V compensation cell disabled Reset: 0 Enable LMI 3.3 V compensation cell RW 12 LMI_COMP33_EN 0: LMI 2.5 V compensation cell enabled 1: LMI 2.5 V compensation cell disabled Reset: 0 Table 10: 25/88 ST40RA166 4 System configuration SYSCONF.SYS_CON2 Functional pin use and behavior sdram data and data strobe pad PROG 1:0 LVTTL OP drive strength 0x0018 RW [13:14] LMI_SDRAM_DATA_DRIVE 00: 1x 01: 2x 10: 3x 11: 4x Reset: 0 LMI address and control pad PROG 1:0 LVTTL OP drive strength RW [15:16] LMI_SDRAM_ADD_DRIVE 00: 1x 01: 2x 10: 3x 11: 4x Reset: 0 [17:35] Reserved Enable EMPI channel 0 DREQ/DRACK/DRACK alternate function 0: Disabled 1: NOTESCS1 remapped to EMPIDREQ0 EMPI_ENB[0] NOTESCS2 EADDR26 RW 36 remapped to EMPIDRAK0 remapped to EMPIDACK0 EADDR26 is only remapped when whilst the ST40RA166 is acting as a bus slave Enable EMPI channel 1 DREQ/DRACK/DRACK alternate function 0: Disabled 37 1: NOTPREQ3 remapped to EMPIDREQ1 EMPI_ENB[1] NOTPGNT3 EADDR25 RW remapped to EMPIDRAK1 remapped to EMPIDACK0 EADDR25 is only remapped when whilst the ST40RA166 is acting as a bus slave Enable EMPI channel 2 DREQ/DRACK/DRACK alternate function 0: Disabled 38 EMPI_ENB[2] RW 1: DREQ0 remapped to EMPIDREQ2 DACK0 remapped to EMPIDACK2 DRAK0 remapped to EMPIDRAK2 Enable EMPI channel 2 DREQ/DRACK/DRACK alternate function 0: Disabled 39 EMPI_ENB[3] RW 1: DREQ1 remapped to EMPIDREQ3 DACK1 remapped to EMPIDACK3 DRAK1 remapped to EMPIDRAK3 Enable mailbox interrupt alternate function RW 40 MAILBOX_ENB 0:Disabled 1:notESC0 remapped to MBXINT Table 10: 26/88 4 System configuration ST40RA166 SYSCONF.SYS_CON2 [41:43] Reserved Functional pin use and behavior 0x0018 Enable EMPI chip selection alternate function 000: NOTESC0 remapped to NOTEMPICS 001: NOTESC1 remapped to NOTEMPICS 010: NOTESC2 remapped to NOTEMPICS [44:46] EMPI_CS_ENB RW 011: NOTESC3 remapped to NOTEMPICS 100: NOTESC4 remapped to NOTEMPICS 101: NOTESC5 remapped to NOTEMPICS 110: Reserved 111: Disabled (value at reset) Select EMI slave or master functionality RW 47 SEL_EXT_EMI_SLAVE 0: EMI is bus master 1: EMI is bus slave [48:59] [60:63] Reserved PIO_CONF PIO_CONF RW Table 10: 4.8.6 PIO alternate functions The function of pads with PIO alternate functions are controlled by the PIO.PC0, PIO.PC1 and PIO.PC2 registers. In the ST40RA166 device, the operational modes for these registers differ from the standard architecture definition and are shown in Table 11. PIO bit configuration NonPIO functiona PIO bidirectional PIO output PIO bidirectional PIO input PIO input Reserved Reserved Open drain Push-pull Open drain High impedance High impedance - PIO output state 0 0 0 0 1 1 1 1 PIO.PC2 0 0 1 1 0 0 1 1 PIO.PC1 0 1 0 1 0 1 0 1 PIO.PC0 Table 11: PIO alternate function registers a. State following reset 27/88 ST40RA166 4.8.7 PCI.PERF register definition. PCI.PERF PCI.PERF modifies the function of the PCI. [3:0] DLY_PERRSAMPLE 5 Clock generation 0x0080 Parity error delay Number of app_clock cycles after end of PCI that access master should wait to see if there is a parity error RW 4 5 [31:6] ENB_WRITEPOST ENB_STBYBYPASS Enable write posting in master Enable standby bypass RW RW Reserved 5 Clock generation The ST40 clock architecture has been organized to maintain compatibility across the ST40 family and allow additional flexibility to increase system performance where required. It includes a more diverse range of peripherals and provides low power use. 5.1 Clock domains and sources Figure 4 shows possible clock domains for ST40RA166 clocks. The ST40RA166 implementation includes two CLOCKGEN macros, which supply up to three independent clock domains across the chip Each PLL may be independently programmed to produce a clock at a specific frequency which is used to derive a series of related clocks which may be used by the system. The clock domains mapping is shown in Table 12. The architecture of the ST40RA166 CLOCKGEN subsystem consists of two standard (ST40 family) CLOCKGEN units (CLOCKGENA and 28/88 5 Clock generation ST40RA166 CLOCKGENB) and a CLOCKCON block. Figure 5 shows the architecture of the ST40RA166 CLOCKGEN subsystem. STBUS_CLK (X_BCK) SuperHyway CPU_CLK PER_CLK (X_ICK) (X_PCK) SH-4 CPU core SH-4 core peripherals STBUS_CLK LMI LMI int DLL CLK SDRAM or DDR memory LMI_CLK 27 MHz XTAL CLOCKGEN subsystem EMI_SS_CLK EMI subsystem CLK Flash. MPX bus, SDRAM PCI_SS_CLK PCI subsystem PCI int. PCI bus PCI_BUS_CLK CLK See CLOCKGENA.PLL1 clock domains See CLOCKGENA.PLL2 clock domains See CLOCKGENB.PLL1 clock domains Figure 4: ST40RA166 clock domains 29/88 ST40RA166 5 Clock generation Subsystem CPU core SuperHyway Clock domain CPU_CLK STBUS_CLK Target frequencies (MHz) 200 100 166 111 83 55 42 150 100 75 50 38 133 88 67 44 33 Sourcea CLOCKGEN_A11 CLOCKGEN_A12 Ratio 1 2/3 1/2 Peripherals PER_CLK 50 33 66 25.14 CLOCKGEN_A13 1/3 1/4 (CPU core PCK) PCI bus clock PCI_BUS_CLK CLOCKGEN_A21 CLOCKGEN_A22 CLOCKGEN_A23 CLOCKGEN_A24 100 75 50 38 100 88 67 44 33 88 CLOCKGEN_A14 CLOCKGEN_B11 CLOCKGEN_B12 100 75 88 67 CLOCKGEN_A12 CLOCKGEN_A14 CLOCKGEN_A13 CLOCKGEN_A12 1/16 1/8 1/21 2/3 1/2 1/3 1/4 2/3 1 1 2/3 1/2 Disabled PCI subsystem PCI_SS_CLK 100 50 111 83 55 42 111 Local memory interface (LMI) EMI subsystem LMI_CLK 133 Reserved EMI_CLK 50 to 100 MHz 100 111 83 Table 12: Clock domains a. Clock naming: CLOCKGEN_[CLOCKGEN label][PLL number][clock number] The sources for PCI_SS_CLK and EMI_SS_CLK, can be set using the PCI_SEL and EMI_SEL bits in the CLOCKGENB.CLK_SELCR register. See Section 5.6.1: CLOCKGENB.CLK_SELCR register on page 36. If CLOCKGEN_A13 is used as PCI_SS_CLK source then the memory bridges 6 and 7 must be enabled. If CLOCKGEN_A12 is used, then the bridges may be placed in bypass mode. This is the recommended mode of operation. If either CLOCKGEN_B12 or CLOCKGEN_A14 are used as the EMI_CLK, the memory bridges 1, 2 and 3 must be enabled. If CLOCKGEN_A12 is used, then the bridges may be placed in bypass. This is the recommended mode of operation. See Chapter 4.7: Memory bridge control on page 19. 30/88 5 Clock generation ST40RA166 27 MHz XTAL ST40RA166 ST40RA166 CLOCKGEN subsystem CPU core ST40 CLOCKGENA 1 PLL1 PLL1 2 3 4 CLOCKCON CPU_CLK (X_ICK) (X_BCK) Control STBUS_CLK PER_CLK (X_PCK)) LPU T1 PCI_BUS_CLK 1 Control (external) Select 0 1 PCI_SEL PLL2 PLL2 2 3 4 5 PCI_SS_CLK 00 01 10 11 EMI_SEL EMI_SS_CLK ST40 CLOCKGENB 1 PLL1 PLL1 2 3 4 0 1 LMI_SEL LMI_CLK Control LPU T1 1 SuperHyway Control PLL2 2 3 4 5 CLK_SEL[3:0] Figure 5: ST40RA166 CLOCKGEN subsystem 31/88 ST40RA166 5 Clock generation 5.2 Recommended operating modes PLL frequency (MHz) PLLA PLLB CPU_ CLK ST40RA166 clock domain frequencies (MHz) Mode for CLOCKGENA and CLOCKGENB PLLA (mode) PLLB (mode) STBUS_ CLK PER_ CLK LMI_ CLK EMI_SS_ CLK PCI_SS_ CLK Recommended reset configuration 0 200 100 50 25 50 50 50 Alternate reset configuration 1 2 3 266 300 332 133 150 166 88 100 111 44 50 66 88 100 111 88 100 111 88 100 111 Recommended operating modes 2 3 300 332 150 166 100 83 100 83 100 83 100 83 100 83 Low power configuration with clocks enabled (programmable after reset) A6 bypass 27 13.5 6.75 6.75 6.75 6.75 6.75 Table 13: Supported operating frequencies 5.3 Reset mode Clocks and registers at start up Reset mode MODE[2:0] 000 001 010 011 100 101 110 111 CLOCKGENA .PLL1CR1 reset value 0x7939 8612 0x7939 B112 0x7938 6412 0x7938 7B14 0x7938 8612 0x7938 A712 0x0938 0000 0x0939 8612 CLOCKGENA core frequency (PLL1) 200 MHz 266 MHz 300 MHz 332 MHz 400 MHz 500 MHz 0 MHz 200 MHz CLK1 fPLL/2 CPU_ CLK 1 1 1 1 1 1 1 1/2 CLK2 STBUS_ CLK 1/2 2/3 2/3 2/3 1/2 1/2 1/2 1/4 CLK3 PER_ CLK 1/4 1/3 1/3 1/3 1/4 1/4 1/2 1/4 CLK4 LMI_ CLK 1/2 2/3 2/3 2/3 1/2 1/2 1/2 1/4 0 1 2 3 4 5 6 7 100 133 150 166 200 250 0 100 Table 14: CLOCKGENA PLL1 reset values 32/88 5 Clock generation 5.3.1 CLOCKGENA_2x PCI (PCI_DIV_BYPASS = 0) Reset mode MODE[4:3] 00 01 10 11 ST40RA166 Reset value 0x7938 B012 0x7938 B012 0x7938 B012 0x0938 B012 PLL2 frequency 528 MHz 528 MHz 528 MHz 0 MHz Table 15: CLOCKGENA PLL2 reset values (PCI_DIV_BYPASS = 0) 5.3.2 Division ratios on CLOCKGENA_2x Mode MODE[4:3] 00 01 10 11 Divide ratio selected 8 16 21 - PCI_BUS_CLK freq. 66 MHz 33 MHz 25.14 MHz 0 MHz Table 16: CLOCKGENA_PLL2 PCI reset division ratios. 5.4 Setting clock frequencies Table 17 shows valid FRQCR ratios and the associated clock frequencies for derived clocks. CLOCKGENA.FRQCR and CLOCKGENB.FRQCR Lower 9 bit 0x000 0x002 0x004 0x008 0x00A 0x00C 0x011 0x013 0x01A 0x01C 0x023 MODE1 MODE[2:3] MODE6 MODE[4:5] ST40RA166 codified ratios CPU_ CLK BUS_ CLK PER_ CLK 1/2 1 1 1/4 1/8 1 1/2 1/2 1/4 1/2 2/3 2/3 1 1/2 1/8 1/6 1/3 1/4 1/8 1 2/3 1/3 1 1 1 1 1 1 1 Clock ratios CPU_ CLK 1 1 1 1 Available on start up BUS_ CLK 1 1 1 1/2 1/2 1/2 2/3 2/3 1/2 1/2 2/3 PER_ CLK 1/2 1/4 1/8 1/2 1/4 1/8 1/6 1/3 1/4 1/8 1/3 MODE0 Table 17: Valid FRQCR values and their ratios 33/88 ST40RA166 5 Clock generation CLOCKGENA.FRQCR and CLOCKGENB.FRQCR Lower 9 bit 0x02C 0x048 0x04A 0x04C 0x05A ST40RA166 codified ratios CPU_ CLK BUS_ CLK 1/2 Clock ratios CPU_ CLK 1 1 1 1 1 1 1 1 Available on start up PER_ CLK 1/8 1/4 BUS_ CLK 1/2 1 1 1 2/3 1/2 1/2 1 1/2 1 1/2 1 1/2 PER_ CLK 1/8 1/2 1/3 1/4 1/6 1/2 1/4 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/3 1/6 1/8 1/6 1/4 1/8 0x05C 0x063 0x06C 0x091 1/3 0x093 0x0A3 0x0DA 1/4 0x0DC 0x0EC 0x123 0x16C 1/4 1/8 1/4 1/8 1/8 1 1 1 1 1/3 1/6 1/6 1 MODE7 1/2 1/2 1/4 Table 17: Valid FRQCR values and their ratios 5.4.1 Programming the PLL output frequency The three dividers used within the PLL are referred to as M (predivider), N (feedback divider) and P (postdivider) for brevity. Note that there is a divide-by-2 fixed prescaler before the feedback divider. The binary values applied to the programmable dividers, and the frequency of CLOCKIN controls the output frequency of the PLL macrocell: 2xN F ( clockout ) = ------------------ x F ( clockin ) M x 2P where the values of M, N and P must satisfy the following constraints: q Divider limits: 1 M 255, 1 N 255, 0 P 5 , F ( clockin ) Phase comparator limits: 1MHz ---------------------------- 2MHz , M 2xN VCO limit: 200MHz ------------- x F ( clockin ) 622MHz , M * M divider limit: F ( clockin ) 200MHz . q q q For example, if 300 MHz from an input clock of 33 MHz is to be generated, the values of M, N and P are worked out as below. 34/88 5 Clock generation 1 2 ST40RA166 The phase comparator must operate between 1 MHz and 2 MHz, so choose M = 22 (for 1.5 MHz operation). The VCO needs to run between 200 MHz and 622 MHz. It could be run at 300 MHz directly (which takes a little less current), or at 600 MHz then divide by 2 to ensure an exact 50% duty cycle. In this example 600 MHz is chosen so N = 200. The postdivider then needs to be a divide by 2. This is programmed in powers of 2, so P = 1. 3 The P divider changes value without glitching of the output clock. 5.4.2 Changing clock frequency The clock frequencies are changed in two ways. q Change the core PLL frequencies. The PLL must be stopped, the control register reconfigured with the new settings, and the PLL restarted at the new frequency. q Change the frequency division ratio of the clock domains. The control registers are changed dynamically and the new frequencies are effective immediately. 5.4.3 Changing the core PLL frequencies This procedure applies to either CLOCKGENA or CLOCKGENB and to PLL1 or PLL2. 1 2 3 Stop the PLL. The CLOCKGENA.PLL1CR2.STBPLLENSEL register selects whether the PLL is enabled by the CLOCKGENA.PLL1CR2.STBPLLEN or the CPG.FRQCR.PLL1EN register. Reconfigure the PLL. Set the CLOCKGENA.PLL1CR1 register to one of the supported configurations on the datasheet. Restart the PLL, following the procedure described in the ST40 System Architecture Volume 1: System. 5.4.4 Changing the frequency division ratio The frequency division ratio is selected by changing the CPG.FRQCR register for PLL1 or the CLOCKGENA.PLL2_MUXCR register for PLL2. This change is immediately effective. 5.5 Power management The power management unit (PMU) is responsible for clock startup and shutdown for each of the on-chip modules. Power is conserved by powering down those modules which are not in use, or even the CPU itself. The PMU is operated using three banks of registers as follows: q CPG: controls the power-down mode of the CPU and the power-down states of the legacy on-chip peripherals, and CLOCKGENB: control the power-down states of the other on-chip peripherals. q CLOCKGENA 5.5.1 CPU low-power modes The CPU can be put into sleep or standby modes. In sleep mode the CPU is halted while the on-chip peripherals continue to operate. In standby mode all the on-chip peripherals are stopped along with the CPU. In addition, the on-chip peripherals can be independently stopped. 35/88 ST40RA166 5 Clock generation Power down is initiated with the sleep instruction and the power down mode is selected with bit 7 of the CPG.STBCR register. If the bit is set, the CPU enters standby mode on the next sleep instruction, and if unset it enters sleep mode. 5.5.2 Module low-power modes Modules are powered down in two ways, depending on whether the module is a ST40 legacy peripheral (controlled by the CPG register bank) or a ST40RA166 peripheral (controlled by the CLOCKGEN register banks). A module controlled by the CPG register bank has its clock stopped when the corresponding bit in the CPG.STBCR or CPG.STBCR2 register is set. The clock is started again when the bit is cleared. To request the power down of a module controlled by the CLOCKGENA or CLOCKGENB register bank, 1 is written to the corresponding bit in the STBREQCR_SET register. When the module has completed its power down sequence and its clock has been stopped, the corresponding bit in the STBACKCR register is set. To restart the module, 1 is written to the corresponding bit in the STBREQCR_CLR register. Note: The modules governed by the CLOCKGENB register bank do not support hardware-only power down and require software interaction to maintain data coherency before making a request to stop the module clock. 5.6 5.6.1 Clock generation registers CLOCKGENB.CLK_SELCR register CLOCKGENB.CLK_SELCR Clock source selection 0x0068 The CLKGENB.CLK_SELCR register controls the selection of clock domain clock sources 0 LMI_SEL Reserved Reset state: 0 Select PCI clock 1 PCI_SEL 0: PCI_SS_CLK from CLOCKGENA_12 1: PCI_SS_CLK from CLOCKGENA_13 Reset state: 0 Select EMI clock 00: EMI_SS_CLK from CLOCKGENA_12 [2:3] EMI_SEL 01: EMI_SS_CLK from CLOCKGENA_13 10: EMI_SS_CLK from CLOCKGENA_14 11: EMI_SS_CLK from CLOCKGENB_12 Reset state: 00 [4:7] [8:31] EXT_CLK_SEL Reserved Not used Reset state: 0000 Reset state: 0 RW RW RW 36/88 5 Clock generation 5.6.2 CPG.STBCR register CPG.STBCR Sleep or standby mode ST40RA166 0x0004 Select between sleep and standby modes when a sleep instruction is issued. SCIF1 standby 0 MSTP0 0: SCIF1 operates 1: SCIF1 clock stopped Reset state: 0 RTC standby 1 MSTP1 0: RTC operates 1: RTC clock stopped Reset state: 0 TMU standby 2 MSTP2 0: TMU operates 1: TMU clock stopped Reset state: 0 SCIF2 standby 3 MSTP3 0: SCIF2 operates 1: SCIF2 clock stopped Reset state: 0 4 MSTP4 Not used Reset state: 0 Peripheral module pull-up pin control Controls the state of peripheral module related pins in the high impedance state 0: Peripheral module related pin pull-up resistors are on 1: Peripheral module related pin pull-up resistors are off Reset state: 0 Peripheral module pin high impedence control Controls the state of peripheral module related pins in standby mode 0: Peripheral module related pins are in normal state 1: Peripheral module related pins go to high impedance state Reset state: 0 Standby 7 STBY 0: Transition to sleep mode on sleep instruction 1: Transition to standby mode on sleep instruction Reset state: 0 RW RW RW RW RW RW RW RW 5 PPU 6 PHZ 37/88 ST40RA166 5.6.3 5 Clock generation CLOCKGENA.STBREQCR and CLOCKGENB.STBREQCR registers CLOCKGENA.STBREQCR CLOCKGENB.STBREQCR Control power down requests 0x0018 This register gives direct access to the power down request register. Low power requests are made in the STBREQCR_SET register and cleared in the STBREQCR_CLR register. Power down requests for module [n] [0:7] REQ[0:7] Controls the power down state for module [n] Bit [n]: 0 Request module [n] to operate normally Bit [n]: 1 Request module [n] to power down Reset state: 0 0: No action 1: Undefined Reset state: Undefined RW [8:31] Reserved 5.6.4 CLOCKGENA.STBREQCR_SET and CLOCKGENB.STBREQCR_SET registers CLOCKGENA.STBREQCR_SET CLOCKGENB.STBREQCR_SET This register sets a low power request. Set power down request for module [n] [0:7] SET[0:7] Sets the power down request state for module [n] Bit [n]: 0 No action Bit [n]: 1 Set power down request Reset state: 0 0: No action 1: Undefined Reset state: Undefined WO Set power down requests 0x0020 [8:31] Reserved 5.6.5 CLOCKGENA.STBREQCR_CLR and CLOCKGENB.STBREQCR_CLR register CLOCKGENA.STBREQCR_CLR CLOCKGENB.STBREQCR_CLR Clear power down requests 0x0028 This register clears a low power request and recommences the clock supply to a module. Clear power down request for module [n] [0:7] CLR[0:7] Clears the power down request state for module [n] Bit [n]: 0 No action Bit [n]: 1 Clear power down request Reset state: 0 0: No action 1: Undefined Reset state: Undefined WO [8:31] Reserved 38/88 5 Clock generation 5.6.6 CLOCKGENA.STBACKCR and CLOCKGENB.STBACKCR register CLOCKGENA.STBACKCR CLOCKGENB.STBACKCR Current module power status ST40RA166 0x0030 This register indicates the current module power status Power down status for module [n] Indicates the current power down status of the module [n] Bit [n]: 0 Module [n] operating normally Bit [n]: 1 Module [n] powered down Reset state: 0 0: No action 1: Undefined Reset state: Undefined RO [0:7] ACK[0:7] [8:31] Reserved Table 18 defines the mapping of modules to bits in the STBREQ and STBACK registers. Bit number 0 1 2 3 4 5 6 7 CLOCKGENA mapping EMI LMI DMAC PCI PIO Reserved Reserved Reserved CLOCKGENB mapping Reserved Reserved Reserved Reserved Reserved Reserved PCI bus Reserved Table 18: STBREQ and STBACK mapping for modules 39/88 ST40RA166 6 Electrical specifications 6 6.1 Electrical specifications DC absolute maximum ratings Symbol VDDCORE VDDIO VDDRTC VIO VIORTC VIOCLK IO TS TA Parameter Core DC supply voltage I/O DC supply voltage RTC DC supply voltage Voltage on input, output and bidirectional pins. Voltage on input pins on VDDRTC supply (LPCLKIN, LPCLKOSC) Voltage on CLKIN and DC output current Storage temperature (ambient) Temperature under bias (ambient) -55 -55 CLKOSC Min 2.1 4.0 2.1 GND -0.6 GND -0.6 GND -0.6 Max Units V V V V V V mA deg C deg C Notes ab , VDDIO + 0.6 VDDRTC + 0.6 VDDCORE + 0.6 25 125 125 pins Table 19: Absolute maximum ratings a. Stresses greater than those listed under Table 19: Absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may effect reliability. b. All I/O pins are 3.3 V tolerant except CLKIN, LPCLKIN, CLKOSC and LPCLKOSC. 6.1.1 Fmax clock domains Function clock CPU_CLK STBUS_CLK PER_CLK LMI_CLK EMI_SS_CLK EMI_EXT PCI_EXT Fmax 166 MHz 100 MHz 50 MHz 100 MHz 100 MHz 100 MHz 66 MHz Table 20: Fmax clock domains 40/88 6 Electrical specifications 6.1.2 Operating conditions Symbol VDDCORE VDDIO VDDRTC VDDMM LVref VDDLMI 3.0 2.3 VIH VIL VIHs VILs VOH VOL VOHs VOLs IIN IOZ IWP CIN CIO LVTTL input logic 1 voltage LVTTL input login 0 voltage SSTT_2 input login 1 voltage SSTT_2 input login 0 voltage LVTTL output logic 1 voltage LVTTL output logic 0 voltage SSTT_2 output logic 1 voltage SSTT_2 output logic 0 voltage Input current (input pin) Offstate digital output current Input weak pull-up or pull-down current Input capacitance (input pins) Input capacitance (bidirectional pins) 7 30 60 tbc tbc +-10 +- 50 110 10 15 2.0 -0.5 tbc tbc 2.4 0.4 3.3 2.5 3.6 2.7 VDD + 0.6 0.8 tbc tbc ST40RA166 Parameter Core positive supply voltage I/O positive supply voltage RTC positive supply voltage VDD mismatch Min 1.65 3.0 1.65 Typical 1.8 3.3 1.8 Max 1.95 3.6 1.95 0.3 Units V V V V Notes a V V V V V V V V V V uA uA uA pF pF b c d 2 4 e 5 3 Table 21: Operating conditions a. VDDCORE - VDDRTC b. When in SDRAM mode c. When in DDR-SDRAM mode d. For specified output loads see Table 23. e. 0 <= VI <= VDD 41/88 ST40RA166 6 Electrical specifications VDDCORE Typical Operating Low power 850 5 VDDIO Units Typical 250 25 Maximum 1150 10 Maximum 350 50 mWa mW Table 22: Power dissipation a. CPU 166 MHz (Mode 3) 6.1.3 Pad specific output AC characteristics Pad type SL P8 C2A C2B C4 E4 EMI/MPX Functional pin group LMI SDRAM/DDR PCI 35 Maximum load (pf) 8 2 2 4 4 Drive (mA) a Notes 200 50 50 100 100 Table 23: I/O maximum capacitive and DC loading a. The SL pads are fully LVTTL and SSTL_2 compliant at maximum 35pf load. 42/88 6 Electrical specifications ST40RA166 Figure 6: Pads characteristics Note: 1.The SL pad type graph represents the maximum drive strength in the LVTTL mode. 43/88 ST40RA166 6 Electrical specifications 6.2 Rise and fall times Figure 7: Timings for C2A, C2B, E4 and C4 pad types 44/88 6 Electrical specifications ST40RA166 Figure 8: Timings for P8 and SL (LVTLL 00, 01 and 10) pad types 45/88 ST40RA166 6 Electrical specifications Figure 9: Timings for SL (LVTTL 11 and SSTL2) pad types 46/88 6 Electrical specifications ST40RA166 6.3 PCI interface AC specifications tPCIHPCIH PCLK tPCIHAOV Outputs tPCIHAON tPCIHAOZ Tri-state outputs tPCIHAIX tBIVPCIH Inputs: bussed tPIVPCIH Inputs : point-to-point Figure 10: PCI timings Symbol tPCIHPCIH tPCIHAOV tPCIHAOZ tPCIHAON tBIVPCIH tPIVPCIH tPCIHAIX PCI clock period PCLK PCLK PCLK Parameter Min 15 1 2 2 3 5 0 Max Units ns a Note high to all PCI output signals valid high to all PCI outputs tri-state high to all PCI outputs on 10 14 ns ns ns ns ns ns a, b a a c b Bused input signals valid to PCLK high Point-to-point input signals valid to PCLK high All PCI input signals hold after PCLK high Table 24: PCI AC timings a. Specified with 30 pF load b. Need to use 4 ns of the PCI propagation delay c. NOTPREQ[0:3] and NOTPGNT[0:3] are point to point signals and have different input setup times to bussed signals. All other synchronous signals are bussed. 47/88 ST40RA166 6 Electrical specifications 6.4 LMI interface (SDRAM) AC specifications tLCHLCH LCLKOUTA LCLKOUTB tLCHLCL tLCLLO V tLCLLCH Outputs tLCHLON tLCHLOZ Tri-state outputs tLCHLIX Inputs tLIVLCH Figure 11: LMI SDRAM mode timings Symbol tLCHLCH tLCHLCL tLCLLCH tLCHLOV tLCHLOZ tLCHLON tLIVLCH tLCHLIX LMI clock period LMI clock high time LMI clock low period LCLKOUT LCLKOUT LCLKOUT Parameter Min 10 0.45 0.45 -1.5 0 -2 1 2 Max Units ns tLCHLCH tLCHLCH Note low to output signals valid high to outputs tri-state high to outputs on 0.5 2 ns ns ns ns ns Input signals valid to LCLKOUT high Input signals hold after LCLKOUT high Table 25: LMI SDRAM AC timings 48/88 6 Electrical specifications ST40RA166 6.5 LMI interface (DDR-SDRAM) AC specifications tLCHLCL tLCHLCH NOTLCLKOUTA:B LCLKOUTA:B tLCLLCH tLCLLA V LMIADDR/COM tDQSH tLCHDQSR DQSREAD Inputs tDQSL tLCHDQSR tDQSRH tDQSRS LMIDATAREAD tDQSRH tDQSRS tLCHDQS DQS WRITE Outputs tDQSH tDQSL tLD S W LMIDATAWRITE tLD H W tLDW S tLDW H tLCHD Z W Figure 12: LMI DDR mode timings Symbol tLCHLCH tLCHLCL Parameter LMI clock period LMI clock high time 10 0.45 Min Max Units ns tLCHLC H Note Table 26: LMI DDR-SDRAM AC timings 49/88 ST40RA166 6 Electrical specifications Symbol tLCLLCH tLCHLAV tLCHDQSR tDQSH tDQSL tDQSRS tDQSRH tLCHDQS tLDWS tLDWH tLCHDWZ Parameter LMI clock low period LCLKOUT LCLKOUT Min 0.45 -1.5 -1.5 0.45 0.45 1 - tLCHLCH / 4 tLCHLCH / 4 + 1 N * tLCHLCH / 4 0.75 N * tLCHLCH / 4 0.75 N * tLCHLCH / 4 + 0.75 2 1.5 1.5 Max Units tLCHLCH ns ns tLCHLCH tLCHLCH ns ns Note low to address and command valid high to read DQS edge a DQS high DQS low Read data setup for DQS edge Read data hold for DQS edge LCLKOUT a a high to write DQS N * tLCHLCH / 4 + 0.75 ns Write data setup to DQS edge ns DQS edge to Write data invalid ns LCLKOUT high to write data Z ns Table 26: LMI DDR-SDRAM AC timings a. Constraint placed on external system 6.6 DDR bus termination (SSTL_2) The JEDEC specification for SSTL_2 and an application note from a DDR SDRAM manufacturer (DDR SDRAM Signaling Design Notes (MIcron Technology)) recommend the following layout to reduce signal reflections on the bus: DDR DDR RS RS ST40RA166 RS RT VTT VTT = 1.25 V (VDD / 2) RS = 27 RT = 27 Figure 13: SSTL_2 bus termination 50/88 6 Electrical specifications ST40RA166 6.7 General purpose peripheral bus (EMI) AC specifications tECHECH tECHCH tECLCL FCLKOUT ECLKOUT MCLKOUT tECHEOV tECHECL tRCLRCH Outputs switched on full cycle tECLEOV Outputs switched on 1/2 cycle tECHLON tECHLOZ Tri-state outputs tECHEIX tEIVECH Inputs tMWVECH tECHMWX Figure 14: EMI AC timings Symbol tECHECH tECHECL tECLECH tECHCH tECLCL tECHEOV tECLEOV tECHEOZ tECHEON tEIVECH tECHEIX Parameter EMI reference clock period EMI reference clock high time EMI reference clock low period EMI reference clock high to all clocks high EMI reference clock low to all clocks low EMI reference clock high to output signals valid EMI reference clock low to output signals valid EMI reference clock high to outputs tri-state EMI reference clock high to outputs on Input signals valid to EMI reference clock high Input signals hold after EMI reference clock high 4 2 Min 12 4 4 -1 -1 1 -1 0 0 Max Units ns ns ns ns ns ns ns ns ns ns ns 1 b 2 1 a Note 6.5 6.5 4 Table 27: EMI AC timings a. EMI reference clock is defined as the time when ECLKOUT, MCLKOUT and FCLKOUT are all valid. 51/88 ST40RA166 b. Including EWAIT signal 6 Electrical specifications 6.8 PIO AC specifications Reference clock in this case means the last transition of any PIO output signal within a bus, and hence is a virtual clock. PIO13:0 Symbol Parameter Min tPCHPOV tPCHWDZ tPIOr tPIOf tPIOr tPIOf PIO reference clock high to PIO output valid PIO tri-state after PIO reference clock high Output rise time Output fall time Input rise time Output rise time -5 -5 1 1 PIO23:14 Units Note Min -5 -5 1 1 Max 0 5 5 5 20 20 Max 0 5 5 5 5 5 ns ns ns ns ns ns b 2 a 1 Table 28: PIO timings a. No skew guarantee is made between the two separate PIO buses: PIO13:0 and PIO23:14 b. Loose input rise and fall times on PIO13:0 bus as these are schmitt trigger inputs. PIO reference clock tPCHPO V PIOOUT tPCHW DZ PIOOUT Figure 15: PIO AC timings 52/88 6 Electrical specifications ST40RA166 6.9 System CLKIN AC specifications The timings referenced in Figure 16 refer to the case where CLKIN is directly clocked from an external source. In this case care should be taken that the total load on the CLOCKOSC output is <2pF. Symbol tCLCH tCHCL tCLCL tCr tCf CLKIN CLKIN CLKIN CLKIN CLKIN Parameter pulse width low pulse width high period rise time fall time 6 6 Min Nom Max Units ns ns Notes 27 10 10 MHz ns ns a b, c 2, 3 Table 29: CLKIN timings a. Measured between corresponding points on consecutive falling edges. b. When driven by an external clock. c. Clock transitions must be monotonic within the range VIH to VIL. VDDCORE * 0.8 VDDCORE * 0.5 VDDCORE * 0.2 tCLCH tCLCL tCHCL 90% 10% 90% 10% tCf Figure 16: CLKIN timings tCr 53/88 ST40RA166 6 Electrical specifications 6.10 Low power CLKIN AC specifications The timings referenced in Figure 17 refer to the case where CLKIN is directly clocked from an external source. In this case care should be taken that the total load on the LPCLKOSC output is <2pF. . Symbol tLCLLCL LPCLKIN LPCLKIN Parameter period duty cycle rise time fall time Min Nom 32 Max Units kHz Notes a, b 10 50 90 10 10 % ns ns c, d 3, 4 tLCr tLCf LPCLKIN LPCLKIN Table 30: LPCLKIN timings a. Measured between corresponding points on consecutive falling edges. b. Variation of individual falling edges from their nominal times. c. When driven by an external clock. d. Transitions must be monotonic within the range VIH to VIL VDDRTC * 0.8 VDDRTC * 0.5 VDDRTC * 0.2 tLCLLCL 90% 10% 90% 10% tLCf Figure 17: CLKIN timings tLCr 54/88 6 Electrical specifications ST40RA166 6.11 UDI and IEEE 1149.1 TAP AC specifications Symbol tTCHTCH tDCHDCH tTIVTCH tTCHTIX tTCHTOV TCK DCK Parameter period period Min 50 50 5 5 Nom Max Units ns ns ns ns a b Notes TAP inputs setup to TCK/DCK high TAP input hold after TCK/DCK high TCK/DCK low to TAP output valid 10 ns Table 31: TAP timings a. During IEEE1149.1 drive board level manufacturing tests only TCK is active. b. During application level diagnostics only DCLK is active. tDCHDCH DCK tDCHTIX tTCHTCH TCK tTCHTIX TDI TMS tTIVTCH TDO tTCHTOV Figure 18: UDI and IEEE TAP timings 55/88 ST40RA166 7 Pin description 7 7.1 Pin description Function pin use selection Full details of the functional pin sharing are found in Section 7.3: PBGA 27 x 27 ballout on page 58. Functional pin group PCI request and grant Pins Alternate use(s) High-end interactive set-top box (with STi5514) example use PCI bus NOTPREQ[0:3] NOTPGNT[0:3] NOTPINTA PIO[14:23] PCI request and grant NOTPREQ[2:3] NOTPGNT[2:3] PIO[14:23] EMPIDREQ[0:1] EMPIDACK[0:1] PCI bus GPDMA handshake DACK[0:1] DREQ[0:1] DRAQ[0:1] PIO[8:13] EMPIDREQ[2:3] EMPIDACK[2:3] EMPIDRACK[2:3] GPDMA 2 x SCIF SCI2, CTS1 RXD0, RXD1 SCK0, SCK1 TXD0, TXD1 PIO[0:7] 2 x SCIF Table 32: ST40RA166 functional pin sharing summary 7.2 Mode selection During the power-on reset cycle a range of basic system configurations can be set up with resistive pull-ups or pull-downs. A detailed description of these selections is found in the relevant chapters of the ST40 System Architecture Manual. See Section 7.3: PBGA 27 x 27 ballout on page 58 for information on which pins these mode inputs have been placed on the ST40RA166. Mode pin MODE2:0 Pin name EADDR2 EADDR3 EADDR4 Architecture signal name MD2:0 Block affected CLOCKGEN Description Set system clock operating mode Notes a MODE4:3 EADDR5 EADDR6 MD4:3 CLOCKGEN Set PCI clock operating mode 1 MODE5 EADDR7 MD5 CLOCKGEN Set clock input source H: Crystal, L: External MODE6 EADDR8 MD6 CLOCKGEN Set enable CKIO Table 33: Mode selection pins for ST40RA166 56/88 7 Pin description ST40RA166 Mode pin MODE7 MODE8 Pin name EADDR9 EADDR10 Architecture signal name MD7 MD8 Block affected EMISS System Description Enable MPX arbiter Set endianess H: Little L: Big Notes MODE9 EADDR11 MD9 EMI Set EMI port H: Master L: Slave b MODE11:1 EADDR12 EADDR13 MD11:10 EMI Set booting ROM bus size 00: Reserved 01: 32-bit 10: 16-bit 11: 8-bit 0 MODE12 MODE13 EADDR14 EADDR15 MD12 MD13 EMI Reserved Enable NOP when accessing flash Tie high c d MODE14 EADDR16 MD14 PCI PCI bridge mode H: Host L: Satellite MODE15 EADDR17 MD15 PCI Reserved: PCI select clock H: External L: Internal e MODE16 MODE17 MODE18 MODE19 EADDR18 EADDR19 EADDR20 EADDR21 MD16 MD17 MD18 MD19 - Reserved: Tie high f Table 33: Mode selection pins for ST40RA166 a. See CLOCKGEN chapter of the ST40 System Architecture Manual for details. b. ST40RA166 is always the clock master, providing EMI clocks to the system. c. See EMI chapter of the ST40 System Architecture Manual for details. d. reserved for enable retiming stage on EMI padlogic e. PCI clock is selected externally on the board for ST40RA166. The mode pin may be used for clock selection in future variants. f. These mode pins are not used in current variants, however, they may be used to enable additional functionality in future variants 57/88 ST40RA166 7 Pin description 7.3 PBGA 27 x 27 ballout This should be used in conjunction with Figure 19: Package layout (viewed through package) on page 72. BPN Architecture signal name MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 Pin function Default Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Pin Alternate Type SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin name Row LDATA0 LDATA1 LDATA2 LDATA3 LDATA4 LDATA5 LDATA6 LDATA7 LDATA8 LDATA9 LDATA10 LDATA11 LDATA12 LDATA13 LDATA14 LDATA15 LDATA16 LDATA17 LDATA18 LDATA19 LDATA20 LDATA21 LDATA22 LDATA23 LDATA24 LDATA25 LDATA26 LDATA27 LDATA28 LDATA29 LDATA30 Col 17 17 18 18 19 19 20 20 13 13 14 14 15 15 16 16 7 7 8 8 9 9 10 10 3 3 4 4 5 5 6 Dir A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A Table 34: PBGA ballout for ST40RA166 (page 1 of 11) 58/88 7 Pin description ST40RA166 BPN Pin name Row LDATA31 LDATA32 LDATA33 LDATA34 LDATA35 LDATA36 LDATA37 LDATA38 LDATA39 LDATA40 LDATA41 LDATA42 LDATA43 LDATA44 LDATA45 LDATA46 LDATA47 LDATA48 LDATA49 LDATA50 LDATA51 LDATA52 LDATA53 LDATA54 LDATA55 LDATA56 LDATA57 LDATA58 LDATA59 LDATA60 LDATA61 LDATA62 LDATA63 LBANK0 Col 6 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 3 Architecture signal name MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 BA0 Pin function Default Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Memory data Mem bank address Pin Alternate Type SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O Dir B F F E E D D C C K K J J H H G G T T R R P P N N Y Y W W V V U U J Table 34: PBGA ballout for ST40RA166 (page 2 of 11) 59/88 ST40RA166 7 Pin description BPN Pin name Row LBANK1 LADDR0 Col 4 3 4 5 3 4 5 3 4 5 3 4 5 3 4 5 19 12 11 2 1 2 1 3 8 Architecture signal name BA1 MA0 Pin function Default Mem bank address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address Memory page/column address DDR data strobe DDR data strobe DDR data strobe DDR data strobe DDR data strobe DDR data strobe DDR data strobe DDR data strobe SDRAM clock output Pin Alternate Type SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL O O O O O O O O O O O O O O O O O O O O O O O O O Dir J G G G F F F E E E D D D C C C C B A B B L M W D LADDR1 MA1 LADDR2 MA2 LADDR3 MA3 LADDR4 MA4 LADDR5 MA5 LADDR6 MA6 LADDR7 MA7 LADDR8 MA8 LADDR9 MA9 LADDR10 MA10 LADDR11 MA11 LADDR12 MA12 LADDR13 MA13 LADDR14 MA14 LDQS0 LDQS1 LDQS2 LDQS3 LDQS4 LDQS5 LDQS6 LDQS7 LCLKOUTA DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 MCLKOA Table 34: PBGA ballout for ST40RA166 (page 3 of 11) 60/88 7 Pin description ST40RA166 BPN Pin name Row NOTLCLKOUTA LCLKOUTB NOTLCLKOUTB LVREF LDQM0 LDQM1 LDQM2 LDQM3 LDQM4 LDQM5 LDQM6 LDQM7 NOTLCSA0 NOTLCSA1 NOTLCSB0 NOTLCSB1 NOTLRASA NOTLRASB NOTLCASA NOTLCASB NOTLWEA NOTLWEB LCLKEN0 LCLKEN1 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 Col 7 3 3 5 20 12 11 2 1 1 2 3 9 9 3 4 8 4 7 4 6 5 6 3 17 18 19 20 17 18 19 20 17 18 Architecture signal name NOTMCLKOA MCLKOB NOTMCLKOB VREF DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 NOTCSA0 NOTCSA1 NOTCSB0 NOTCSB1 NOTRASA NOTRASB NOTCASA NOTCASB NOTWEA NOTWEB CKE0 CKE1 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 Pin function Default SDRAM clock output SDRAM clock output SDRAM clock output DDR reference voltage SDRAM data mask SDRAM data mask SDRAM data mask SDRAM data mask SDRAM data mask SDRAM data mask SDRAM data mask SDRAM data mask Chip select A Chip select A Chip select B Chip select B Row add strobe A Row add strobe B Column add strobe A Column add strobe B Write enable A Write enable B Clock enable Clock enable PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data Pin Alternate Type SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL SL P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 O O O I O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Dir D L M H C A B A A L M Y C D H H C K C L D J C K T T R R R R P P P P Table 34: PBGA ballout for ST40RA166 (page 4 of 11) 61/88 ST40RA166 7 Pin description BPN Pin name Row PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 NOTPCBE0 NOTPCBE1 NOTPCBE2 NOTPCBE3 PPAR NOTPFRAME NOTPIRDY NOTPTRDY NOTPSTOP NOTPERR NOTPSERR NOTPDEVSEL Col 19 20 17 18 19 20 17 18 19 20 17 18 19 20 17 18 19 20 17 18 17 18 16 16 16 16 16 19 20 17 19 17 18 18 Architecture signal name PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 PCI_PAR NOTPCI_FRAME NOTPCI_IRDY NOTPCI_TRDY NOTPCI_STOP NOTPCI_PERR NOTPCI_SERR NOTPCI_DEVSEL Pin function Default PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI address and data PCI com and byte enable PCI com and byte enable PCI com and byte enable PCI com and byte enable Parity signal PCI beginning access PCI initiator ready PCI target ready PCI req stop transfer PCI parity error PCI system error PCI device select Pin Alternate Type P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Dir N N N N M M K K J J J J H H H H G G G G F F P N K H M K K L L M M L Table 34: PBGA ballout for ST40RA166 (page 5 of 11) 62/88 7 Pin description ST40RA166 BPN Pin name Row PIDSEL NOTPRST NOTPLOCK PCLK NOTPREQ0 NOTPREQ1 Col 16 16 20 19 18 17 Architecture signal name PCI_IDSEL NOTPCI_RST NOTPLOCK PCI_CLK NOTPCI_REQ0 NOTPCI_REQ1 Pin function Default PCI initialization device PCI reset PCI exclusive access PCI clock input PCI external request for bus PCI external request for bus PIO16 PIO18 Pin Alternate Type P8 P8 P8 P8 P8 I/O I/O I I I/O I I/O I/O Dir J R L F E E NOTPREQ2 NOTPREQ3 F G 16 16 NOTPCI_REQ2 NOTPCI_REQ3 PCI external request for bus PCI external request for bus PIO20 PIO22 EMPIDREQ1 P8 P8 I I I/O I/O O NOTPGNT0 NOTPGNT1 NOTPGNT2 NOTPGNT3 D D E D 18 17 16 16 NOTPCI_GNT0 NOTPCI_GNT1 NOTPCI_GNT2 NOTPCI_GNT3 PCI grant external request PCI grant external request PCI grant external request PCI grant external request PIO17 PIO19 PIO21 PIO23 EMPIDRAK1 P8 P8 P8 P8 I/O O O O I/O I/O I/O I/O I PCLKOUT NOTPINTA DACK0 F T U 20 19 19 PCI_CLOCKOUT NOTPCI_INTA DACK0 PCI clock output PCI interrupt request DMA bus acknowledge PIO14 PIO15 PIO10 EMPIDACK2 P8 P8 C2A O I/O O I/O I/O I/O I DRAK0 U 18 DRACK0 DMA request acknowledge PIO9 EMPIDRAK2 C2A O I/O I DREQ0 V 20 DREQ0 DMA transfer request PIO8 EMPIDREQ2 C2A I I/O O DACK1 U 20 DACK1 DMA bus acknowledge PIO13 EMPIDACK3 C2A O I/O I DRAK1 T 20 DRACK1 DMA request acknowledge PIO12 EMPIDRAK3 C2A O I/O I DREQ1 U 17 DREQ1 DMA transfer request PIO11 EMPIDREQ3 C2A I I/O O SCI2 CTS1 RXD0 RXD1 SCK0 SCK1 TXD0 V V Y W Y W Y 19 18 19 20 18 18 20 RTS1/PIO7 CTS1/PIO6 RXD0/PIO1 RXD1/PIO4 SCK0/PIO0 SCK1/PIO3 TXD0/PIO2 SCI2 transmission request SCI2 transmission enabled SCI receive data input SCI receive data input SCI clock input SCI clock input SCI transmit data output PIO7 PIO6 PIO1 PIO4 PIO0 PIO3 PIO2 C2A C2A C2A C2A C2A C2A C2A O O I I I I O I/O I/O I/O I/O I/O I/O I/O Table 34: PBGA ballout for ST40RA166 (page 6 of 11) 63/88 ST40RA166 7 Pin description BPN Pin name Row TXD1 NOTRST IRL0 IRL1 IRL2 IRL3 NMI TMUCLK LPCLKIN LPCLKOSC VDDRTC CLKIN CLKOSC AUXCLKOUT Col 19 14 10 11 12 13 13 15 12 13 11 20 20 19 14 14 18 17 16 15 15 19 9 11 12 10 7 6 8 4 4 5 Architecture signal name TXD1/PIO5 NOTRESET IRL0 IRL1 IRL2 IRL3 NMI TCLK EXTAL2 XTAL2 VCCRTC CLKIN CLKOSC CKIO Pin function Default SCI transmit data output Power on reset Interrupt request signal Interrupt request signal Interrupt request signal Interrupt request signal Nonmaskable interrupt RTC output clock TMU input clock PIO5 Pin Alternate Type C2A C2B O I I I I I I I/O I O I C4 I O O O O O O O O O O I/O I I I I I O O O O I I I I/O Dir I/O W E C C C D C E E E E E D E C D C C C C D D E D D D E E E V U V RTC crystal resonator input: on VDDRTC supply RTC crystal resonator output: on VDDRTC supply Real-time clock supply System clock input: on VDDCORE supply Crystal resonator pin: on VDDCORE supply Reference 27 MHz clock output Processor operating status Processor operating status AUD bus command and data AUD bus command and data AUD bus command and data AUD bus command and data AUD command valid AUD clock output Dedicated emulator pin Clock for udi Test clock Test mode Test reset Test data input Test data output EMI external address EMI external address EMI external address MODE0 MODE1 MODE2 STATUS0 STATUS1 AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDSYNC AUDCLK NOTASEBRK STATUS0 STATUS1 AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDSYNC AUDCK NOTASEBRK/ BRKACK DCLK TCK TMS NOTTRST TDI TDO EADDR2 EADDR3 EADDR4 DCK TCK TMS TRST TDI TDO MA2 MA3 MA4 E4 E4 E4 Table 34: PBGA ballout for ST40RA166 (page 7 of 11) 64/88 7 Pin description ST40RA166 BPN Pin name Row EADDR5 EADDR6 EADDR7 EADDR8 EADDR9 EADDR10 EADDR11 EADDR12 EADDR13 EADDR14 EADDR15 EADDR16 EADDR17 EADDR18 EADDR19 EADDR20 EADDR21 EADDR22 EADDR23 EADDR24 EADDR25 EADDR26 EDATA0 EDATA1 EDATA2 EDATA3 EDATA4 EDATA5 EDATA6 EDATA7 EDATA8 EDATA9 EDATA10 EDATA11 Col 5 6 6 7 7 8 8 9 9 11 11 12 12 13 14 15 15 15 16 16 16 17 4 4 5 5 6 6 6 7 7 7 8 8 Architecture signal name MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 MA17 MA18 MA19 MA20 MA21 MA22 MA23 MA24 MA25 MA26 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 Pin function Default EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address EMI external address External data / MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address EMPIDACK1 EMPIDACK0 Pin Alternate Type E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I Dir I I I I I I I I I I I I I I I I I U U T U T U T U T V U V U U U V U T V U T V W Y W Y V W Y V W Y V W MODE3 MODE4 MODE5 MODE6 MODE7 MODE8 MODE9 MODE10 MODE11 MODE12 MODE13 MODE14 MODE15 MODE16 MODE17 MODE18 MODE19 Table 34: PBGA ballout for ST40RA166 (page 8 of 11) 65/88 ST40RA166 7 Pin description BPN Pin name Row EDATA12 EDATA13 EDATA14 EDATA15 EDATA16 EDATA17 EDATA18 EDATA19 EDATA20 EDATA21 EDATA22 EDATA23 EDATA24 EDATA25 EDATA26 EDATA27 EDATA28 EDATA29 EDATA30 EDATA31 ECLKOUT ECLKEN EDQM0 EDQM1 EDQM2 EDQM3 NOTECS0 NOTECS1 NOTECS2 NOTECS3 NOTECS4 NOTECS5 NOTERAS Col 8 9 9 9 11 11 12 12 13 13 13 14 14 14 15 15 16 16 17 17 10 10 4 4 5 5 4 4 5 12 13 14 3 Architecture signal name MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 ECLKOUT ECLKEN EBE_DQM0 EBE_DQM1 EBE_DQM2 EBE_DQM3 NOTECS5 NOTECS4 NOTECS3 NOTECS2 NOTECS1 NOTECS0 NOTERAS Pin function Default External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External data/MPX address External clock for SDRAM External clock enable External byte enables External byte enables External byte enables External byte enables External chip select External chip select External chip select External chip select External chip select External chip select External raw add strobe MSTART Pin Alternate Type E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 E4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O O O O O O O O I/O I Dir Y V Y W W Y W Y V W Y V W Y W Y W Y W Y W U N P P R R T T T T T U One NOTECS[0:5] used for NOTEMPICS Selected via software E4 E4 E4 E4 E4 E4 and E4 FLBADDR Table 34: PBGA ballout for ST40RA166 (page 9 of 11) 66/88 7 Pin description ST40RA166 BPN Pin name Row NOTECAS Col 3 Architecture signal name NOTECAS Pin function Default Alternate Type E4 Pin Dir O I/O T External column address strobe, MFRAME (MPX_FRAME) and EOE_N (EMI output enable signal) External wait command (notready) External read not write EMI pending refresh or access MPX clock MPX bus request MPX bus acknowledge Flash clock Flash bus address advance Reserved tri-state Reserved tri-state Reserved tri-state MBXINT EMPIDREQ0 EMPIDRAK0 EWAIT T V N Y R P V N L M M 10 3 3 10 3 3 10 5 5 5 4 EWAIT E4 E4 E4 P8 P8 P8 I/O I/O O O I/O I/O O O O O I NOTEWE EPENDING NOTEWR EPENDING MCLKOUT NOTMREQ NOTMACK FCLKOUT NOTFBAA NOTESCS0 NOTESCS1 NOTESCS2 MCLKOUT NOTMREQ NOTMACK FCLKOUT - GND H8:N13 36 ball array for ground supply and heat dissipation VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE M N P R R R R R R T R R R M N P 6 6 6 6 7 8 9 10 11 11 12 13 14 15 15 15 VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE Table 34: PBGA ballout for ST40RA166 (page 10 of 11) 67/88 ST40RA166 7 Pin description BPN Pin name Row VDDCORE VDDLMI VDDLMI VDDLMI VDDIO VDDLMI VDDIO VDDLMI VDDIO VDDLMI VDDIO VDDIO VDDLMI VDDIO VDDIO VDDIO VDDLMI VDDLMI VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO Col 15 5 6 6 6 6 6 6 7 8 9 10 10 11 12 13 14 15 15 15 15 15 15 16 Architecture signal name VDDCORE VDDLMI VDDLMI VDDLMI VDDIO VDDLMI VDDIO VDDLMI VDDIO VDDLMI VDDIO VDDIO VDDLMI VDDIO VDDIO VDDIO VDDLMI VDDLMI VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO Pin function Default Alternate Type Pin Dir R K F G H J K L F F F E F F F F F F G H J K L L Table 34: PBGA ballout for ST40RA166 (page 11 of 11) 68/88 7 Pin description ST40RA166 7.4 Pin states The following table shows the direction and state of the pins during and immediately after reset. q q q q q q q Z indicates an output or I/O pin that has been tri-stated. I indicates an input or I/O pin in input modes (I/O buffer tri-stated). 1 indicates an output or I/O pin driving logical high. 0 indicates an output or I/O pin driving logical low. X indicates an output or I/O pin driving undefined data. H indicates a pin with weak internal pull-up enabled. L indicates a pin with weak internal pull-down enabled. Architecturally defined reset state Dir During reset Implementation reset state during and after reset Dir During reset Following reset Pin names LMI system pins LDATA0:63 LBANK0:1 LADDR0:14 LDQS0:7 LCLKOUTA:B NOTLCLKOUTA:B LDQM0:7 NOTLCSA/B0:1, NOTLRASA:B, NOTLCASA:B, NOTLWEA:B LCLKEN0:1 I/O O O I/O O O O O O O Z X X Z 1 0 X 1 1 0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Z 11 1...1 Z X X X 11 1 0 PCI system pins PAD0:31 NOTPCBE0:3 PPAR NOTPFRAME NOT PIRDY NOTPTRDY NOTPSTOP NOTPERR NOTPSERR NOTPDEVSEL PIDSEL NOTPRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 0 0 0 1 1 1 1 1 1 1 0 0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O 0 0 0 H H H H H H H 0 0 Table 35: Pin reset states for ST40RA166 69/88 ST40RA166 7 Pin description Pin names Architecturally defined reset state Dir During reset 1 Running - Implementation reset state during and after reset Dir I/O I/O I/O I/O I/O I/O During reset H Z Z Following reset NOTPLOCK PCLK NOTPREQ[0:3] NOTPGNT[0:3] PCLKOUT NOTPINTA I I I O O I/O 1111 Running H GPDMA pins DACK0, DACK1 DRAK0, DRAK1 DREQ0, DREQ1 O O I Z Z - I/O I/O I/O 0 0 Z Serial communication interface with FIFO (SCIF) pins SCI2 CTS1 RXD0, RXD1 SCK0, SCK1 TXD0, TXD1 I O I I O Z Z I/O I/O I/O I/O I/O H H H H H Power, clocks and so on NOTRST IRL0:3, NMI TMUCLK LPCLKIN CLKIN LPCLKOSC, CLKOSC AUXCLKOUT STATUS1:0 AUDATA0:3 AUDSYNC AUDCLK NOTASEBRK DCLK, TCK, EADDR,TDI NOTTRST, TDO I I I/O I I O O O O O O I I I O Oscillator output CLKIN I I I/O I I O O O O O O I/O I I O (0) H H 0 Running Running CLKIN (1) 11 00 1 0 Z 11 0000 1 0 (1) (0) (0) Z 00 (1) Table 35: Pin reset states for ST40RA166 70/88 7 Pin description ST40RA166 Pin names Architecturally defined reset state Dir During reset Implementation reset state during and after reset Dir During reset Following reset EMI system pins EADDR[2:26]A O Z I/O ZZZE740 (Mode 0) 0 EDATA[0:31] ECLKOUT, MCLKOUT, FCLKOUT ECLKEN EDQM[0:3] NOTECS[0:5] NOTERAS, NOTECAS, NOTEWE EWAIT EPENDING I/O O O O O I/O I/O O I Z 0 Z Z 1 1 Z 0 (MD7 = 0) Z (MD7 = 1) Z Z Z I/O O O O I/O I/O I/O I/O MD7 =0 I O O I/O Z Z Z Z Z Z Z Z 0 1 1111 111111 1 Z 0 NOTMREQ (HLD_ACK when EMI slave) NOTMACK I O O O Z 1 1 Z (HLD_REQ when EMI slave) NOTFBAA NOTESCS[0:2] Table 35: Pin reset states for ST40RA166 a. The reset state of the EADDR bus is tri-state, the value given corresponds to a specific boot mode and shows the expected ties. 71/88 ST40RA166 8 Package 8 Package Physical properties: q q q q q 27x27mm 372 pin BGA package, Typical power consumption <2 W, Substrate height: 0.56 mm, Total height: 2.33 mm, Cover + substrate: 1.73 mm. Figure 19 is a diagram of the pin disposition on the package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R S T U V W Y Pin #1 corner Top view Side view Figure 19: Package layout (viewed through package) 72/88 A Interconnect architecture ST40RA166 A Interconnect architecture This detail is included for information only. It is not recommended to write to any of these registers, without prior consultation from ST, as it could cause the device to malfunction. ST only guarantees correct operation of the device with the default register values. The register reset default values have been programmed to balance the system and give optimum system performance, so there is no need to modify them. For details of other registers see the ST40 System Architecture Manual. The internal architecture of the block is shown in Figure 20. SH4 subsystem Node 1 64-bit full cross bar conn_2 x 2 ST40 core T3 32 CPU P LPUG Cpu_plug f_conv T3 64 T3 LM I 64 T3/T3 64/32 T3/T3 Node 2 32/64 CPU subsystem 100 MHz T3 T3 32 32 EMI subsystem PCI 32-bit 32 T3 T1 PCI (t) 100 MHz T3 32 Full cross bar 32 T3/T1 32/32 T3 1 32 P T3 32 I 32 T1 PER sub GPDMA conn_4 x 4 SH_PER T3 EMPI 32 Programming port Figure 20: ST40RA166 interconnect architecture 73/88 PER ST40RA166 A Interconnect architecture A.1 A.1.1 Arbitration schemes PCI arbiter: (CPU, GPDMA, PCI, EMPI) The default configuration (after reset) for fixed priority mode has to be in the following priority order: q q q q CPU buffer, EMPI, GPDMA, PCI (PCI master request, although not expected, get served to avoid deadlock). The priority orders have to be programmable and the latency checking algorithm can be enabled for GPDMA, PCI, EMPI. A.1.2 EMI arbiter: (CPU buffer, GPDMA, PCI, EMPI) The default configuration (after reset) for fixed priority mode has to be in the following priority order: q q q q CPU buffer, PCI, EMPI, GPDMA. The priority order have to be programmable and the latency checking algorithm can be enabled for GPDMA, PCI, EMPI. A.1.3 LMI 1 arbiter: (CPU, GPDMA, PCI, EMPI) The default configuration (after reset) as to be to work fixed priority mode in the following priority order: q q CPU, GPDMA and PCI buffer. The priority orders have to be programmable and the latency checking algorithm can be enabled for GPDMA, PCI, EMPI. A.1.4 PER arbiter: (CPU, GPDMA, PCI, EMPI) The default configuration (after reset) as to be to work fixed priority mode in the following priority order: q q q q CPU buffer, PCI, EMPI, GPDMA. The priority order have to be programmable and the latency checking algorithm can be enabled for GPDMA, PCI, EMPI. 74/88 A Interconnect architecture A.1.5 LMI2 arbiter: (CPU, GPDMA, PCI, EMPI) ST40RA166 The default configuration (after reset) as to be to work fixed priority mode in the following priority order: q q q q PCI, EMPI, GPDMA, CPU buffer (although the CPU requests are not supposed to go in that node to be send in the LMI, it has to be managed in order to avoid deadlock). The priority order have to be programmable and the latency checking algorithm can be enabled for GPDMA, PCI, EMPI. A.1.6 Return arbitration The possibilities of the return arbitration are simpler than for the request arbitration. The arbiter is not programmable but a specific arbitration can be chosen when implementing it. The arbitration mode chosen is the fixed priority. For each arbiter (one per initiator), the order is the following: LMI then other targets for the arbiters in node 1 and LMI, EMI, PCI, peripheral subsystem for the arbiters of node 2. A.2 Interconnect registers A summary of registers is given in Table 36. Addresses in the table are offset from the interconnect base address at 0x1B05 0000. Address offset 0x010 0x018 0x020 0x110 0x118 0x120 0x128 0x130 0x210 0x218 0x220 0x228 0x230 0x310 Name LATENCY_LMI1_ENABLE LMI1_CPU_PRI LATENCY_LMI1_VALUE LATENCY_LMI2_ENABLE LMI2_CPU_PRI LMI2_LATENCY_PCI LMI2_LATENCY_EMPI Function Enables or disables initiators latency counters, see page 76 Defines priority for the CPU in the LMI1 arbiter, see page 76 Defines priority and latency value for the node 2 in the LMI1 arbiter, see page 76 Enables or disables initiators latency counters, see page 77 Defines priority for the CPU in the LMI2 arbiter, see page 77 Defines priority and latency value for PCI initiator in the PCI arbiter, see page 77 Defines priority and latency value for EMPI initiator in the PCI arbiter, see page 77 Defines priority and latency value for GPDMA initiator in the PCI arbiter, see page 77 Enables or disables initiators latency counters, see page 78 Defines priority for the CPU in the EMI arbiter, see page 78 Defines priority and latency value for PCI initiator in the EMI arbiter, see page 78 Defines priority and latency value for EMPI initiator in the EMI arbiter, see page 78 Defines priority and latency value for GPDMA initiator in the EMI arbiter, see page 79 Enables or disables initiators latency counters, see page 79 LMI2_LATENCY_GPDMA LATENCY_EMI_ENABLE EMI_CPU_PRI EMI_LATENCY_PCI EMI_LATENCY_EMPI EMI_LATENCY_GPDMA LATENCY_PCI_ENABLE Table 36: Interconnect register summary 75/88 ST40RA166 A Interconnect architecture Address offset 0x318 0x320 0x328 0x330 0x410 0x418 0x420 0x428 0x430 Name PCI_CPU_PRI PCI_LATENCY_PCI PCI_LATENCY_EMPI Function Defines priority for the CPU in the PCI arbiter, see page 79 Defines priority and latency value for PCI initiator in the PCI arbiter, see page 79 Defines priority and latency value for EMPI initiator in the PCI arbiter, see page 79 Defines priority and latency value for GPDMA initiator in the PCI arbiter, see page 80 Enables or disables initiators latency counters, see page 80 Defines priority for the CPU in the peripheral arbiter, see page 80 Defines priority and latency value for PCI initiator in the peripheral arbiter, see page 80 Defines priority and latency value for EMPI initiator in the peripheral arbiter, see page 81 Defines priority and latency value for GPDMA initiator in the peripheral arbiter, see page 81 PCI_LATENCY_GPDMA LATENCY_PER_ENABLE PER_CPU_PRI PER_LATENCY_PCI PER_LATENCY_EMPI PER_LATENCY_GPDMA Table 36: Interconnect register summary A.2.1 LMI1 arbiter LATENCY_LMI1_ENABLE 0 1 Reserved ENABLE_1 LMI1 arbiter: enable latency counters Reset: Always 0 Enable latency check for node 2 Reset: 0 0x010 RW [31:2] Reserved Reset: Always 0 LMI1_CPU_PRI [3:0] CPU_PRIORITY LMI1 arbiter: CPU priority Defines priority for CPU Reset: 0x1 0x018 RW [31:4] Reserved LATENCY_LMI1_VALUE [3:0] NODE2_PRIORITY LMI1 arbiter: node 2 intitiator priority and latency Defines priority for node 2 initiators Reset: 0x0 0x020 RW [15:4] [23:16] Reserved NODE2_LATENCY Defines maximum accepted latency for node 2 initiators Reset: 0x00 RW [31:24] Reserved 76/88 A Interconnect architecture A.2.2 LMI2 arbiter LATENCY_LMI2_ENABLE 0 1 Reserved ENABLE_PCI ST40RA166 LMI2 arbiter: enable latency counters Reset: Always 0 Enable latency check for PCI Reset: 0 0x110 RW 2 ENABLE_EMPI Enable latency check for EMPI Reset: 0 RW 3 ENABLE_GPDMA Enable latency check for GPDMA Reset: 0 RW [31:4] Reserved Reset: Always 0 LMI2_CPU_PRI [3:0] CPU_PRIORITY LMI2 arbiter: CPU priority Defines priority for CPU Reset: 0x0 0x118 RW [31:4] Reserved LMI2_LATENCY_PCI [3:0] PCI_PRIORITY LMI2 arbiter: PCI intitiator priority and latency Defines priority for PCI Reset: 0x3 0x120 RW [15:4] [23:16] Reserved PCI_LATENCY Defines maximum accepted latency for PCI Reset: 0x00 RW [31:24] Reserved LMI2_LATENCY_EMPI [3:0] EMPI_PRIORITY LMI2 arbiter: EMPI intitiator priority and latency Defines priority for EMPI Reset: 0x2 0x128 RW [15:4] [23:16] Reserved EMPI_LATENCY Defines maximum accepted latency for EMPI Reset: 0x00 RW [31:24] Reserved LMI2_LATENCY_GPDMA [3:0] GPDMA_PRIORITY LMI2 arbiter: GPDMA intitiator priority and latency Defines priority for GPDMA Reset: 0x1 0x130 RW [15:4] Reserved 77/88 ST40RA166 A Interconnect architecture LMI2_LATENCY_GPDMA [23:16] GPDMA_LATENCY LMI2 arbiter: GPDMA intitiator priority and latency Defines maximum accepted latency for GPDMA Reset: 0x00 0x130 RW [31:24] Reserved A.2.3 EMI arbiter LATENCY_EMI_ENABLE 0 1 Reserved ENABLE_PCI EMI arbiter: enable latency counters Reset: Always 0 Enable latency check for PCI Reset: 0 0x210 RW 2 ENABLE_EMPI Enable latency check for EMPI Reset: 0 RW 3 ENABLE_GPDMA Enable latency check for GPDMA Reset: 0 RW [31:4] Reserved Reset: Always 0 EMI_CPU_PRI [3:0] CPU_PRIORITY EMI arbiter: CPU priority Defines priority for CPU Reset: 0x3 0x218 RW [31:4] Reserved EMI_LATENCY_PCI [3:0] PCI_PRIORITY EMI arbiter: PCI intitiator priority and latency Defines priority for PCI Reset: 0x2 0x220 RW [15:4] [23:16] Reserved PCI_LATENCY Defines maximum accepted latency for PCI Reset: 0x00 RW [31:24] Reserved EMI_LATENCY_EMPI [3:0] EMPI_PRIORITY EMI arbiter: EMPI intitiator priority and latency Defines priority for EMPI Reset: 0x1 0x228 RW [15:4] [23:16] Reserved EMPI_LATENCY Defines maximum accepted latency for EMPI Reset: 0x00 RW [31:24] Reserved 78/88 A Interconnect architecture ST40RA166 EMI_LATENCY_GPDMA [3:0] GPDMA_PRIORITY EMI arbiter: GPDMA intitiator priority and latency Defines priority for GPDMA Reset: 0x0 0x230 RW [15:4] [23:16] Reserved GPDMA_LATENCY Defines maximum accepted latency for GPDMA Reset: 0x00 RW [31:24] Reserved A.2.4 PCI arbiter LATENCY_PCI_ENABLE 0 1 Reserved ENABLE_PCI PCI arbiter: enable latency counters 0x310 Enable latency check for PCI Reset: 0 RW 2 ENABLE_EMPI Enable latency check for EMPI Reset: 0 RW 3 ENABLE_GPDMA Enable latency check for GPDMA Reset: 0 RW [31:4] Reserved Reset: Always 0 PCI_CPU_PRI [3:0] CPU_PRIORITY PCI arbiter: CPU priority Defines priority for CPU Reset: 0x3 0x318 RW [31:4] Reserved PCI_LATENCY_PCI [3:0] PCI_PRIORITY PCI arbiter: PCI intitiator priority and latency Defines priority for PCI Reset: 0x0 0x320 RW [15:4] [23:16] Reserved PCI_LATENCY Defines maximum accepted latency for PCI Reset: 0x00 RW [31:24] Reserved PCI_LATENCY_EMPI [3:0] EMPI_PRIORITY PCI arbiter: EMPI intitiator priority and latency Defines priority for EMPI Reset: 0x2 0x328 RW [15:4] Reserved 79/88 ST40RA166 A Interconnect architecture PCI_LATENCY_EMPI [23:16] EMPI_LATENCY PCI arbiter: EMPI intitiator priority and latency Defines maximum accepted latency for EMPI Reset: 0x00 0x328 RW [31:24] Reserved PCI_LATENCY_GPDMA [3:0] GPDMA_PRIORITY PCI arbiter: GPDMA intitiator priority and latency Defines priority for GPDMA Reset: 0x1 0x330 RW [15:4] [23:16] Reserved GPDMA_LATENCY Defines maximum accepted latency for GPDMA Reset: 0x00 RW [31:24] Reserved A.2.5 Peripheral arbiter LATENCY_PER_ENABLE 0 1 Reserved ENABLE_PCI Peripheral arbiter: enable latency counters Reset: Always 0 Enable latency check for PCI Reset: 0 0x410 RW 2 ENABLE_EMPI Enable latency check for EMPI Reset: 0 RW 3 ENABLE_GPDMA Enable latency check for GPDMA Reset: 0 RW [31:4] Reserved Reset: Always 0 PER_CPU_PRI [3:0] CPU_PRIORITY Peripheral arbiter: CPU priority Defines priority for CPU Reset: 0x3 0x418 RW [31:4] Reserved PER_LATENCY_PCI [3:0] PCI_PRIORITY Peripheral arbiter: PCI intitiator priority and latency 0x420 Defines priority for PCI Reset: 0x2 RW [15:4] [23:16] Reserved PCI_LATENCY Defines maximum accepted latency for PCI Reset: 0x00 RW [31:24] Reserved 80/88 A Interconnect architecture ST40RA166 PER_LATENCY_EMPI [3:0] EMPI_PRIORITY Peripheral arbiter: EMPI intitiator priority and latency Defines priority for EMPI Reset: 0x1 0x428 RW [15:4] [23:16] Reserved EMPI_LATENCY Defines maximum accepted latency for EMPI Reset: 0x00 RW [31:24] Reserved PER_LATENCY_GPDMA [3:0] GPDMA_PRIORITY Peripheral arbiter: GPDMA intitiator priority and latency Defines priority for GPDMA Reset: 0x0 0x430 RW [15:4] [23:16] Reserved GPDMA_LATENCY Defines maximum accepted latency for GPDMA Reset: 0x00 RW [31:24] Reserved 81/88 ST40RA166 B Implementation restrictions B B.1 B.1.1 Implementation restrictions ST40 CPU tas.b The atomicity of the tas.b instruction is only guaranteed for processes executing on the ST40 CPU core and should not be used to implement intermodule or interchip semaphores. Either use the mailbox functionality or an appropriate software algorithm for such semaphores. B.1.2 Store queue power-down The store queue is considered part of the general CPU and independent power-down of this block is not implemented. B.1.3 UBC power-down The UBC is considered part of the general CPU and independent power-down of this block is not implemented. B.1.4 System standby To enter and leave standby it is necessary for the CPU to power down the system including memory devices and then to enter standby by executing a sleep instruction. On leaving sleep and standby, it may be necessary for the CPU to power itself up and subsequently power up the system and its memory devices. During the power-down and power-up sequences the main memory devices are not available. The CPU therefore preloads the appropriate code into the cache as part of the power sequencing. B.2 B.2.1 PCI Clocking PCI internal clock loopback is not implemented. To use the internal PCI clock, the pads PCICLOCKOUT and PCICLOCKIN are connected to loopback the clock generator. Alternatively an external clock source may be used. B.2.2 Type 2 configuration accesses Configuration space accesses to devices across a PCI bridge are implemented as type 2 operations on the PCI bus. In this implementation such accesses must be broken into a sequence of byte operations. For example, access to a 32-bit register is through four single byte operations. B.2.3 Software visible changes between STB1HC7 and ST40RA166H8D PCI PLL reprogramming required for H7 parts is no longer required for H8. The PCI PLL register is renamed from PLLPCICR to CLKGENA.PLL2CR. The register implementation for PCI MBAR mappings has changed between the STB1HC7 and ST40RA166H8D implementations and software device drivers should reflect this. B.2.4 Error behavior The implementation of local (PCI register) error handling is not fully implemented. 82/88 B Implementation restrictions B.2.5 Master abort ST40RA166 When operating as a bus master, the PCI module is not guaranteed to have the value 0xFFFF FFFF following a master abort of a read cycle. The master abort may be detected using either the PCI module status and interrupt information supplied by the module. B.3 B.3.1 EMI/EMPI EMPI burst mode operation: ST40RA166 MPX target MPX operations using the ST40RA166 as the target which lead to burst requests to memory (Read ahead, 8-, 16- and 32-byte read operations) have limited support. MPX operations from the ST40RA166 as an initiator includes full support for all transfer sizes. B.3.2 SDRAM initialization during boot from flash During the SDRAM initialization sequence only internal EMI registers are accessible, it is therefore necessary to ensure the program required to execute the initialization sequence is placed in an alternate memory location such as the LMI or preloaded into the cache. B.3.3 MPX boot BootFromMPX is not supported on this part. B.4 B.4.1 Mailbox Test and set functionality This is not supported. B.5 B.5.1 Power down Module power-down sequencing Whilst powering down using the associated registers for the ST40RA166 module, in general, software is responsible for ensuring the module is in a safe state before requesting module shutdown. For details refer to the appropriate documentation. B.5.2 Accesses to modules in power-down state Once a module is in power-down state, attempts to access that module may lead the system to hang. 83/88 ST40RA166 B Implementation restrictions B.6 B.6.1 PIO PIO default functionality following reset In the ST40 family device, the operational modes for these registers differ from the standard architecture definition and are shown in Table 37. PIO bit configuration NonPIO functiona PIO bidirectional PIO output PIO bidirectional PIO input PIO input Reserved Reserved Open drain Push-pull Open drain High impedance High impedance PIO output state PIO.PC2 0 0 0 0 1 1 1 1 PIO.PC1 0 0 1 1 0 0 1 1 PIO.PC0 0 1 0 1 0 1 0 1 Table 37: PIO alternate function registers a. State following reset B.6.2 PCI/PIO alternate functions The following PIO signals cannot be used when PCI is enabled even if the PCI implementation does not require the primary pin function BPN Pin name Row NOTPREQ0 NOTPREQ1 Col 18 17 Architecture signal name NOTPCI_REQ0 NOTPCI_REQ1 Pin function Default PCI external request for bus PCI external request for bus Pin Alternate PIO16 PIO18 Type P8 P8 Dir I/O I I/O I/O E E NOTPREQ2 NOTPREQ3 F G 16 16 NOTPCI_REQ2 NOTPCI_REQ3 PCI external request for bus PCI external request for bus PIO20 PIO22 EMPIDREQ1 P8 P8 I I I/O I/O O Table 38: PCI/PIO alternate functions If PCI is disabled, the alternate functions may be used. 84/88 B Implementation restrictions ST40RA166 B.7 B.7.1 Interconnect Memory bridge functionality Ensure there is no traffic passing though the memory bridge when changing frequency. Semisynchronous modes of operation are not supported. B.7.2 Clock selection The alternate CLOCKGENB clock is not supported for the LMI. B.7.3 Pad drive control Programmable drive strength control is not supported for DDR operation. B.8 B.8.1 GPDMA Linked list support Decrementing transfers are not supported as part of link list transfer sequences B.8.2 2-D transfers 2-D transfers fail if the following conditions are met. 1 2 3 Source or destination length is greater than 64 bytes. Real transfer unit is less then 32 bytes. The expression length = n * 64 + tu is true, where: length is either SLENGTH or DLENGTH, tu the real transfer unit of the first access of the second line, n > 0. B.8.3 Protocol signals DACK and DRACK protocol signals have limited support. B.9 RTC clock The feedback circuit for the LPCLK and LPOSC clock generation to the TC fails if the main core supply is removed. In applications where this may occur, an LPCLK should be generated externally. 85/88 ST40RA166 Revision history Revision history Version Version D Cover Title changed Old Figure 1 replaces cover diagram 3 ST40 systems using the ST40RA166 4 ST40RA166 system organization Section removed Comments Section 4.6: EMI address pin mapping on page 18 5 Electrical specifications Definition of address lines on EMI interface in 8-, 16- and 32bit data width Section 6.2: Rise and fall times on page 44 Version C Rise and fall times for the memory interfaces Name change from ST40STB1 to ST40RA166 New sections 5.2 System identifiers 5.6.8 PLL programming formulas 5.6.9 PLL stabilization times 6.1.1 Fmax clock domains 6.5 DDR bus termination (SSTL_2) B1.3 UBC power down B2.2 Type 2 configuration accesses B8 LMI B9 GPDMA B10 RTC clock New tables Table 31 Power dissipation New figures Figure 2 Pocket multimedia device Figure 8 Pads characteristics for SL, P8, C2A and C2B pad types Figure 9 Pad characteristics for C4 and E4 pad types Figure 13 SSTL_2 bus termination Sections revised Cover: bus interface figures for LMI and EMI changed 3 ST40 systems using the ST40RA166: rewording 6 Electrical specifications: AC/DC characterisation figures changed B2.3 Software visible changes between ST40RA166HC7 and ST40RA166H8D: used to be MBAR register definition B3.1 EMPI burst mode operaton: ST40RA166 MPX target: clarifying sentence added at end B9.2 2D transfers: point 3 explained more fully 86/88 Revision history ST40RA166 Version Tables revised Comments Table 1 Subsystem configuration registers: SYS_STAT1 added Table 8 Clock domains: CLOCKGEN_B12 bit reserved, EMI_CLK target frequency range added Table 9 CLOCKGENB.CLK_SELCR bit allocation: LMI_SEL bit reserved Table 10 Supported operating frequencies: recommended operation codes changed Table 15 CPG.STBCR2 register definition, comment added about stopping the store queue and UBC Table 24 EMI.GENCFG register, footnote added about EWAIT signal Table 28 SYSCONF2 definitions: field names changed, LMI_SDRAM_DATA_DRIVE, LMI_SDRAM_ADD_DRIVE Table 30 Absolute maximum ratings: New symbol VIORTC and note added Table 31 Operating conditions: PD and PDlp removed Table 33 I/O maximum capacitive and DC loading: pad types C2A and C2B replace C2 Table 34 PCI AC timings: tPCIHAOV max now 10 and min 1 Table 44 PBGA ballout for ST40RA166: CLKIN, CLKOSC, LPCLKIN, LPCLKOSC BPN numbers changed and pad types changed for some pins. EWAIT Table 44 PBGA ballout for ST40RA166: footnote added for pin. Figures revised Figure 5 ST40RA166 clock architecture: some labels changed Figure 19 Package layout (viewed through package) 87/88 ST40RA166 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. (c) 2002 STMicroelectronics. All Rights Reserved. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 88/88 |
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