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| 74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker January 1990 Revised December 1998 74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description The ACT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. The ACT899 features independent latch enables for the A-to-B direction and the B-toA direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. Features s Latchable transceiver with output sink of 24 mA s Option to select generate parity and check or "feed-through" data/parity in directions A-to-B or B-to-A s Independent latch enable for A-to-B and B-to-A directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking s Ability to simultaneously generate and check parity s May be used in system applications in place of the 280 s May be used in system applications in place of the 657 and 373 (no need to change T/R to check parity) Ordering Code: Order Number 74ACT899QC Package Number V28A Package Description 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450" Square Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbol Connection Diagram Pin Assignment for PCC FACTTM is a trademark of Fairchild Semiconductor Corporation. (c) 1999 Fairchild Semiconductor Corporation DS010637.prf www.fairchildsemi.com 74ACT899 Pin Descriptions Pin Names A0-A7 B0-B7 APAR, BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB Description A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs ODD/EVEN Parity Select, Active LOW for EVEN Parity Output Enables for A or B Bus, Active LOW Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode Latch Enables for A and B Latches, HIGH for Transparent Mode Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs Functional Description The ACT899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. * Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW, the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA). * Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU). * Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table). Function Table Inputs GAB GBA SEL H H H H L L X L L LEA LEB X L H X H H Busses A and B are 3-STATE. Generates parity from B[0:7] based on O/E (Note 1). Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generates parity from B[0:7] based on O/E. Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity from B latch data based on O/E. Generated parity APAR. Generated parity checked against latched BPAR and output as ERRB . BPAR/B[0:7] APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. BPAR/B[0:7] APAR/A[0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L L H H L L H H L H Generates parity for A[0:7] based on O/E. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generates parity from A[0:7] based on O/E. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. Generates parity from A latch data based on O/E. Generated parity BPAR. Generated parity checked against latched APAR and output as ERRA . APAR/A[0:7] BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. L H H H H APAR/A[0:7] BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note 1: O/E = ODD/EVEN Operation H H H L L L L H H X X H L H H L L H H L H L H X L www.fairchildsemi.com 2 74ACT899 Functional Block Diagram AC Path An, APAR Bn, BPAR (Bn, BPAR An, APAR) FIGURE 1. An BPAR (Bn APAR) FIGURE 2. 3 www.fairchildsemi.com 74ACT899 An ERRA (Bn ERRB) FIGURE 3. O/E ERRA O/E ERRB FIGURE 4. O/E BPAR (O/E APAR) FIGURE 5. www.fairchildsemi.com 4 74ACT899 APAR ERRA (BPAR ERRB) FIGURE 6. ZH, HZ FIGURE 7. ZL, LZ FIGURE 8. SEL BPAR (SEL APAR) FIGURE 9. 5 www.fairchildsemi.com 74ACT899 LEA BPAR, B[0:7] (LEB APAR, A[0:7]) FIGURE 10. TS(H), TH(H) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) FIGURE 11. TS(L), TH(L) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) FIGURE 12. FIGURE 13. www.fairchildsemi.com 6 74ACT899 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or 50 mA -65C to +150C 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V Sink Current Junction Temperature (TJ) 300 mA 140C Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate V/t VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications. 4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Note 3: Maximum of 9 outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.5 0.6 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = V IL or VIH 3.76 4.76 0.1 0.1 V V IOH = -24 mA IOH = -24 mA (Note 3) IOUT = 50 A VIN = VIL or VIH 0.44 0.44 1.0 5.0 1.5 75 -75 V A A mA mA mA A IOL = 24 mA IOL = 24 mA (Note 3) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND 5.5 5.5 5.5 5.5 5.5 5.5 8.0 80.0 7 www.fairchildsemi.com 74ACT899 AC Electrical Characteristics VCC Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPHL tPHZ tPLZ Parameter Propagation Delay An, Bn to Bn, An Propagation Delay APAR, BPAR to BPAR, APAR Propagation Delay An, Bn to BPAR, APAR Propagation Delay An, Bn to ERRA, ERRB Propagation Delay ODD/EVEN to ERRA, ERRB Propagation Delay ODD/EVEN to APAR, BPAR Propagation Delay APAR, BPAR to ERRA, ERRB Propagation Delay SEL to APAR, BPAR Propagation Delay LEB to An, Bn Propagation Delay LEA to APAR, BPAR Propagation Delay LEA, LEB to ERRA, ERRB Output Enable Time GBA or GAB to An, Bn Output Enable Time GBA or GAB to BPAR or APAR Output Disable Time GBA or GAB to An, Bn Output Disable Time GBA or GAB to BPAR, APAR 5.0 1.5 6.5 9.5 1.5 9.5 ns 5.0 1.5 6.5 9.5 1.5 9.5 ns 5.0 1.5 6.0 9.0 1.5 9.5 ns 5.0 2.5 7.0 10.5 2.5 11.0 ns Figure 7 Figure 8 Figure 7 Figure 8 Figure 7 Figure 8 Figure 7 Figure 8 5.0 2.5 8.0 11.5 2.5 12.0 ns 5.0 2.0 8.0 11.5 2.0 12.0 ns 5.0 2.5 7.0 10.5 2.5 11.0 ns Figure 10 Figure 11 Figure 10 Figure 11 Figure 12 5.0 1.5 6.5 9.0 1.5 9.5 ns Figure 9 5.0 1.5 7.5 10.5 1.5 11.5 ns Figure 6 5.0 2.5 8.0 11.5 2.5 12.0 ns Figure 5 5.0 2.0 8.0 11.5 2.0 12.0 ns Figure 4 5.0 2.0 8.0 11.5 2.0 12.0 ns Figure 3 5.0 2.5 8.5 12.0 2.5 12.5 ns Figure 2 5.0 1.5 6.0 8.5 1.5 9.0 ns Figure 1 (V) (Note 5) 5.0 Min 2.5 TA = +25C CL = 50 pF Typ 7.5 Max 11.5 TA = -40C to +85C CL = 50 pF Min 2.5 Max 12.0 ns Figure 1 Units Fig. No. Note 5: Voltage Range 5.0 is 5.0V 0.5V. AC Operating Requirements VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW An, Bn, PAR to LEA, LEB Hold Time, HIGH or LOW An, Bn, PAR to LEA, LEB Pulse Width for LEB, LEA 5.0 4.0 4.0 ns Note 6: Voltage Range 5.0 = 5.0V 0.5V. TA = +25C CL = 50 pF 3.0 1.5 TA = -40C to +85C CL = 50 pF 3.0 1.5 Units ns ns Fig. No. Figure 11 Figure 12 Figure 11 Figure 12 Figure 13 (V) (Note 6) 5.0 5.0 Guaranteed Minimum Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 210 Units pF pF VCC = 5.0V VCC = 5.0V Conditions www.fairchildsemi.com 8 74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450" Square Package Number V28A LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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