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CDB4391 Evaluation Board for CS4391
Features
l Demonstrates
Description
The CDB4391 evaluation board is an excellent means for quickly evaluating the CS4391 24-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS4391 (for control port mode only) and a power supply. Analog line level outputs are provided via RCA phono jacks. The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converter and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB4391 Evaluation Board
recommended layout and grounding arrangements l CS8414 receives AES/EBU, S/PDIF, & EIAJ340 compatible digital audio l Digital and analog patch areas l Requires only a digital signal source and power supplies for a complete Digital-toAnalog-Converter system
I/O for Clocks and Data
Control Port Channel A Output and Mute
CS8414 Digital Audio Interface
CS4391 Channel B Output and Mute
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
MAR `00 DS335DB2 1
CDB4391
TABLE OF CONTENTS
1. CDB4391 SYSTEM OVERVIEW .............................................................................................. 3 2. CS4391 DIGITAL TO ANALOG CONVERTER ........................................................................ 3 3. CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 3 4. CS8414 DATA FORMAT .......................................................................................................... 3 5. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 4 6. POWER SUPPLY CIRCUITRY ................................................................................................. 4 7. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 4 8. CONTROL PORT SOFTWARE ................................................................................................ 4 9. DSD OPERATION .................................................................................................................... 4 10. ERRATA FOR THE REVISION A CIRCUIT BOARD ............................................................ 4 11. PACKING LIST FOR CDB4391 ............................................................................................ 21
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .......................................................................... 8 Figure 2. CS4391 and Level Shift ................................................................................................... 9 Figure 3. Channel B Audio Output and Mute Circuit ..................................................................... 10 Figure 4. Channel A Audio Output and Mute Circuit ..................................................................... 11 Figure 5. CS8414 Digital Audio Receiver...................................................................................... 12 Figure 6. Digital Audio Inputs ........................................................................................................ 13 Figure 7. Reset Circuit................................................................................................................... 14 Figure 8. Control Port Interface ..................................................................................................... 15 Figure 9. I/O for Clocks and Data.................................................................................................. 16 Figure 10. Power Supply ............................................................................................................... 17 Figure 11. Silkscreen Top ............................................................................................................. 18 Figure 12. Top Side....................................................................................................................... 19 Figure 13. Bottom Side.................................................................................................................. 20
LIST OF TABLES
Table 1. CS8414 Supported Formats.............................................................................................. 3 Table 2. System Connections ......................................................................................................... 5 Table 3. CDB4391 Jumper and Switch settings - STAND-ALONE MODE ..................................... 6 Table 4. CDB4391 Jumper and Switch settings - CONTOL PORT MODE..................................... 7
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
I2C is a registered trademark of Philips Semiconductors. SPI is a registered trademark of International Business Machines Corporation. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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DS335DB2
CDB4391
1. CDB4391 SYSTEM OVERVIEW
The CDB4391 evaluation board is an excellent means of quickly evaluating the CS4391. The CS8414 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4391 schematic has been partitioned into 9 schematics shown in Figures 2 through 10. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics. datasheet. It is likely that the de-emphasis control for the CS4391 will be erroneous and produce an incorrect audio output if the Error Information Switch is activated and the CS4391 is in the standalone mode with internal serial clock mode selected. Encoded sample frequency information can be displayed provided a proper clock is being applied to the FCK pin of the CS8414. When an LED is lit, this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L nor R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, see Figure 6. However, both inputs cannot be driven simultaneously.
2. CS4391 DIGITAL TO ANALOG CONVERTER
A description of the CS4391 is included in the CS4391 datasheet.
4. CS8414 DATA FORMAT
The CS8414 data format can be set with switches M0, M1, M2, and M3, as described in the CS8414 datasheet. The format selected must be compatible with the data format of the CS4391, as shown in the CS4391 datasheet. Please note that the CS8414 does not support all the possible modes of the CS4391 and the Left-Justified Format for the CS8414 and the CS4391 have incompatible serial clocks, see Table 1. The default settings for M0-M3 on the evaluation board are given in Tables 3-4.
CS4391 CP Mode Format 0 1 2 3 4 5 CS4391 SA Mode Format 0 1 2 3 CS8414 Format Unsupported 2 5 Unsupported Unsupported 6
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 datasheet. During normal operation, the CS8414 operates in the Channel Status mode where the LED's display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8414 to decode the de-emphasis bit from the digital audio interface for control of the CS4391 de-emphasis filter, when the CS4391 is in stand-alone mode. When the Error Information Switch is activated, the CS8414 operates in the Error and Frequency information mode. The information displayed by the LED's can be decoded by consulting the CS8414
Table 1. CS8414 Supported Formats
DS335DB2
3
CDB4391
5. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, J9. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 9. The 74HC243 transceiver functions as an I/O buffer where HRD1 through HRD6 determine if the transceiver operates as a transmitter or receiver. A transmit function is implemented with all jumpers, HRD1 through HDR6 in the 8414 position. LRCK, SDATA, and SCLK from the CS8414 will be outputs on J9. The transceiver operates as a receiver with HRD1 through HDR6 in the EXT_CLK position. MCLK, LRCK, SDATA and SCLK on J9 become inputs.
7. GROUNDING AND POWER SUPPLY DECOUPLING
The CS4391 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 10 details the power distribution used on this board. The decoupling capacitors are located as close to the CS4391 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.
8. CONTROL PORT SOFTWARE
The CDB4391 is shipped with Windows based software for interfacing with the CS4391 control port via the DB25 connector, P1. The software can be used to communicate with the CS4391 in either SPI or I2C mode; however, in SPI mode the CS4391 registers are write-only. Note: The CDB4391 must be configured for control port mode as shown in Table 4. Further documentation for the software is available on the distribution diskette. The documentation is available in the plain text format file, README.TXT.
6. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six binding posts (GND, +5V, +3/+5V, VL, VCC and VEE), see Figure 10. The +5V input supplies power to the +5 volt digital circuitry (VA+5, VD+5, VDPC+5), while the VL input supplies power to the Voltage Level Converters and the CS4391 VL pin. +3/+5V supplies power to the CS4391. VCC and VEE supply power to the op-amp and can be +/-5 to +/-12 volts. WARNING: Refer to the CS4391 datasheet for maximum allowable voltages levels. Operation outside of this range can cause permanent damage to the device.
9. DSD OPERATION
The CDB4391 supports Direct Stream Digital (DSD) operation through the header for external clocks and data, J9. The CS4391 must be placed into the DSD mode and the jumpers HDR1 through HDR6 must be placed into the external clock positions.
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DS335DB2
CDB4391
CONNECTOR +5V +3/+5V VL VEE VCC GND Coax Input Optical Input J9 Parallel Port HDR9 AOUTA AOUTB
INPUT/OUTPUT Input Input Input Input Input Input Input Input Input/Output Input/Output Input/Output Output Output + 5 Volt power
SIGNAL PRESENT + 2.7 to + 5.5 Volt power for the CS4391 + 1.8 to +5.5 digital interface voltage (Note that VL should not exceed the voltage applied to the+3/+5V terminal) -12 to -5V negative supply for the op-amp +5 to +12V positive supply for the op-amp Ground connection from power supply Digital audio interface input via coax Digital audio interface input via optical I/O for master, serial, left/right clocks and serial data Parallel connection to PC for SPI / I2C control port signals I/O for SPI / I2C control port signals Channel A line level analog output Channel B line level analog output
Table 2. System Connections
DS335DB2
5
CDB4391
JUMPER / SWITCH SW1 - M0 SW1 - M1 SW1 - M2 SW1 - M3 SW1 CSLR/FCK HDR8 HDR7 ENCTRL M0/AD0/CS M1/SDA/CDIN M2/SCL/CCLK
PURPOSE CS8414 mode selection CS8414 mode selection CS8414 mode selection CS8414 mode selection Selects channel for CS8414 channel status information External mute for AOUTA External mute for AOUTB Enables / Disables parallel port CS4391 Mode Selection CS4391 Mode Selection CS4391 Mode Selection
POSITION *LO *HI *LO *LO *LO *ON OFF *ON OFF ENABLE *DISABLE *HI LO HI *LO GND HI *DEM HI *LO *8414 EXT
FUNCTION SELECTED See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details Mute Enabled Mute Disabled Mute Enabled Mute Disabled Invalid for Stand-Alone Mode Disables parallel port See CS4391 datasheet for details See CS4391 datasheet for details See CS4391 datasheet for details Allows the CS8414 to control de-emphasis See CS4391 datasheet for details Selects CS8414 as source Digital I/O header becomes source
M3 HDR1 to HDR6
CS4391 Mode Selection Selects source of clocks and audio data
Table 3. CDB4391 Jumper and Switch settings - STAND-ALONE MODE *Settings for Stand-Alone mode Notes: The CDB4391 evaluation board is shipped from the factory configured for Control Port mode.
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DS335DB2
CDB4391
JUMPER SW1 - M0 SW1 - M1 SW1 - M2 SW1 - M3 SW1 CSLR/FCK HDR8 HDR7 ENCTRL M0/AD0/CS M1/SDA/CDIN M2/SCL/CCLK
PURPOSE CS8414 mode selection CS8414 mode selection CS8414 mode selection CS8414 mode selection Selects channel for CS8414 channel status information External mute for AOUTA External mute for AOUTB Enables / Disables parallel port AD0/CS SDA/CDIN Pull-Up SCL/CCLK Pull-Up
POSITION *LO *HI *LO *LO *LO *ON OFF *ON OFF *ENABLE DISABLE *HI LO *HI LO GND *HI DEM HI *LO *8414 EXT
FUNCTION SELECTED See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details Mute Enabled Mute Disabled Mute Enabled Mute Disabled Enables parallel port Invalid for Control Port mode "Don't Care" for Control Port mode SDA/CDIN pulled high Invalid for Control Port mode Invalid for Control Port mode SCL/CCLK pulled high Invalid for Control Port mode Must be low for Control Port mode Selects CS8414 as source Digital I/O header becomes source
M3 HDR1 to HDR6
Not Functional Selects source of clocks and audio data
Table 4. CDB4391 Jumper and Switch settings - CONTOL PORT MODE *Settings for Control Port mode Notes: The CDB4391 evaluation board is shipped from the factory configured for Control Port mode.
DS335DB2
7
8
I/O for Clocks and Data Fig 9
Reset Circuit Fig 7
Control Port Interface Fig 8 Channel A Outputs and Mute Circuit Fig 4 CS4391 Fig 2 Channel B Outputs and Mute Circuit Fig 3
Digital Audio Inputs Fig 6
RXN
CS8414 Digital Audio RXP Receiver Connections Fig 5
MCLK LRCK SCLK SDATA
CDB4391
DS335DB2
Figure 1. System Block Diagram and Signal Flow
DS335DB2
C54 .1UF X7R U9
VL SDATA SCLK
1 2 4 5 13 12 10 9
VL GND
VCC /A0 B0 /A1 B1 /A2 B2 /A3 B3 O0 O1 O2 O3 GND 74VHC125M
3 6
14
U7 R10 499 R13 499 R14 499 R41 SDATA SCLK LRCK MCLK M3 M2
M2/SCL/CCLK
1 2 3 4 5 6 7 8 9 10 \RST VL SDATA/DSD_A SCLK/DSD_B LRCK/DSDMODE MCLK (DSD_CLK)M3 (SCL/CCLK)M2 (SDA/CDIN)M1 (AD0/\CS\)M0 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ 20 19 18 17 16 15 14 13 12 11
FERRITE_BEAD L1
VA+3/+5 AMUTEC AOUTAAOUTA+ AOUTB+ AOUTBBMUTEC
C59 .1UF
C17 .1UF X7R
C40 1UF
LRCK GND M3
11 8 7
GND
49.9
GND
GND
CS4391 C20 1UF
C34 .1UF X7R
M1
M1/SDA/CS
C21 1UF
M0
M0/AD0/CS
GND
U6
1 2 4 5 13 12 10 9
VCC /A0 B0 /A1 B1 /A2 B2 /A3 B3 O0 O1 O2 O3 GND 74VHC125M
3 6
14
MCLK VL RST 8414_DEM
11 8 7
DEM
C61 .1UF
GND GND
GND
CDB4391
Figure 2. CS4391 and Level Shift 9
HDR1X2 HDR7 1 2
10
R35 C4 2700PF COG AOUTBAOUTB-
5.62K
10UF R34 C41
5.62K
GND
R29
1.18K
C18
560PF COG U11
7
6
AOUTB+
AOUTB+
10UF R33 C39 C28 2700PF COG
GND GND need cog VA+3/+5
2
R19
560 R4 47K
J4 CON_RCA_RA
1 2 3 4 NC
5.62K
R32 R31 5.62K
1.18K
5
+ C22 560PF COG
GND
MC33078D
AOUTB
GND
GND
1
MMUN2111LT1 Q6
3
Q5 2SC2878 R36 2K
3
2
3
BMUTEC
BMUTEC
1
Q2 MMUN2211LT1
2
1
GND
GND
CDB4391
DS335DB2
Figure 3. Channel B Audio Output and Mute Circuit
2700PF COG
GND
560PF COG
GND VEE
C48 .1UF
GND
HDR1X2 HDR8 1 2
DS335DB2
R28 C7 2700PF COG
GND
5.62K
C6
560PF COG
VCC
C49 .1UF V+ C42 C43
AOUTA+
8
AOUTAAOUTA-
10UF 10UF
R24 R26
5.62K 5.62K C14
R17 R18 R15 5.62K
U11 GND
1
1.18K 1.18K
2
J3 CON_RCA_RA R20 560 R5 47K
1 2 3 4 NC
3
+ C5 V4
MC33078D
AOUTA
AOUTA+
GND
GND
GND
VA+3/+5
2
1
MMUN2111LT1 Q3
3
Q1 2SC2878 R25 2K
3
2
3
AMUTEC AMUTEC
1
Q4 MMUN2211LT1
2
1
GND GND
CDB4391
Figure 4. Channel A Audio Output and Mute Circuit 11
D1 LED_RECT
2
1
SN74HC04N
D3 LED_RECT 4 3
VA
CS8414_M2
RXP RXN
R9 470
C33
.068UF X7R GND
SW_DIP_5
OPEN
12
HDR1X3 HDR5 1 2 3 1 2 3
MCLK
HDR1X3 HDR4
VA+5
C1 10UF
VA
HDR1X3 HDR3
GND
1 2 3
GND
1 2 3
SCLK
HDR1X3 HDR2 RN4 47K
LRCK
VD1
R11
VD1
10
1 2 3
HDR1X3 HDR1
C26
RN3 560
SDATA
.1UF X7R 1UF
1 2 3 4 5 6 7 8 9 10 11 12 13 14
C27
C16
VD+5
14
U2 VERF C CE/F2 CD/F1 SDATA CC/F0 ERF CB/E2 M1 CA/E1 M0 /C0/E0 VA+ VD+ AGND DGND FILT RXP RXN MCK FSYNC M2 SCK M3 CS12/FCK SEL U CBL CS8414
28 27 26 25 24 23 22 21 20 19 18 17 16 15
.1UF X7R
CS8414_M0
.1UF C31
SW1
VD+5
VCC
U8
GND
1UF C32
CS8414_M1 5 4 3 2 1
GND
D5 LED_RECT
6
5
CSLR/FCK
8414_DEM
D6 LED_RECT 8 9
SW_B3W_1100 S4
D4 10 LED_RECT 11
R7 47.5K
ERROR & FREQ
D2 12 LED_RECT 13
VD1
7
GND
GND
CDB4391
DS335DB2
Figure 5. CS8414 Digital Audio Receiver
DS335DB2
DIGITAL INPUT
J5
CON_RCA_RA
3 NC 4 1 2 6
OPTICAL INPUT
OPT1
C11 R30 75
.01UF
RXN
1 2 3 4 5
C10 C9 .01UF L4
.01UF
RXP
47UH
VD+5
GND
TORX173
GND
CDB4391
Figure 6. Digital Audio Inputs 13
GND
GND
S1 SW_B3W_1100
14
U3 DS1233-10
1 GND RST 3 Vcc
VD+5
GND
2
1
RST
C23 100PF
CDB4391
DS335DB2
Figure 7. Reset Circuit
DS335DB2
VDPC+5 VD+5
C63 .1UF
PC PORT VDPC+5
C46 .1UF
RN2
6
4.7K
11
GND
2
VCC
14
U15
3
HDR4X2 HDR9 1 2 3 4 5 6 7 8
VL GND ENCTRL DISABLE ENABLE
1 2 3
SN74HCT125D GND
71
C45
VDPC+5
GND
.1UF
U5
1 2 4 5 13 12 10 9
GND
HDR10 HDR1X3
VCC /A0 B0 /A1 B1 /A2 B2 /A3 B3 O0 O1 O2 O3 GND
3 6
14
GND
RN2
1
4.7K
16 5
U15
6
GND
VDPC+5
RN1 1K
SN74HCT125D
4
M1/SDA/CDIN
11 8 7
M0/AD0/CS M2/SCL/CCLK
U1
GND
EN_SCL/CCLK
RN2
2
1 11 2 3 4 5 6 7 8 9
4.7K
15
/OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q VCC GND
19 18 17 16 15 14 13 12 20 10
74VHC125M
RN2
3 DB25M_RA P1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
4.7K
14
R6 2K
R8 2K
R12 2K
GND VL VDPC+5
HDR1X3 HDR11 1 2 3 HDR1X3 HDR12 1 2 3
RN2
4
4.7K
13 9
U15
8
EN_SCL/CCLK
SN74HCT125D
10
SN74HC574DW
C47 .1UF
M0/AD0/CS
M2/SCL/CCLK
M1/SDA/CDIN
RN2
5
4.7K
12
GND GND GND
GND
HDR23 1 2 HDR22 1 2 HDR21 1 2
VL
U15
11 12
M1/SDA/CDIN
13
SN74HCT125D
DEM
GND
GND VDPC+5 GND VDPC+5
VCC C62
2
14
U16
3
.1UF GND
GND GND
71
SN74HCT125D
U16
5 6
SN74HCT125D
4
GND
U16 R38 4.7K
9 8 D7 BAT85
SN74HCT125D
10
GND RST
U16
11 12
SN74HCT125D
13
CDB4391
GND
Figure 8. Control Port Interface 15
GND
VCC GND SN74HC243N
14 7
VD+5
C35 .1UF
R1
GND
0
16
U4
HDR5X2 J9 2 1 4 3 6 5 8 7 10 9 1 13 3 4 5 6
G1 G2 A1 A2 A3 A4 B1 B2 B3 B4 VCC GND
11 10 9 8 14 7
SDATA LRCK SCLK MCLK
SDATA LRCK SCLK MCLK VD+5
(DSD_CLK)M3
C24 .1UF
RN5 47K
GND
SN74HC243N U10
1 13 3 4 5 6
DIGITAL I/O
8414 EXTERNAL CLK SOURCE HDR1X3 HDR6
VD+5
HDR1X3 HDR14 1 2 3
G1 G2 A1 A2 A3 A4 B1 B2 B3 B4
11 10 9 8
GND
1 2 3
VD+5
M3 M3
GND
CDB4391
DS335DB2
Figure 9. I/O for Clocks and Data
DS335DB2
+5V
CON_BANANA
GND
CON_BANANA
+3V/+5V
CON_BANANA
VL
CON_BANANA
VCC
CON_BANANA
VEE
CON_BANANA
J6 Z1
J7 P6KE6V8P
J1 P6KE6V8P
J11
J8 Z3 P6KE13 Z4 P6KE13
J10
P6KE6V8P
Z2
Z5
C12 47UF
C2 47UF
GND
C29 47UF
VL
C30 47UF
C36 47UF
C25
VA+5
.1UF
C3
.1UF
VA+3/+5
C57
.1UF C37 .1UF C38 .1UF
L3 FB C8 L2 .1UF FB C13 47UF
GND VCC GND VEE
GND
GND
10UF C19
VDPC+5
VD+5
CDB4391
Figure 10. Power Supply 17
CDB4391
Figure 11. Silkscreen Top
18
DS335DB2
CDB4391
Figure 12. Top Side
DS335DB2
19
CDB4391
Figure 13. Bottom Side
20
DS335DB2
CDB4391
10. PACKING LIST FOR CDB4391
Inspect the Contents of the package and confirm that the following contents are included: 1) CDB4391 2) CDB4391 datasheet 3) CS4391 datasheet 4) 3.5 inch floppy disk with the Windows based CDB4391 Graphical User Interface 5) 25-pin RS-232 cable
Item CDB4391 CS4391-KZ CDB4391 data sheet CS4391 Data sheet 3.5 inch floppy disk with windows based graphical user interface 25-pin RS-232 cable
Revision B A DS335DB2 DS335PP2 1.0
If any of the items are missing please contact Cirrus for Crystal(R) Audio support at (800) 888-5016.
DS335DB2
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