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Preliminary Data Sheet No. PD60166-I
IR2136/IR21362/IR21363 (J&S)
Features
* Floating channel designed for bootstrap operation * * * * * * * * * *
Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V (IR2136), 11.5 to 20V (IR21362) or 12 to 20V (IR21363) Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Independent 3 half-bridge drivers Matched propagation delay for all channels Lowside outputs out of phase with inputs. High side outputs out of phase (IR2136/IR21363) or in phase (IR21362) with inputs. Cross-conduction prevention logic 3.3V logic compatible Lower di/dt gate driver for better noise immunity Externally programmable delay for automatic fault clear
3-PHASE BRIDGE DRIVER
Product Summary
VOFFSET 600V max. IO+/120 mA / 250 mA VOUT 10 - 20V or 12V - 20V Deadtime (typ.) 200 nsec ton/off (typ.) 400 nsec
Packages
Description
The IR2136/IR21362/IR21363(J&S) are high votage, high speed power MOSFET and IGBT drivers with three independent high and low side referenced output channels for 3-phase applications. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3V logic. A current trip function which terminates all six outputs can be derived from an external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. Overcurrent fault conditions are cleared
28-Lead SOIC 28-Lead PDIP
44-Lead PLCC w/o 12 leads
automatically after a delay programmed externally via an RC network connected to the RCIN input. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which operates up to 600 volts.
up to 600V
Typical Connection
VCC HIN1,2,3 / HIN1,2,3 LIN1,2,3 FAULT EN VCC HIN1,2,3 / HIN1,2,3 LIN1,2,3 HO1,2,3 FAULT EN VS1,2,3 VB1,2,3
RCIN
TO LOAD LO1,2,3 COM
(Refer to Lead Assignments for correct pin configuration). This/ These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit GND board layout.
ITRIP VSS
IR2136(2)(3)
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IR2136/IR21362/IR21363(J&S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VS VBS VHO VCC VSS VLO1,2,3 VIN
Definition
High side offset voltage High side floating supply voltage High side floating output voltage Low side and logic fixed supply voltage Logic ground Low side output voltage Input voltage LN ,HIN(IR2136/IR21363),HIN (IR21362) ITRIP, I , EN, RCIN
Min.
-0.3 -0.3 VS1,2,3 - 0.3 -0.3 VCC - 25 -0.3 VSS - 0.3
Max.
600 25 VB1,2,3 + 0.3 25 VCC + 0.3 VCC + 0.3 (VSS + 15) or VCC + 0.3) which ever is lower VCC + 0.3 50 1.5 1.6 2.0 83 78 63 125 150 300
Units
V
VFLT dV/dt PD
FAULT output voltage Allowable offset voltage slew rate Package power dissipation @ TA +25C
(28 lead PDIP) (28 lead SOIC) ( 44leadPLCC) (28 lead PDIP) (28 lead SOIC) (44 lead PLCC)
VSS - 0.3 -- -- -- -- -- -- -- -- -55 --
V/ns W
RthJA
Thermal resistance, junction to ambient
C/W
TJ TS TL
Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute referenced to COM. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
VB1,2,3
Definition
High side floating supply voltage IR2136 IR21362 IR21363
Min.
10 11.5 12 Note 1 VS1,2,3 0 10 11.5 12 -5 VSS VSS
Max.
20 20 20 600 VB1,2,3 VCC 20 20 20 5 VCC VCC
Units
VS1,2,3 VHO1,2,3 VLO1,2,3 VCC
High side floating supply offset voltage High side output voltage Low side output voltage Low side and logic fixed supply voltage
IR2136 IR21362 IR21363
V
VSS VFLT VRCIN
Logic ground FAULT output voltage RCIN input voltage
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IR2136/IR21362/IR21363(J&S)
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute referenced to COM. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
VITRIP ITRIP input voltage
Definition
Min.
VSS
Max.
VSS +5
Units
V VIN Logic input voltage LN , HIN (IR2136), HIN(IR21362), EN I VSS VSS +5 o Ambient temperature -40 125 C TA Note 1: Logic operational for VS of COM -5 to COM +600V. Logic state held for VS of COM -5V to -COM -VBS. (Please refer to the Design Tip DT97-3 for more details). Note 2: All input pins and the ITRIP pin are internally clamped with a 5.2V zener diode.
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six channels (HS1,2,3 and LS1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.
Symbol
VIH VIL VEN,TH+ VEN,THVIT,TH+ VIT,HYS VRCIN,TH+ VRCIN,HYS VOH VOL VCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH I LK IQBS IQCC VIN, CLAMP I LIN+
Definition
Logic "0" input voltage LIN1,2,3, HIN1,2,3 Logic "1" input voltage HIN1,2,3 Logic "1" input voltage LIN1,2,3, HIN1,2,3 Logic "0" input voltage HIN1,2,3 EN positive going threshold EN negative going threshold ITRIP positive going threshold ITRIPinput hysteresis RCIN positive going threshold RCIN input hysteresis High level output voltage, VBIAS - VO Low level output voltage, VO VCC and VBS supply undervoltage positive going threshold VCC and VBS supply undervoltage negative going threshold VCC and VBS supply undervoltage lockout hysteresis Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current
Input clamp voltage (HIN, LIN, ITRIP and EN)
Min. Typ. Max. Units Test Conditions
3 -- -- 0.8 370 -- -- -- -- -- IR2136 IR21362 IR21363 IR2136 IR21362 IR21363 IR2136 IR21362 IR21363 8.0 9.6 10.7 7.4 8.6 10.5 0.3 0.5 -- -- 20 -- 4.9 -- -- -- -- -- 460 70 8 3 0.8 0.3 8.9 10.4 11.2 8.2 9.4 11.0 0.7 1.0 0.2 -- 60 1 5.2 150 -- 0.8 3 -- 550 -- -- -- 1.4 0.6 9.8 11.2 11.7 9.0 10.2 11.5 -- -- -- 50 A 150 2 5.5 400 mA V A VIN = =100A IIN 0V or 5V VLIN = 0V VB1,2,3=VS1,2,3 = 600V V IO = 20 mA IO = 20 mA mV
V
Input bias current (LOUT = HI)
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IR2136/IR21362/IR21363(J&S)
Static Electrical Characteristics cont.
VBIAS (VCC, VBS1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six channels (HS1,2,3 and LS1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.
Symbol
ILINI HIN+ I HINIITRIP+ I ITRIPIEN+ IENIRCIN IO+ IORON,RCIN RON,FLT
Definition
Input bias current (LOUT = LO) Input bias current (HOUT = HI) Input bias current (HOUT = LO) "high" ITRIP input bias current "low" ITRIP input bias current "high" ENABLE input bias current "low" ENABLE input bias current RCIN input bias current Output high short circuit pulsed current Output low short circuit pulsed current RCIN low on resistance FAULT low on resistance IR2136(3) IR21362 IR2136(3) IR21362
Min. Typ. Max. Units Test Conditions
-- -- -- -- -- -- -- -- -- -- 120 250 -- -- 100 150 -- 100 0 -- 0 -- 0 0 200 350 60 60 250 300 100 250 1 100 1 100 1 1 -- -- -- -- mA A VLIN = 5V VHIN = 0V VHIN = 5V VHIN = 5V VHIN = 0V VITRIP = 5V VITRIP = 0V VENABLE= 5V VENABLE = 0V VRCIN = 0V or 15V VO=0V PW 10 s , VO=15V PW 10 s ,
Dynamic Electrical Characteristics
VCC = VBS = VBIAS = 15V, VS1,2,3 = VSS = COM, TA = 25o C and CL = 1000 pF unless otherwise specified.
Symbol
ton toff tr tf tEN tITRIP tbl tFLT tFILIN tFLTCLR DT MT MDT PM
Definition
Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time ENABLE low to output shutdown propagation delay ITRIP to output shutdown propagation delay ITRIP blanking time ITRIP to FAULT propagation delay Input filter time (HIN, LIN, EN) FAULT clear time RCIN: R=2meg, C=1nF Deadtime Matching delay ON and OFF Matching delay, max (ton,toff) - min (ton,toff), (ton,toff are applicable to all 3 channels) Output pulse width matching, PWin - PWout (fig.2)
Min.
-- -- -- -- -- -- 100 -- 100 -- -- -- -- --
Typ.
400 380 110 50 400 700 150 500 200 1.8 250 0 0 0
Max. Units Test Conditions
-- -- -- -- -- -- -- -- -- -- -- 80 75 75 nS External dead time >400nsec mS nS VIN, VEN = 0V or 5V VITRIP = 5V VIN = 0V or 5V VITRIP = 5V VIN = 0V or 5V VITRIP = 5V VIN = 0 & 5V VIN = 0V or 5V VITRIP = 0V VIN = 0 & 5V VIN = 0 & 5V VS1,2,3 = 0 to 600V
NOTE: For high side PWM, HIN pulse width must be 1sec
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IR2136/IR21362/IR21363(J&S)
VCC VBS X ITRIP X 0V 0V >VITRIP 0V
ENABLE X 5V 5V 5V 0V
FAULT 0 (note 1) high imp high imp 0 (note 2) high imp
LO1,2,3 0 LIN1,2,3 LIN1,2,3 0 0
HO1,2,3 0 0 HIN1,2,3 0 0
Note: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously. Note 1: UVCC is not latched, when VCC>UVCC, FAULT returns to high impedance. Note 2: When ITRIP Functional Block Diagram
2136/21363
DEADTIME & SHOOT-THROUGH PREVENTION VSS/COM LEVEL SHIFTER HV LEVEL SHIFTER SET RESET LATCH DRIVER UV DETECT
VB1 HO1 VS1 VB2
HIN1 LIN1
INPUT NOISE FILTER INPUT NOISE FILTER
HIN2 LIN2
INPUT NOISE FILTER INPUT NOISE FILTER
DEADTIME & SHOOT-THROUGH PREVENTION
VSS/COM LEVEL SHIFTER
HV LEVEL SHIFTER
SET RESET
LATCH DRIVER UV DETECT
HO2 VS2 VB3
HIN3 LIN3 VSS
INPUT NOISE FILTER INPUT NOISE FILTER
DEADTIME & SHOOT-THROUGH PREVENTION
VSS/COM LEVEL SHIFTER
HV LEVEL SHIFTER
SET RESET
LATCH DRIVER UV DETECT
HO3 VS3 VCC
EN
INPUT NOISE FILTER
UV DETECT
VSS/COM LEVEL SHIFTER
DELAY
DRIVER
LO1
ITRIP
+
0.5V
INPUT NOISE FILTER S Q SET R DOMINANT LATCH VSS/COM LEVEL SHIFTER DELAY DRIVER
LO2
RCIN
FAULT
VSS/COM LEVEL SHIFTER
DELAY
DRIVER
LO3 COM
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IR2136/IR21362/IR21363(J&S)
Functional Block Diagram
HIN1 LIN1
INPUT NOISE FILTER INPUT NOISE FILTER
IR21362
DEADTIME & SHOOT-THROUGH PREVENTION VSS/COM LEVEL SHIFTER HV LEVEL SHIFTER SET RESET LATCH DRIVER UV DETECT
VB1 HO1 VS1 VB2
HIN2 LIN2
INPUT NOISE FILTER INPUT NOISE FILTER
DEADTIME & SHOOT-THROUGH PREVENTION
VSS/COM LEVEL SHIFTER
HV LEVEL SHIFTER
SET RESET
LATCH DRIVER UV DETECT
HO2 VS2 VB3
HIN3 LIN3 VSS
INPUT NOISE FILTER INPUT NOISE FILTER
DEADTIME & SHOOT-THROUGH PREVENTION
VSS/COM LEVEL SHIFTER
HV LEVEL SHIFTER
SET RESET
LATCH DRIVER UV DETECT
HO3 VS3 VCC
EN
INPUT NOISE FILTER
UV DETECT
VSS/COM LEVEL SHIFTER
DELAY
DRIVER
LO1
ITRIP
+ -
INPUT NOISE FILTER S SET R DOMINANT LATCH Q VSS/COM LEVEL SHIFTER DELAY DRIVER
0.5V
LO2
RCIN
FAULT
VSS/COM LEVEL SHIFTER
DELAY
DRIVER
LO3 COM
6
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IR2136/IR21362/IR21363(J&S)
Lead Definitions
Symbol Description
VCC VSS Low side and logic fixed supply Logic Ground
HIN1,2,3 Logic inputs for high side gate driver outputs (HO1,2,3), out of phase (IR2136/IR21363) HIN1,2,3 Logic inputs for high side gate driver outputs (HO1,2,3), in phase (IR21362) LIN1,2,3 FAULT EN ITRIP Logic inputs for low side gate driver outputs (LO1,2,3), out of phase Indicates over-current (ITRIP) or low-side undervoltage lockout has occured. Negative logic, open-drain output Logic input to enable I/O functionality. Positive logic, i.e. I/O logic functions when ENABLE is high. No effect on FAULT and not latched Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and activates FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time TFLTCLR, then automatically becomes inactive (open-drain high impedance). External RC network input used to define FAULT CLEAR delay, TFLTCLR, approximately equal to R*C. When RCIN>8V, the FAULT pin goes back into open-drain high-impedance Low side gate driver return High side floating supply High side gate driver outputs High voltage floating supply returns Low side gate driver output
RCIN COM VB1,2,3 HO1,2,3 VS1,2,3 LO1,2,3
Lead Assignments
1 2 3 4 5 6 7 8 9
VCC HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FAULT ITRIP
VB1 HO1 VS1
28 27
HIN3 HIN2 HIN1 HO1 VCC VB1
1 2
VS1
VCC HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FAULT ITRIP
VB1 HO1 VS1
28 27 26 25
26 25
7
3 4 5
6
5
4
3
43
42
41
VB2 HO2 VS2
24 23 22 21
LIN1 LIN2 LIN3
8 9 10 11 37 36 35
VB2 HO2 VS2
24 23 22 21
VB2 HO2 VS2
6 7 8 9
IR2136
FAULT
IR2136
VB3 HO3 VS3
20 19 18 17
12 13
VB3 HO3 VS3
20 19 18 17
EN RCIN
IR2136 44 LEAD PLCC w/o 12 LEADS
10 EN 11 RCIN 12 VSS 13 COM 14 LO3
10 EN
ITRIP
14 15 16 17 18 19 20 21 22 23 24 25 31 30 29
VB3 HO3 VS3
11 RCIN 12 VSS 13 COM 14 LO3
LO1 LO2
16 15
LO1 LO2
16 15
LO3
LO2
VSS
28 Lead PDIP
44 Lead PLCC w/o 12 leads
44 lead PLCC w/o 12 leads
COM
LO1
28 lead SOIC (wide body)
IR2136/IR21363
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IR2136J/IR21363J
IR2136S/IR21363S
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IR2136/IR21362/IR21363(J&S)
HIN3
HIN2
HIN1
VCC
VB1
VS1
HO1
1 VCC 2 3 4 37 36 35
VB1 28 HO1 27 VS1 26
25
1 VCC 2 3 4 5 6 7 8 9
VB1 28 HO1 27
7
6
5
4
3
43
42
41
HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FAULT ITRIP
HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FAULT ITRIP
VS1 26 LIN1
25 8 9 10 11
LIN2 VB2 24 LIN3 HO2 23
VB2 HO2 VS2
5 6 7 8 9
VB2 24 HO2 23 VS2 22
21
VS2 22 FAULT
21 13 12
VB3 20 HO3 19 VS3 18
17
VB3 20 ITRIP
14 15 31 30 29 18 19 20 21 22 23 24 25 10 EN
10 EN 11 RCIN 12 VSS 13 COM 14 LO3
HO3 19 VB3 HO3 VS3
11 RCIN 12 VSS 13 COM 14 LO3
VS3 18 EN
17 16 17
RCIN LO1 16
LO1 16 LO2 15
VSS
LO2 15
COM
LO3
LO2
44 lead PLCC w/o 12 leads
28 Lead PDIP
44 Lead PLCC w/o 12 leads
LO1
28 lead SOIC (wide body)
IR21362
IR21362J
IR21362S
HIN1,2,3
HIN1,2,3
LIN1,2,3
EN
ITRIP
FAULT
RCIN
HO1,2,3
LO1,2,3
Figure 1. Input/Output Timing Diagram
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IR2136/IR21362/IR21363(J&S)
LIN1,2,3 HIN1,2,3
PW IN 50% 50%
LIN1,2,3 HIN1,2,3
ton
50%
50%
tr PW OUT
toff
tf
HO1,2,3 LO1,2,3
90%
90%
10%
10%
Figure 2. Switching Time Waveforms
LIN1,2,3 HIN1,2,3
50% 50%
LIN1,2,3 HIN1,2,3
50%
50%
LO1,2,3
DT
50%
50%
DT
HO1,2,3
50%
50%
Figure 3. Internal Deadtime Timing Waveforms
Vrcin,th+
RCIN
50%
EN
ITRIP
50% 50%
ten
FAULT
tflt 50% 50%
90%
90% tfltclr
Any output
titrip
HO1,2,3 LO1,2,3
Figure 4. ITRIP/RCIN Timing Waveforms
Figure 5. Output Enable Timing Waveform
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IR2136/IR21362/IR21363(J&S)
Case outlines
28-Lead PDIP (wide body)
01-6011 01-3024 02 (MS-011AB)
28-Lead SOIC (wide body)
10
01-6013 01-3040 02 (MS-013AE)
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IR2136/IR21362/IR21363(J&S)
NOTES
44-Lead PLCC w/o 12 leads
01-6009 00 01-3004 02(mod.) (MS-018AC)
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 1/28/2002
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