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19-2694; Rev B, 07/04

Single +3.3V Power Supply Operation
DESIGNATION QTY DESCRIPTION C1, C2, C5, C9, 0.1F 10% ceramic capacitors 8 C13, C15, C16, (0402) C17 C3 C4, C6, C7, C8, C11, C12 C10 C14 C18 D1 D2 L1, L2, L3 L4 R1, R2 R3 R4 R5, R12 R6, R13 R7 R8 R9, R11 R10, R26, R27, R34, R35, R36 R14 R15 1 6 1 1 1 1 1 3 1 2 1 1 2 2 1 1 2 6 1 1
DESIGNATION QTY DESCRIPTION R16 1 500k potentiometer Q1, Q2 Q3 JU1-JU8, JU10 J1-J7 2 1 9 7 MOSFET (SOT23)
NPN transistors (SOT23)
0.047F 10% ceramic capacitor (0402) 0.01F 10% ceramic capacitors (0402) Open 10F 10% ceramic capacitor (0805) 10F 10% tantalum capacitor (B Case) VCSEL laser and photodiode* LED, red T1 package 1H inductor (1008CS) 10k potentiometers
2-pin headers, 0.1in centers SMA connectors, round contacts
TP1-TP11, TP20, 13 Test points TP21 U1 U2 None None None 1 1 9 1 1 MAX3740AETG (24QFN) MAX495ESA (8 SO) Shunts MAX3740A EV board MAX3740A data sheet
* These components are not supplied but can be populated for VCSEL testing.
350 1% resistor (0402) 2.49k 1% resistor (0402) 499 1% resistors (0402) 10k 5% resistors (0402) 0 1% resistor (0402)* 4.7k 1% resistor (0402) 49.9 1% resistors (0402) Open 20k potentiometer 50k potentiometer
SUPPLIER AVX Coilcraft Digi-Key
PHONE
FAX
843-444-2863 847-639-6400 218-681-6674 402-474-4800 415-964-6321
843-626-3123 847-639-1469 218-681-3380 402-474-4858 415-964-8165
EF Johnson Murata
Note: Please indicate that you are using the MAX3701 when ordering from these suppliers.
_________________________________________________________________Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
PART TEMP. RANGE IC PACKAGE MAX3740AEVKIT -40C to +85C 24 QFN
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The output of the evaluation kit can be interfaced to an SMA connector, which can be connected to a 50s terminated oscilloscope. With slight modifications, the evaluation kit can also be used to evaluate the MAX3740A operation with a common-cathode VCSEL.
|
Allows Optical and Electrical Evaluation
The MAX3740A evaluation kit (EV kit) is an assembled demonstration board that provides complete optical and electrical evaluation of the MAX3740A VCSEL driver.
Fully Assembled and Tested
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In the electrical configuration, an automatic power control (APC) test circuit is included to emulate a semiconductor laser with a monitor photodiode. Monitor diode current is provided by transistor Q1, which is controlled by an operational amplifier (U2). The APC test circuit, consisting of U2 and Q1, applies the simulated monitor diode current to the MD pin of the MAX3740. To ensure proper operation in the electrical configuration, set up the evaluation board as follows: 1) 2) 3) Place shunts on JU4 - JU8 and JU10 (see the Adjustment and Control Description section for details). Remove shunts JU1 and JU2. To enable the output connect TX_DISABLE to GND by placing a shunt on JU3. Note: When performing the following resistance checks, autoranging DMMs may forward bias the onchip ESD protection and cause inaccurate measurements. To avoid this, manually set the DMM to a high range. 4) Adjust R15, the RBIASSET potentiometer, for 1.7k resistance between TP4 (BIASSET) and ground. 5) Adjust R1, the RPWRSET potentiometer, for 10k resistance between TP2 (REF) and pin 1 (MD) of JU2. 6) Adjust R14, the RPEAKSET potentiometer, for 20k resistance between TP10 (PEAKSET) and ground, to disable peaking. 7) Adjust R16, the RTC potentiometer, for 0 resistance between TP7 (TC1) and TP8 (TC2), to disable temperature compensation. 8) Adjust R2, the RMODSET potentiometer, for 10k resistance between TP9 (MODSET) and ground. 9) Apply a differential input signal (250mVP-P to 2200mVP-P) between SMA connectors J5 and J7 (IN+ and IN-). 10) Attach a high-speed oscilloscope with a 50 input to SMA connector J6 (OUT). 11) Connect a +3.3V supply between TP20 (VCC) and TP21 (GND). Adjust the power supply until the voltage between TP11 and ground is +3.3V. 12) Adjust R1 (RPWRSET) until desired laser bias current is achieved.
For optical evaluation of the MAX3740A, configure the evaluation kit as follows: 1) 2) 3) 4) 5) Place shunts on JU2, JU6, JU7, JU8 and JU10 (See the Adjustment and Control Description section for details). Remove components L2 and C9. Remove the shunts from JU1, JU4 and JU5. Install a 0 resistor at R7 to connect the anode of the VCSEL to the output. To enable the output connect TX_DISABLE to GND by placing a shunt on JU3. Connect a common cathode VCSEL as shown in Figure 1. Keep leads short to reduce reflection. Note: When performing the following resistance checks, autoranging DMMs may forward bias the onchip ESD protection and cause inaccurate measurements. To avoid this, manually set the DMM to a high range. 6) 7) 8) 9) Adjust R15, the RBIASSET potentiometer, for 1.7k resistance between TP4 (BIASSET) and ground. Adjust R1, the RPWRSET potentiometer, for 10k resistance between TP2 (REF) and pin 1 (MD) of JU2. Adjust R14, the RPEAKSET potentiometer, for 20k resistance between TP10 (PEAKSET) and ground, to disable peaking. Adjust R16, the RTC potentiometer, for 0 resistance between TP7 (TC1) and TP8 (TC2), to disable temperature compensation.
I
BIAS
=
V 49.9
PIN 1 _ JU 5
13) The MD and BIAS currents can be monitored at TP1 (VPWRMON) and TP3 (VBIASMON) using the equations below:
2 ________________________________________________________________________________________
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PWRSET
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BIAS
=
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BIASMON
Note: If the voltage at TP1 exceeds VPMTH (0.8V typ) or TP3 exceeds VBMTH (0.8V typ), the FAULT signal will be asserted and latched. 14) Adjust R2 until the desired laser modulation current is achieved.
IMOD =
15) Adjust R14 (RPEAKSET) until the desired amount of peaking is achieved.
Signal Amplitude (V ) 50
PWRSET
COMPONENT D2 JU1 JU2 JU3 JU4 JU5 JU6 JU7 JU8 JU10 R1 R2 R14 R15 R16
NAME
FUNCTION
Fault Indicator COMP PHOTODIODE TX_DISABLE IPD APCOPEN FAULT SQUELCH POWER VCCEXT RPWRSET RMODSET RPEAKSET RBIASSET RTC
The LED is illuminated when a fault condition has occurred (refer to the Detailed Description section of the MAX3740 data sheet). Enables/disables the APC circuit. Remove the shunt to enable the APC circuit. Installing a shunt connects the photodiode of the VCSEL to the MD pin. Used when a VCSEL is installed. Enable/disable the output currents. Install a shunt to enable output currents. Determines the gain of the photodiode emulator. When JU4 is open, the gain is 0.02A/A. When JU4 is shunted, the gain is 0.12A/A. Installing a shunt connects the electrical output of the part to the emulation circuit. Installing a shunt enables the external fault-indicator circuit. Installing a shunt enables the squelch function. Installing a shunt provides power to the part. Installing a shunt provides power to the emulation and fault-indicator circuits. Adjusts transmit optical power to be maintained by the APC loop. Adjusts the laser modulation current. Adjusts the peaking for the falling edge of the VCSEL. In a closed-loop configuration: adjusts the maximum bias current available to the APC. In an open-loop configuration: adjusts the bias level of the output. Adjusts the temperature compensation of the modulation current.
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3
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PWRMON
VU
V 2xR
RS
T
16) Adjust R2 (RMODSET) until the desired optical amplitude is achieved. Optical amplitude can be observed on an oscilloscope connected to an optical/electrical converter. VCSEL overshoot and ringing can be improved by appropriate selection of R10 and C10, as described in the Design Procedure section of the MAX3740 data sheet.
Q
EH
IP
Note: If the voltage at TP1 exceeds VPMTH (typical 0.8V) or TP3 exceeds VBMTH (typical 0.8V), the FAULT signal will be asserted and latched.
FE
I
BIAS
=
BIASMON
CD G
10) Adjust R2, the RMODSET potentiometer, for 10k resistance between TP9 (MODSET) and ground. 11) Apply a differential input signal (250mVP-P to 2200mVP-P) between SMA connectors J5 and J7 (IN+ and IN-). 12) Attach the VCSEL fiber connector to an optical/electrical converter. 13) Connect a +3.3V supply between TP20 (VCC) and TP21 (GND). Adjust the power supply until the voltage between TP11 and ground is +3.3V. 14) Adjust R1 (RPWRSET) until desired average optical power is achieved. 15) The MD and BIAS currents can be monitored at TP1 (VPWRMON) and TP3 (VBIASMON) using the equations below:
9xV 350
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JU8 POWER
L4 1H
TP11 NOISEGEN
VCC1 JU10 VCCEXT VCCEXT C17 0.1F C7 0.01F
L3 BLM18HD102SN1
TP20 VCC
Q3
C14 10F TP6 PORTEST C15 0.1F C16 0.1F C18 10F
TP21 GND
R35 OPEN
JU2 PHOTODIODE C12 0.01F VCCEXT
J1 CALIN+
C1 0.1F
R1 10k PWRSET J2 CALOUT+ TP2 REF C3 0.047F
VCC1 C6 0.01F JU1 COMP Q1 FMMT491A
7 6
MAX495
3 U2 2
4
C2 0.1F J3 CALINJ4 CALOUTTP1 PWRMON
TP3 BIASMON
R3 350 JU4 IPD
24
23
22
21
20
19
PWRMON
BIASMON
REF
COMP
MD
VCC
L1 BLM18HD102SN1
R4 2.49k
R5 499
R6 10k JU5 APCOPEN
JU3 TX_DISABLE
1 2
GND
BIAS
18 17
TP4 BIASSET R36 OPEN R15 50k BIASSET VCC1
R11 49.9 L2 BLM18HD102SN1
J5 IN+ J7 INVCCEXT
C5 0.1F C13 0.1F
3 4 5
IN+ INFAULT
U1 MAX3740A
PEAKSET MODSET
VCC OUT+ OUTGND
16 15 14 13
C8 0.01F
C11 0.01F R9 49.9 C10 OPEN R10 OPEN R7 OPEN
C9 0.1F
J6 OUT
VCC1 D2 FAULT
JU7 SQUELCH 6
SQUELCH GND VCC TC1 TC2
R13 10k JU6 FAULT R12 499 TP5 FAULT
VCC1
2 1
4 3
Q2 FMMT491A
7
R8 4.7k C4 0.01F
8
9
10
11
12
D1 VCSEL PHOTODIODE
R16 500k TC
TP9 MODSET R2 10k MODSET R27 OPEN R14 20k PEAKSET R26 OPEN
TP10 PEAKSET R34 OPEN
TP7 TC1
TP8 TC2
Figure 1. MAX3740A EV Kit Schematic Diagram
TX_DISABLE
BIASSET
4 ________________________________________________________________________________________
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Figure 2. MAX3740A EV Kit Component Placement Guide - Component Side
Figure 3. MAX3740A EV Kit PC Board Layout Solder Side
_________________________________________________________________________________________
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Figure 4. MAX3740A EV Kit PC Board Layout Ground Plane
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 ___________________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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Figure 5. MAX3740A EV Kit PC Board Layout Power Plane
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* I E I E E E I I E O OO O NO Ox

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