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NEW!
L 30W CCF Inverter D esign
JULY 2000
ML4877*
LCD Desktop Backlight Lamp Driver
GENERAL DESCRIPTION
The ML4877 is an ideal solution for driving multiple cold cathode fluorescent tubes (CCFL) used in liquid crystal display (LCD) backlight applications. It provides dimming ballast control for the LCD display. By utilizing differential drive the ML4877 can deliver the same light output with significantly less input power compared to existing single ended drive schemes. Improvements as high as 30% can be realized when using low power lamps and advanced LCD screen housings. This increased light output is achieved because the differential drive configuration is much less sensitive, and therefore less power is wasted in the capacitive parasitics that exist in the backlight housing. An additional benefit of this configuration is an even distribution of light. The IC includes an adjustable lamp out detect circuit that latches the IC off when a lamp fault is detected. Also, the unique architecture of the ML4877 allows the development of a backlight system that will inherently meet the UL requirements for safety. The ML4877 is optimized for large LCD applications applications where high efficiency is critical to maximize battery life. The high efficiency is achieved by a resonant scheme with zero voltage switching.
FEATURES
s s s s s s s s s
Ideal for 30W inverter designs, 1 to 8 lamp design PWM dimming capability Backlight lamp driver with differential drive Up to 30% lower power for same light output Low standby current (<10A) Improved efficiency (95%) Allows all N-channel MOSFET drive Adjustable lamp out detect with latch Resonant threshold detection and synchronous rectification Positive input for dimming control
s
* THIS PART IS END OF LIFE AS OF JULY 1, 2000
BLOCK DIAGRAM
AZR 2 VDD 13 VDD HVDD 12 LINEAR REGULATOR B ON 19 B OFF 20 B SYNC OUT 11 10 L RTD
DR3
DR1
DR1
DR2 Q
14 L GATE 1
VREF 5
MASTER BIAS & UVLO
ONE SHOT SQ RQ
NEG EDGE DELAY
T Q DR2 16 L GATE 2
+ - 0.5V
6
L ILIM
ON/OFF 15 SS QS QR + - VDD CLK OSCILLATOR SS 17 PGND 18 GND 4 RT 9 CT 3 SS CAP RESONANT THRESHOLD DETECTOR - - + +
8 7 1
LEA OUT LEA- LEA+
1
ML4877
PIN CONFIGURATION
ML4877 20-Pin SSOP (R20)
LEA+ AZR SS CAP RT VREF L ILIM LEA- LEA OUT CT L RTD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 B OFF B ON GND PGND L GATE 2 ON/OFF L GATE 1 VDD HVDD B SYNC OUT
TOP VIEW
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1 2
LEA+ AZR
Positive input for lamp error amp Connection to gate of external FET for high voltage regulator. Internally a zener diode to ground. Connection of optional external soft start capacitor
11 12 13
B SYNC OUT HVDD VDD L GATE1
Output of MOSFET driver to gate of synchronous FET catch diode. Battery power input to linear regulator Output of linear regulator. Positive power for IC. Output of MOSFET driver. Connection to gate of one side of inverter FET drive pair. Logic input for chip Output of MOSFET driver. Connection to gate of one side of inverter FET drive pair. Power ground Signal ground Connection to primary side of gate pulse transformer Output of MOSFET driver. Connection to gate of FET that disables the input power.
3 4 5 6 7 8
SS CAP RT VREF L ILIM LEALEA OUT
14 Oscillator timing resistor Voltage reference output 15 Input to current limit amplifier 16 Negative input for lamp error amplifier Output of lamp error amplifier. External compensation capacitor connects between this pin and LEA. Oscillator timing capacitor Input to resonant threshold detector 20 17 18 19
ON/OFF L GATE2
PGND GND B ON B OFF
9 10
CT L RTD
2
ML4877
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ............................................... 75mA Output Current, Source or Sink ............................. 250mA Voltage on Pins LEA+, AZR, SS CAP, RT, VREF, L ILIM, LEA-, LEA OUT, CT, B SYNC OUT, VDD, L GATE 1, ON/OFF, L GATE 2, PGND, GND, B ON, B OFF ............................... -0.3V to VDD +0.3V Voltage on HVIDD .................................................... 20V Current into L RTD ............................................... 10mA Junction Temperature .............................................. 150C Storage Temperature Range ....................... -65C to 150C Lead Temperature (Soldering 10 sec.) ..................... 260C Thermal Resistance (qJA) .................................... 100C/W
OPERATING CONDITIONS
Temperature Range ML4877C ................................................... 0C to 70C ML4877E...............................................-20C to 70C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VDD = 5V 5%, TA= Operating Temperature Range, CT = 47pF, RT = 82kW (Note 1)
SYMBOL CURRENT REGULATOR ERROR AMPLIFIER Open Loop Gain Output High Output Low Bandwidth (-3dB) Common Mode Voltage Range Input Bias Current Input Offset Voltage Soft Start Charge Current Soft Start Threshold (LEA OUT) CURRENT LIMIT COMPARATOR Current Threshold Input Bias Current Propagation Delay OUTPUT DRIVERS Output High - B SYNC OUT, B OFF Output Low - B SYNC OUT, B OFF Rise & Fall time - B SYNC OUT, B OFF Output High - B ON Output Low - B ON Fall Time - B ON ONE SHOT Pulse Width 100 150 200 ns VDD 5V, ILOAD = 12mA ILOAD 12mA CLOAD =100pF VDD 5V, ILOAD = 12mA ILOAD 50mA CLOAD = 2400pF (Note 2) 4.625 4.625 4.8 0.2 20 4.8 0.2 45 0.375 80 0.375 50 V V ns V V ns VILIM = 0.1V (Note 2) 450 500 50 150 550 100 250 mV nA ns VSSCAP = 1V VSSCAP = 1V -5 550 2 0 50 0 750 ILOAD = 5A ILOAD = 25A 2.8 60 3.0 0.4 1 1.0 100 5 950 2.5 0.7 70 dB V V MHz V nA mv nA V PARAMETER CONDITIONS MIN TYP MAX UNITS
3
ML4877
ELECTRICAL CHARACTERISTICS
SYMBOL DELAY TIMER Delay Time HIGH VOLTAGE INVERTER Oscillator Nominal Frequency Discharge Current Peak Voltage Valley Voltage Output Drivers Output High - L GATE 1, 2 Output Low - L GATE 1, 2 Rise & Fall Time - L GATE 1, 2 Resonant Threshold Detector Threshold Hysteresis Lamp Out Detect Threshold Latch Inhibit Threshold (SSCAP) Under Voltage Detector Start Up Threshold Hysteresis Logic Interface (ON/OFF) V IH VIL Input Bias Current Linear Regulator Aux Zener Reference Voltage (AZR) Regulator Voltage (VDD) Regulator Source Current Drop Out Voltage Drop Out Voltage HVDD Input Voltage Range IAZR = 10A HVDD = 12V External to device IHVDD = 1mA lHVDD = 5mA 5 12.3 4.75 13.5 5.0 10 30 125 90 275 18 14.7 5.35 V V mA mA mA V ON/OFF = 3V 2.5 0.5 10 25 V V A 3.8 150 4.1 300 4.4 450 V mV LRTD > VDD + 0.1V -2 VDD 2.5 2 % V 0.45 0.15 0.8 03 1.15 0.45 V mV VDD = 5V, ILOAD 12mA ILOAD = 50mA CLOAD =1000pF 4.625 4.8 0.2 20 0.375 50 V V ns VCT = 2V 68 500 2.3 0.8 80 700 2.5 1 92 900 2.7 1.2 kHz A V V 20 35 55 ns PARAMETER
(Continued)
CONDITIONS MIN TYP MAX UNITS
4
ML4877
ELECTRICAL CHARACTERISTICS
SYMBOL BIAS VDD Supply Current VDD Supply Current VREF Load Regulation VREF Output Voltage VREF Line Regulation VREF Line, Load, Temp
Note 1: Note 2:
(Continued)
CONDITIONS MIN TYP MAX UNITS
PARAMETER
ON/OFF = "I", no load ON/OFF = "0", HVDD = 12V ILOAD = 25A TA = 25C 2.47
375 1 10 2.5 20 2.465 2.5
450 10 20 2.53 30 2.535
A A mV V mV V
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Actual load is 1200pF. The 2:1 transformer reflects an effective 2400pF.
5
ML4877
U2-A 5 TO 18V IN C7 C8 R1 *OPTIONAL SEE NOTE T2 C1 Q1 R7 10k AZR 2 HVDD 12 VDD 13 VDD LINEAR REGULATOR ONE SHOT 5 C3 1.0F MASTER BIAS & UVLO DR3 DR1 DR1 DR2 VREF NEG EDGE DELAY S S Q Q L ILIM
+ -
D1 Q2 U2-B OR OPTIONAL L1 100h
C9
B ON 19
B ON 20
B SYNC 11 10
T1 L RTD C6 0.1F
C11 39pF
GATE1 14 GATE2 16
Q T Q DR2 Q4
6
R6 O.5 R6 100k
0.5V ON/OFF 8 15 SS
+ -
LEA OUT C4 LEA- 0.047F 7 1 R5 100k
Q Q
S R
VDD
CLK
OSCILLATOR
17 PGND
18 GND RT R2 82k
4
9 CT C5 47pF C2 0.1F
Figure 1. Typical Application Schematic for the ML4877
6
+
RESONANT THRESHOLD DETECTOR
R4 1.6M
SS
3 SS CAP
LAMP
-
+ -
ML4877
FUNCTIONAL DESCRIPTION
The ML4877 consists of a PWM regulator, a lamp driver/ inverter, a linear regulator and control circuits. This IC, in conjunction with external components, converts a DC battery voltage into the high voltage and high frequency AC signal required to start and drive miniature cold cathode fluorescent lamps. Typical application circuits are shown in Figure 1 and Figure 5. Note: Please read the Power Sequencing section below prior to using the ML4877. LAMP DRIVER The lamp driver, sometimes referred to as a lamp inverter, is comprised of a PWM regulator and a Royer type inverter circuit to drive the lamp. The PWM regulator, in a buck configuration, controls the magnitude of the lamp current to provide the dimming capability. Figure 2 shows a simplified circuit to more easily illustrate the operation of the circuit. Due to the presence of the buck inductor, L1, the circuit shown in Figure 2 is essentially a current fed parallel loaded resonant circuit. Lm is the primary inductance of the output transformer, T1, which tunes with the resonant capacitor CR to set the resonant frequency of the inverter. The oscillator frequency is always set lower than the natural resonant frequency to ensure synchronization. The current source IC models the current through the buck inductor L1. The MOSFETs, (Q3 and Q4) are alternately turned on with a constant 50% duty cycle signal (L GATE1, L GATE2) at one-half the frequency of the oscillator. In this way each transistor pulses, or excites, the resonant tank on each half cycle. The combination of these two signals appear across the primary winding of the output transformer as a sinusoidal waveform. This voltage is multiplied by the step-up turns ratio of the output transformer and impressed across the lamp. The output transitions are controlled by feedback through the L RTD pin by sensing the voltage at the center tap of the output transformer. Each time this signal reaches the minimum resonant threshold detection point an internal clock pulse is generated to keep the system synchronized. Figure 3 shows some of these representative waveforms at the important nodes of the circuit. The PWM regulator is comprised of a MOSFET (U2-A), inductor L1, and the gate control and drive circuitry as shown in Figure 1. A signal with a constant pulse width of I 50ns is applied to the primary of the 2:1 pulse transformer T2, rectified by diode D1, and used to charge the gate capacitance of U2-A, thereby turning it on. The turn off is controlled by discharging this capacitance through MOSFET Q2. The pulse width of the signal on the gate of Q2 (B OFF) varies according to the difference of the amplitude of the feedback signal on LEA+, and LEA-. The signal on LEA- is proportional to the AC current flowing in the lamp, while the signal on LEA+ is a function of the brightness control setting. The AC lamp current feedback signal is developed by monitoring the current through resistor R6 in the common source connection of the inverter MOSFETs, Q3 and Q4. The lamp current, and therefore brightness, is adjusted by varying the voltage applied to R4, at the brightness adjust control point. Increasing this voltage increases the brightness. OSCILLATOR The frequency of the oscillator in the ML4877 is set by selecting the values Of CT and RT. Figure 4 shows the
CT
IC
(c)
T1 Lm Lm
COUT T1 1:N
CLOCK
L GATE1
CR
LAMP
DRAIN-Q4
L GATE2
Q3 Q4
DRAIN-Q3
T1-CNTR-PRI SOURCE OF U2-A
Figure 2. Kelvin Sense Connections
Figure 3. Operating Waveforms of the Lamp Driver Section
7
ML4877
FUNCTIONAL DESCRIPTION
(Continued) By selecting the appropriate value the AC lamp current can be set to slowly increase with a controlled time constant. The capacitor value can be calculated according to the following formula. C = (3 X 10-7)TS (1) oscillator frequency versus the value of RT for different values Of CT. This nomograph may be used to select the appropriate value of RT and CT to achieve the desired oscillator frequency for the ML4877. LINEAR REGULATOR A linear voltage regulator is provided to power the low voltage and low current control circuitry on the ML4877. This is typically used when there is no separate 5V supply available at the inverter board. For operation up to 18V, the linear regulator is used by connecting the HVDD pin to the input battery voltage. For operation over 18V, a MOSFET, and a resistor (Q and R1, Figure 1) are connected as shown. The MOSFET is required to stand off the high voltage. The AZR pin is just a zener diode to ground used to bias the gate of Q1. LAMP OUT DETECT In those cases when there is no lamp connected, or the connection is faulty, the output voltage of the lamp driver circuit will tend to rise to a high level in an attempt to start the nonexistent lamp. The lamp out detect circuit on the ML4877 will detect this condition by sensing a voltage proportional to the center tap voltage on the primary of the output transformer, T1 on the L RTD pin. The ration of resistors R7 and R8 sets the lamp out detect threshold. When the voltage on the L RTD pin exceeds VDD, an internal latch is set and the lamp driver goes into a shutdown mode. The logic control pin ON/OFF must be cycled low, then high to reset the latch and return the lamp driver to the normal state. The input to the lamp out latch is inhibited by the signal on the soft start pin. The latch will not be set until the voltage on SS CAP (pin 3) rises to more than 4.2V nominally. SOFT START The capability to control the start up behavior is achieved by setting the value of a single capacitor, C2 in Figure 1.
1000
Where TS = Duration of the soft start sequence in seconds LOGIC CONTROL The ML4877 is controlled by a single logic input, ON/ OFF. A logic level high on this pin enables the lamp driver. A logic zero puts the circuit into a very low power state. POWER SEQUENCING It is important to observe correct power and logic input sequencing when powering up the ML4877. The following procedure must be observed to avoid damaging the device. 1. Apply the battery power to HVDD, or 2. If HVDD is not used. Apply the VDD voltage. With HVDD connected the VDD voltage is supplied by the internal regulator on the ML4877. 3. Apply a logic high to the ON/OFF input. Please refer to Application Note 32 for detailed application information beyond what is presented here.
APPLICATIONS SECTION
HIGH POWER INVERTER The ML4877 is easily adapted to high power CCFL inverter designs. Figure 5 displays a schematic of a 30W ML4877 application. This particular design employs PWM dimming in order to extend dimming range. The 30W inverter design is ideal for applications between the 20W and 30W range. Deep dimming capability is achieved via PWM technique with no flicker and no popon effects. Uniform intensity can be maintained across 1 to 8 lamps to well below 5%. Figure 6 provides a top view of an example of a ML4877 30W design. This design can be modified for 1 to 8 lamps and contains a PWM dimming interface using standard low cost components. For the latest application notes and other information, visit the Micro Linear website at www.microlinear.com.
FRQUENCY (kHz)
C
=
30
100
C
pF
C =
= C = 12 0p 81
46 pF
pF F
10 10
100 RESISTANCE (k)
1000
Figure 4. Oscillator Frequency Nomograph
8
ML4877
J1 GND VDD DIMMING 1 2 3 3 T1 1 C2 68pF 1kV C3 68pF 1kV C4 68pF 1kV C5 68pF 1kV J2 1 2 3 4 5 6 7 8 9 10 11 J3 C6 68pF 1kV C7 68pF 1kV C8 68pF 1kV C9 68pF 1kV 1 2 3 4 5 6 7 8 9 10 11
4, 10 L1 22H F1 4A C24 220F C22 220F C20 0.1F Q4 IRF7416 R17 20 C1 0.22F MKS-10 63V Q1 IRLR2905 9
5 8
12
CR6 SK34MSCT R5 30k CR5
R15 1k
R18 200 C23 1nF
Q7 2N3904
Q2 IRLR2905
C21 1nF R14 1k R13 10k Q6 2N3904
R16 20 Q8 2N3906
R6 7.5k
R11 0.2 1W
R12 0.2 1W
Q5 2N3904
C19 4.7nF
R7 10k
R8 91k C18 1nF C13 1F C17 4.7nF R4 6.2k
1 2 3 4 5 6 7 8 9 10
LEA+ B OFF AZR B ON SS CAP GND RT ML4877 PGND VREF L GATE 2 L ILIM ON/OFF LEA- U2 L GATE 1 LEA OUT VDD CT HVDD L RTD B SYNC OUT
20 19 18 17 16 15 14 13 12 11
R3 10k R9 143k
C14 C12 1F 1F
CR1 5.1V
C16 47pF
J1 1 2 R2 10k R6 390k 1
J2 2
5 6 C15 1F
8
+ -
R1 10k
CR3 1N4148
+
3
-
2
U1B
1
CR2 1N4148 Q3 2N3906 C10 0.033F
U1A 4
7 C11 1F
CR4 1N4148
R10 10k PWM Control
Figure 5. 30W Backlight CCFL Inverter with PWM Dimming
9
ML4877
Figure 6. 30W CCFL Inverter Board, 1 to 8 Lamps
10
ML4877
PHYSICAL DIMENSIONS
inches (millimeters)
Package: R20 20-Pin SSOP
0.279 - 0.289 (7.08 - 7.34)
20
0.205 - 0.213 (5.20 - 5.40)
PIN 1 ID
0.301 - 0.313 (7.65 - 7.95)
1
0.026 BSC (0.65 BSC)
0.068 - 0.078 (1.73 - 1.98)
0 - 8
0.066 - 0.070 (1.68 - 1.78)
0.009 - 0.015 (0.23 - 0.38)
SEATING PLANE
0.002 - 0.008 (0.05 - 0.20)
0.022 - 0.038 (0.55 - 0.95)
0.004 - 0.008 (0.10 - 0.20)
ORDERING INFORMATION
PART NUMBER ML4877CR (END OF LIFE) ML4877ER (OBSOLETE) TEMPERATURE RANGE 0C to 70C -20C to 70C PACKAGE Molded SSOP (R20) Molded SSOP (R20)
(c) Micro Linear 1998.
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
DS4877-01
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com
10/29/98 Printed in U.S.A.
11

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