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| PRELIMINARY PRODUCT FLYER Semiconductor Solutions for High Speed Communications and Fiber Optic Applications TethysTM 448 is optimized for SONET/SDH applications as a full-duplex sixteen STS-48/STM-16 or a mix of sixteen STS-12/STM-4 and STS-3/STM-1 MUX/DEMUX with full framer functionality including pointer processing, and overhead termination; ideal for aggregation, ADM and DWDM applications. In the demultiplex ingress direction, TethysTM 448 accepts either sixteen STS-48/ STM-16, or a mix of sixteen STS-12/STM-4 and STS-3/ STM-1 signals in serial 2.5 Gbit/s or serial 622 Mbit/s or serial 155 Mbit/s format. TethysTM 448 locates the incoming SONET/SDH frame, optionally de scrambles the data, monitors the TOH and POH, and provides STS-1 level pointer processing. In addition, TethysTM 448 supports TOH and POH overhead transparency. In the multiplex direction, TethysTM 448 accepts sixteen STS-48/STM-16 signals in serial 2.5 Gbit/s format. TethysTM 448 further provides corresponding functionality in the DEMUX direction. Applications ADM Metro Aggregation Digital Cross connects Repeaters DWDM Equipment Test Equipment TethysTM 448 Features Provides serial STS-48/STM-16, STS-12/STM-4 or STS-3/STM-1 links Differential CML 2.5 Gbit/s I/O interface to optics Differential CML 2.5 Gbit/s I/O interface to system/backplane TFI-5 Support Processes SONET/SDH sixteen STS-48/STM-16 or a mix of sixteen STM-12/STM-4 and STS-3/STM-1 on the line side interface Processes SONET/SDH sixteen STS-48/STM-16 on the system/client side serial 2.5 Gbit/s interface Provides line timing of all line and system side interfaces Processes SONET/SDH flexible concatenation streams of STS-2c, 3c, 4c, ... to 48c Supports auto-detection of concatenation streams STS-3c/STM-1, STS-12c/STM-4 and STS-48c/STM-16 Supports STS-1 level pointer processing of STS-48/STM-16 or STM-12/STM-4 or STS-3/STM-1 streams Provides interfaces for dropping alarm and status information, and for forcing alarm conditions Power dissipation of 15 W, depending on mode of operation Terminates and generates SONET section, line, and path layers Provides TOH and POH transparency Provides monitoring of POH bytes B3 and N1/Z5 Provides B2 SF/SD capability for Poisson and bursty error distribution Pro Provides full TOH/POH add/drop Provides STS-1 level POH add/drop Supports more than 746 UI programmable output skew on STS48/STM-16 output links to external cross-connects For diagnostic purposes, Tethys provides PRBS generator/checker and loop backs Te t h y s TM 4 4 8 PEB1756E Sixteen STS-48/STM-16 MUX/DEMUX Never stop thinking. PRELIMINARY PRODUCT FLYER Features (cont'd) Provides B1, B2, H1 and H2 bit error generation for both receive and transmit direction diagnostics Provides 1 second performance monitors 0.13 m process, 1.2 V core, 3.3 V I/O P-FCHBGA-1397 CBGA Motorola 32-bit synchronous microprocessor interface for configuration, control, and status monitoring Complies with GR-253, GR-1377, ITU-T G.707, and ANSI T1.105 Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes Specifications OIF TFI-5 Standards ANSI T1.105-2000-193R2 (DRAFT) ANSI T1.105.05-1994 T1X1.3/93-005RI -1993 preliminary GR-253-CORE Sept. 2000 Type 1397 ball BGA Sales Code - TOH/POH Drop 4 x STS-48 4 x STS-12 4 x STS-3 De-Framers Description - Alarm Drop Package P-FCHBGA-1397 Tethys 448 TOH/POH Add Alarm Force STS-48 #1 - #4 STS-12 #1 - #4 STS-3 #1 - #4 #1 - #4 4 x STS-48/STS-12/STS-3 Pointer Processor PRBS Gen/Chk #1 - #4 STS-48 #5 - #8 STS-12 #5 - #8 STS-3 #5 - #8 4 x STS-48 4 x STS-12 4 x STS-3 De-Framers 4 x STS-48 4 x STS-12 4 x STS-3 Framers STS-48 #1 - #4 DeMux 4 x STS-48 4 x STS-12 4 x STS-3 De-Framers Mux STS-48 #9 - #12 STS-12 #9 - #12 STS-3 #9 - #12 #13 - #16 4 x STS-48/STS-12/STS-3 Pointer Processor PRBS Gen/Chk #13 - #16 4 x STS-48 4 x STS-12 4 x STS-3 Framers STS-48 #13 - #16 STS-48 #13 - #16 STS-12 #13 - #16 STS-3 #13 - #16 4 x STS-48 4 x STS-12 4 x STS-3 De-Framers RX TX #1 - #4 STS-48 #1 - #4 STS-12 #1 - #4 STS-3 #1 - #4 4 x STS-48 4 x STS-12 4 x STS-3 Framers STS-48 #5 - #8 STS-12 #5 - #8 STS-3 #5 - #8 4 x STS-48 4 x STS-12 4 x STS-3 Framers 4 x STS-48/STS-12/STS-3 Pointer Interpreter PRBS Gen/Chk #1 - #4 4 x STS-48 4 x STS-12 4 x STS-3 De-Framers De-Mux/ iMux De-skew STS-48 #1 - #4 Mux STS-48 #9 - #12 STS-12 #9 - #12 STS-3 #9 - #12 4 x STS-48 4 x STS-12 4 x STS-3 Framers #13 - #16 4 x STS-48 4 x STS-12 4 x STS-3 Framers 4 x STS-48/STS-12/STS-3 Pointer Interpreter PRBS Gen/Chk 4 x STS-48 4 x STS-12 #13 - #16 4 x STS-3 De-Framers STS-48 #13 - #16 STS-48 #13 - #16 STS-12 #13 - #16 STS-3 #13 - #16 Alarm Force TOH/POH Add 32 bit data u-proc I/F JTAG I/F TOH/POH Drop Alarm Drop TethysTM 448 PEB1756E Block Diagram Published by Infineon Technologies AG PRELIMINARY PRODUCT FLYER Overview TethysTM 448 is a highly integrated device that implements full duplex SONET/SDH processing at STS-48/STM-16, STS-12/ STM-4 or STS-3/ STM-1 rates. In the rest of this document, only SONET terminology will be stated. However, SDH terminology applies equally well unless otherwise written. TethysTM 448 supports up to 40 Gbit/s bandwidth or 80 Gbit/s full-duplex. It provides section, line, and path overhead processing and supports framing, scrambling/de scrambling, alarm signal insertion/detection, bit interleaved parity (B1/B2/B3) processing, path overhead processing, pointer processing and TOH and POH transparency. It also provides substantial performance monitoring of TOH/POH overhead for receive direction with 1 second count accumulation. On the line side, sixteen STS-48's, or a mix of sixteen STS-12's and STS-3's are supported. The interface utilizes serial independent 2.5 Gbit/s links, serial independent 622 Mbit/s links or serial independent 155 Mbit/s respectively for each interface. The STS-48, STS-12 and STS-3 interfaces can be received at differing clock frequencies, depending on the SONET line clock variation of 20 ppm. Similarly, the STS-48, STS-12 or STS-3 outputs can be line timed to the STS-48 inputs. On the system/client side, sixteen STS-48 can be interfaced. In this case, serial 2.5 Gbit/s is utilized for the respective interfaces. The System side can support 16 independent STS-48 links. The selection/configuration of the system and line side interfaces is completely independent. All TOH (A1... E2) bytes can be added/dropped onto the parallel TOH/POH interfaces. This applies in both receive and transmit directions. All POH passing through the device can be added or dropped onto the TOH/POH ports. The TOH and POH ports are physically shared. Detected alarms like LOS, LOF, SEF, AIS-L can be dropped onto the parallel Alarm Drop Interfaces. This applies in both the receive and transmit directions. In addition, TethysTM 448 can drop the payload concatenation configuration onto the same interface. In TOH Transparency mode, J0, B1, E1, F1, K1, K2, D1-D12, S1, M0/M1 and E2 bytes are transparent through the device. In POH Transparency mode, all POH bytes, including the B3 bytes, are transparent as is. TOH/POH transparency can be implemented through the TOH/POH ADD/DROP ports using the dropped overhead and bit error masks on these interfaces. This applies to both the receive and transmit directions. TethysTM 448 can process any legal mix of flexible concatenated signals ranging from STS-1, STS-2c, STS-3c ... up to STS-48c. Each set of concatenated signals must fit inside an STS-3, STS-12 or STS-48 boundary (depending on whether the pointer processor is configured as an STS-3, STS-12 or STS-48) and must be formatted as an STS-Nc frame as defined in GR-253-CORE. TethysTM 448 provides the ability for certain frame structures to be automatically detected and configured into the device. This feature allows the user to interface to systems with unknown standard payload concatenation configurations. Various diagnostic features are provided. Framed PRBS-32 can be generated and checked on any channel via loopbacks. Errors can be inserted into B1, B2, H1 and H2 bytes on a bitby-bit basis. To support asynchronous timing between different physical ports, TethysTM 448 provides STS-1 level pointer processing for sixteen STS-48 or a mix of sixteen STS-12 and STS-3 interfaces in the receive direction. On the line side receive interface, all inputs can be asynchronous with frequency differences of 20 ppm. The pointer processor on the receive side adjusts for these differences and outputs the STS-48, STS-12 or STS-3 streams based on the line timed or system frequencies selected on the system side. In the transmit direction, the system side ingress ports and line side egress ports must be locked to the same frequency. TethysTM 448 aggregates all STS-48 ports from the system side to the line side in the transmit/multiplex direction. STS-3 and STS-12 rate streams received from the line side are always multiplexed into the STS-48 rate streams on the system side. In the receive direction, the de-aggregation of physical ports is the reverse of the transmit direction aggregation. To select the best timing available in the system, the S1 bytes are processed and the system has the option to select either timing from the line or timing from the local reference source. On the system side, the receive outputs can be line timed to their respective system side transmit inputs. TethysTM 448 generates and detects all SONET/SDH relevant alarms and defects, including LOS, LOF, RDI-L, REI-L, AIS-P, AIS-L and LOC on each line side and system side interface Published by Infineon Technologies AG PRELIMINARY PRODUCT FLYER Applications The application below shows how sixteen STS-48 signals can be connected to a TethysTM 448 device. TethysTM 448 receives a serial independent 2.5 Gbit/s format STS-48 frame from the optical device. It then performs framing, performance monitoring, and rate adaptation in the receive direction, and finally outputs a single STS-48 2.5 Gbit/s differential pair to the STS-48 link cross connect or the STS-48 optic transceivers. In the transmit direction, TethysTM 448 performs the reverse operation. TOH and POH interfaces may be added and dropped as required through the respective TethysTM 448 ports (not shown). Many other configuration options are possible that cannot be shown in this diagram. Please refer to the data sheet for more detailed information. 2.5G STS-48 Optics STS-48 Optics STS-48 Optics STS-48 Optics #4 #3 #2 #1 STS-48 4x2.5G #1 STS-48 1x2.5G STS-48 1x2.5G 2.5G STS-48 4x2.5G #8 STS-48 Link STS-48 4x2.5G #1 2.5G Cross STS-48 1x2.5G STS-48 1x2.5G Connect 2.5G STS-48 4x2.5G #8 Infineon Tethys 448 2.5G STS-48 Optics STS-48 Optics STS-48 Optics STS-48 Optics #16 #15 #14 #13 STS-48 4x2.5G STS-48 1x2.5G STS-48 Optics #1 2.5G 2.5G 2.5G STS-48 4x2.5G 2.5G STS-48 4x2.5G 2.5G STS-48 4x2.5G STS-48 1x2.5G STS-48 Optics #8 2.5G 2.5G 40G - STS-48 Cross Connect and Aggregation How to reach us: http://www.infineon.com Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 Munchen (c) Infineon Technologies AG 2003. All Rights Reserved. TethysTM is a trademark of Infineon Technologies AG. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in lifesupport devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Template: pb_tmplt.fm/4/2003-07-01 Published by Infineon Technologies AG 2003-07-01 R&L |
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