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| ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C SST55017A/B/CATA Flash Disk Controller Preliminary Specifications FEATURES: * Industry Standard ATA/IDE Bus Interface - Host Interface: 8 or 16 bit access - Support up to PIO Mode-4 * Interface for standard NAND Flash Media - Flash Media Interface: 8 bit access - Up to 1 Gbit flash media components - SST55LD017A: - supports up to 5 flash media devices directly for 128 MB maximum capacity - SST55LD017B/SST55LD017C: - supports up to 5 flash media devices directly for 640 MB maximum capacity - supports up to 16 flash media devices with external decoder for 2 GB maximum capacity * Low power, 3.3V core operation * 5.0V or 3.3V host interface through VDDQ pins * Low current operation: - Active mode: 25 mA/35 mA (3.3V/5.0V) (typical) - Sleep mode: 40 A/50 A (3.3V/5.0V) (typical) * Power Management Unit - Immediate disabling of unused circuitry * 20 Byte Unique ID for Enhanced Security - Factory Set 10 Byte Unique ID - User Programmable 10 Byte ID * Pre-programmed Embedded Firmware - Performs self-initialization on first system power-up - Executes industry standard ATA/IDE commands - Implements wear-leveling algorithms to substantially increase the longevity of flash media - Embedded Flash File System - Built-in ECC corrects up to 3 random 12-bit symbols of error per 512 Byte sector * Internal or External System Clock Option * Write-Protect (WP_PD#) pin for preventing data overwrites * Fast Sustained Read Performance - Up to 5.0 MB/sec * Fast Sustained Write Performance (Host to Flash) - SST55LD017A supports up to 1.2MB/sec - SST55LD017B supports up to 2.4MB/sec - SST55LD017C supports up to 4.0MB/sec * Multi-tasking Technology enables Fast Sustained Write Performance * Support for Both Commercial and Industrial Temperature Ranges - 0C to 70C for operating commercial - -40C to +85C for operating industrial * 100-lead TQFP package PRODUCT DESCRIPTION SST's ATA flash disk controller is the heart of a high-performance, flash media-based data storage system. The ATA flash disk controller recognizes the control, address, and data signals on the ATA/IDE bus and translates them into memory accesses to the standard NAND-type flash media. This technology suits solid state mass storage applications offering new, expanded functionality while enabling smaller, low power consuming, and lighter designs. The ATA/IDE interface is widely used in such products as portable and desktop computers, digital cameras, music players, handheld data collection scanners, PDAs, handy terminals, personal communicators, audio recorders, monitoring devices, and set-top boxes. Utilizing SST's proprietary SuperFlash embedded memory technology, The ATA flash disk controller is preprogrammed with an embedded flash file system which, upon power-up, recognizes the flash media devices and performs all the necessary handshaking routines for flash media support. This enables the product manufacturer a completely seamless integration of flash drive into an embedded design. The ATA flash disk controller integrates an on-chip clock circuitry and Serial Communication Interface (SCI) for system reset and user customization. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 1 The SST55LD017A is a standard performance ATA disk controller supporting capacities up to 128 MB. SST55LD017B is a high-performance ATA disk controller with sustained write performance up to 2.4 MB/ sec. SST55LD017C is a super high-performance ATA disk controller with sustained write performance up to 4.0 MB/sec. Both the SST55LD017B and SST55LD017C can support up to 5 flash media devices directly for a maximum capacity of 640 MB. By using an external decoder, the SST55LD017B and SST55LD017C can support up to 16 flash media devices for the equivalent capacity of 2 GB. Users can select either an internal or external system clock option for optimal performance vs. the supply current. The ATA flash disk controller comes packaged in an industry standard 100-lead TQFP package for easy integration into an SMT manufacturing process. The ATA flash disk controller also comes preprogrammed with a 10-byte unique serial ID. For even greater system security and data protection, the user has the option of programming an additional 10 Bytes of ID space to create a unique, 20 Byte ID. The controller also offers a WP_PD# pin to protect data stored on flash media from unauthorized overwrites. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications TABLE OF CONTENTS PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Performance-optimized ATA Flash Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 Microcontroller Unit (MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Flash File System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-tasking Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 6 6 6 6 6 2.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.0 CAPACITY SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.0 SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.0 EXTERNAL CLOCK INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.0 CONFIGURABLE WRITE-PROTECT/POWER-DOWN MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 Write-Protect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.0 POWER-ON AND BROWN-OUT RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.0 I/O TRANSFER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.0 SOFTWARE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10.1 ATA Flash Disk Controller Drive Register Set Definitions and Protocol. . . . . . . . . . . . . . . . . . . . . . . . 15 10.1.1 ATA Flash Disk Controller Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 ATA Flash Disk Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.1 Data Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.2 Error Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.3 Feature Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.4 Sector Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.5 Sector Number (LBA 7-0) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.6 Cylinder Low (LBA 15-8) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (c)2002 Silicon Storage Technology, Inc. S71211-01-000 15 15 15 16 16 16 16 16 7/02 2 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.1.2.7 Cylinder High (LBA 23-16) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.8 Drive/Head (LBA 27-24) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.9 Status & Alternate Status Registers (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.10 Device Control Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.11 Drive Address Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2.12 Command Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 ATA Flash Disk Controller Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.1 Check-Power-Mode - 98H or E5H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.2 Execute-Drive-Diagnostic - 90H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.3 Format-Track - 50H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4 Identify-Drive - ECH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.1 General Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.2 Default Number of Cylinders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.3 Default Number of Heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.4 Default Number of Sectors per Track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.5 Number of Sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.6 Serial Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.7 Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.8 Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.9 ECC Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.10 Firmware Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.11 Model Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.12 Read-/Write-Multiple Sector Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.13 Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.14 PIO Data Transfer Cycle Timing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.15 Translation Parameters Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.16 Current Number of Cylinders, Heads, Sectors/Track . . . . . . . . . . . . . . . . . . 10.2.1.4.17 Current Capacity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.18 Multiple Sector Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.19 Total Sectors Addressable in LBA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.20 Advanced PIO Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.4.21 Minimum PIO Transfer Cycle Time Without Flow Control . . . . . . . . . . . . . . 10.2.1.4.22 Minimum PIO Transfer Cycle Time With IORDY . . . . . . . . . . . . . . . . . . . . . 10.2.1.5 Idle - 97H or E3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.6 Idle-Immediate - 95H or E1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.7 Initialize-Drive-Parameters - 91H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.8 Read-Buffer - E4H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.9 Read-Multiple - C4H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.10 Read-Long-Sector - 22H or 23H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.11 Read-Sector(s) - 20H or 21H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.12 Read-Verify-Sector(s) - 40H or 41H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.13 Recalibrate - 1XH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.14 Seek - 7XH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.15 Set-Features - EFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.16 Set-Multiple-Mode - C6H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.17 Set-Sleep-Mode - 99H or E6H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.18 Set-WP_PD#-Mode - 8BH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.19 Standby - 96H or E2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.20 Standby-Immediate - 94H or E0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.21 Write-Buffer - E8H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.22 Write-Long-Sector - 32H or 33H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1.23 Write-Multiple - C5H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (c)2002 Silicon Storage Technology, Inc. S71211-01-000 16 17 18 18 19 19 20 21 21 22 22 24 24 24 24 24 24 24 24 24 24 24 24 24 25 25 25 25 25 25 25 25 25 25 26 26 26 27 28 28 29 29 29 30 31 31 32 32 33 33 33 34 7/02 10.2 ATA Flash Disk Controller Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.24 Write-Sector(s) - 30H or 31H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2.1.25 Write-Verify - 3CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2.2 Error Posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.0 ELECTRICAL SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.1.1 Input Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1.2 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.2.1 Host Side Interface I/O Input (Read) Timing Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.2.2 Host Side Interface I/O Output (Write) Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.2.3 Media Side Interface I/O Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.0 APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 Differences between SST ATA Flash Disk Controller and ATA/ATAPI-5 Specifications . . . . . . . . . . . 48 12.1.1 Idle Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1.2 Recovery from Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2 Reference Design Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3 Bill of Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.0 PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 14.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LIST OF FIGURES FIGURE 2-1: SST ATA Flash Disk Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 3-1: Pin Assignments for 100-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 8-1: Power-On and Brown-Out Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FIGURE 11-1: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FIGURE 11-2: Host Side Interface I/O Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FIGURE 11-3: Host Side Interface I/O Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 11-4: Media Command Latch Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FIGURE 11-5: Media Address Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FIGURE 11-6: Media Data Loading Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FIGURE 11-7: Media Data Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FIGURE 12-1: Schematic for ATA Flash Module, up to 640 MByte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 4 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications LIST OF TABLES TABLE 3-1: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TABLE 3-2: Host Side Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 3-3: Flash Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 3-4: Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3-5: External Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3-6: Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 4-1: Default ATA Flash Drive Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 4-2: Functional Specification of SST55LD017A/SST55LD017B/SST55LD017C. . . . . . . . . . . . . . 12 TABLE 8-1: Power-On and Brown-Out Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 9-1: I/O Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 10-1: Task File Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 10-2: ATA Flash Disk Controller Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 10-3: Diagnostic Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TABLE 10-4: Identify-Drive Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 10-5: Features Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 10-6: Transfer Mode Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 10-7: Error and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TABLE 11-1: Absolute Maximum Power Pin Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 11-2: Recommended System Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TABLE 11-3: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 11-4: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 11-5: Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 11-6: Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 11-7: Input Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 11-8: Input Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 11-9: Input Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TABLE 11-10: Input Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TABLE 11-11: Output Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TABLE 11-12: Output Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TABLE 11-13: Output Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TABLE 11-14: Output Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TABLE 11-15: DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TABLE 11-16: Host Side Interface I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TABLE 11-17: Host Side Interface I/O Write Timing Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TABLE 11-18: SST55LD017A/B/C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TABLE 12-1: Sample Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TABLE 12-2: Optional Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 TABLE 12-3: Supported NAND Flash Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 5 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 1.0 GENERAL DESCRIPTION The SST's ATA flash disk controller contains a microcontroller and embedded flash file system integrated in a 100lead TQFP package. Refer to Figure 2-1 for SST's ATA flash disk controller block diagram. The controller interfaces with the host system allowing data to be written to and read from the flash media. 1.1.5 Embedded Flash File System Embedded Flash File System is an integral part of the SST's ATA flash disk controller. It contains MCU Firmware that performs the following tasks: 1. Translates host side signals into flash media Writes and Reads. 2. Provides flash media wear leveling to spread the Flash writes across all unused memory address space to increase the longevity of flash media. 3. Keeps track of data file structures. 1.1.6 Error Correction Code (ECC) The SST's ATA flash disk controller utilizes 72-bit ReedSolomon Error Detection Code (EDC) and Error Correction Code (ECC), which provides following error immunity for each 512-Byte block of data: 1. Corrects up to three random 12-bit symbol errors 2. Corrects single bursts up to 25 bits 3. Detects single bursts up to 61 bits and double bursts up to 15 bits 4. Detects up to six random 12-bit symbol errors. 1.1.7 Serial Communication Interface (SCI) The Serial Communication Interface is designed to enable the user to restart the self-initialization process and to customize the Drive Identification Information. 1.1.8 Multi-tasking Technology Multi-tasking technology enables fast, sustained write performance by allowing concurrent Read, Program, and Erase operations to multiple flash media devices. 1.1 Performance-optimized ATA Flash Disk Controller The heart of the Flash Drive is the ATA flash disk controller which translates standard ATA signals into flash media data and control signals. The following components contribute to the ATA flash disk controller's operation. 1.1.1 Microcontroller Unit (MCU) The MCU translates ATA/IDE commands into data and control signals required for flash media operation. 1.1.2 Internal Direct Memory Access (DMA) The ATA flash disk controller uses Internal DMA allowing instant data transfer from buffer to flash media. This implementation eliminates microcontroller overhead associated with traditional, firmware-based approach, thereby increasing the data transfer rate. 1.1.3 Power Management Unit (PMU) Power Management Unit controls the power consumption of the ATA flash disk controller. The PMU dramatically reduces the power consumption of ATA flash disk controller by putting the part of the circuitry that is not in operation into sleep mode. 1.1.4 SRAM Buffer A key contributor to the ATA flash disk controller performance is an SRAM buffer. The buffer optimizes host's data transfer to and from flash media. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 6 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 2.0 FUNCTIONAL BLOCKS ATA Flash Disk Controller Embedded Flash File System SRAM Buffer MCU NAND Flash Media Multi-tasking Interface HOST ATA/IDE BUS ECC Internal DMA PMU SCI 540 ILL B1.6 FIGURE 2-1: SST ATA FLASH DISK CONTROLLER BLOCK DIAGRAM (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 7 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 3.0 PIN ASSIGNMENTS The signal/pin assignments are listed in Table 3-1. Low active signals have a "#" suffix. Pin types are Input, Output or Input/Output. Section 11.0 defines the DC characteristics for all input and output type structures. The ATA flash disk controller functions in ATA Mode, which is compatible with IDE hard disk drives. Table 3-2 to Table 3-6 describe the I/O signals. Signals whose source is the host are designated as inputs while signals that the ATA flash disk controller sources are outputs. Refer to Section 11.0 for definitions of Input and Output types. SCIDOUT SCIDIN SCICLK DNU VSS (IO) DNU DNU DNU DNU DNU DNU DNU DNU VDD (IO) DNU DNU DNU DNU VSS (IO) INTCLKEN# DNU DNU VDD (Core) POR# FWP# 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 D10 D2 D9 D1 VSS (IO) D8 D0 D7 D15 VDDQ (IO) IOCS16# PDIAG# VSS (IO) DNU TIE_UP A0 A1 A2 TIE_DN RESET# TIE_DN TIE_DN VDDQ (IO) TIE_DN TIE_DN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100-lead TQFP Top View 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TIE_UP TIE_DN IOWR# VSS (Core) TIE_DN IORD# TIE_DN TIE_DN CS3FX# CS1FX# INTRQ VSS (IO) DASP# WP_PD# CSEL VDDQ (IO) D14 D6 D13 D5 VSS (IO) D12 D4 D11 D3 Note: DNU means Do Not Use, must be left unconnected. VSS (Core) FRDYbsy# FRE# FWE# FCLE FALE FAD0 FAD1 FAD2 VSS (IO) EXTCLKIN EXTCLKOUT VDD (IO) FAD3 FAD4 FAD5 FAD6 FAD7 VSS (IO) FCE0# FCE1# FCE2# FCE3# FCE4# SCIEN# 540 100-tqfp ILL P01.11 FIGURE 3-1: PIN ASSIGNMENTS FOR 100-LEAD TQFP (c)2002 Silicon Storage Technology, Inc. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S71211-01-000 7/02 8 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications TABLE Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 3-1: PIN ASSIGNMENTS Signal Name SCIDOUT Pin Type O I I I/O Type1 O1 I5Z I5Z TABLE Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 3-1: PIN ASSIGNMENTS (CONTINUED) Signal Name D11 D4 D12 VSS (IO) D5 D13 D6 D14 VDDQ (IO) CSEL WP_PD# DASP# VSS (IO) INTRQ CS1FX# CS3FX# TIE_DN TIE_DN IORD# TIE_DN VSS (Core) IOWR# TIE_DN TIE_UP TIE_DN TIE_DN VDDQ (IO) TIE_DN TIE_DN RESET# TIE_DN A2 A1 A0 TIE_UP DNU VSS (IO) PDIAG# IOCS16# VDDQ (IO) D15 D7 D0 D8 VSS (IO) D1 D9 D2 D10 Pin Type I/O I/O I/O I/O I/O I/O I/O I I I/O O I I I/O Type1 I2D/O4 I2D/O4 I2D/O4 I2D/O4 I2D/O4 I2D/O4 I2D/O4 I1U I2U I2U/O2 O2 I3U I3U SCIDIN SCICLK DNU2 VSS (IO) DNU DNU DNU DNU DNU DNU DNU DNU VDD (IO) DNU DNU DNU DNU VSS (IO) INTCLKEN# DNU DNU VDD (Core) POR# FWP# VSS (Core) FRDYbsy# FRE# FWE# FCLE FALE FAD0 FAD1 FAD2 VSS (IO) EXTCLKIN EXTCLKOUT VDD (IO) FAD3 FAD4 FAD5 FAD6 FAD7 VSS (IO) FCE0# FCE1# FCE2# FCE3# FCE4# SCIEN# D3 I I3U I I5U I I3U I O I O O O O I/O I/O I/O I O I/O I/O I/O I/O I/O O O O O O I I/O I5Z O3 I6Z O3 O3 O3 O3 I5U/O3 I5U/O3 I5U/O3 I6Z O1 I5U/O3 I5U/O3 I5U/O3 I5U/O3 I5U/O3 O1 O1 O1 O1 O1 I5U I2D/O4 I I I I I4U I2D I2D I2D I/O O I/O I/O I/O I/O I/O I/O I/O I/O I2U/O2 O4 I2D/O4 I2D/O4 I2D/O4 I2D/O4 I2D/O4 I2D/O4 I2D/O4 I2D/O4 T3-1.18 1211 1. Please refer to Section 11.1 for details. 2. All DNU pins should not be connected. S71211-01-000 7/02 (c)2002 Silicon Storage Technology, Inc. 9 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 3.1 Pin Description TABLE Symbol A2 - A0 D15 - D0 3-2: HOST SIDE INTERFACE Type1 I I/O Pin 83,84,85 Name and Functions A[2:0] are used to select one of eight registers in the Task File. 92,59,57, Data bus 54,52,100, 98,95,93, 58,56,53, 51,99,97, 94 66,67 61 CS1FX# is the chip select for the task file registers while CS3FX# is used to select the Alternate Status register and the Device Control register. This internally pulled-up signal is used to configure this device as a Master or a Slave. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. The pin setting should remain the same from power-up to power-down. This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the chip. The I/O Write strobe pulse is used to clock I/O data into the chip. This output signal is asserted low when the device is indicating a word data transfer cycle. This signal is the active high Interrupt Request to the host. The Pass Diagnostic signal in the Master/Slave handshake protocol. The Drive Active/Slave Present signal in the Master/Slave handshake protocol. This input pin is the active low hardware reset from the host. The WP_PD# pin can be used for either the Write-Protect mode or Power-Down mode, but only one mode is active at any time. The Write-Protect or Power-Down modes can be selected through the host command. The Write-Protect mode is the factory default setting. For details, please refer to Section 7.0 and Section 10.2.1.18 T3-2.11 1211 CS1FX#, CS3FX# CSEL I I IORD# IOWR# IOCS16# INTRQ PDIAG# DASP# RESET# WP_PD# I I O O I/O I/O I I 70 73 90 65 89 63 81 62 1. Please refer to Section 11.1 for detail TABLE Symbol FWP# FRDYbsy# FRE# FWE# FCLE FALE 3-3: FLASH MEDIA INTERFACE Type O I O O O O I/O 25 27 28 29 30 31 43,42,41, 40,39,34, 33,32 49,48,47, 46,45 Pin Name and Functions This signal is an Active Low Flash Media Chip Write-Protect. Connect this pin to NAND Flash Media Write-Protect Pin. This signal is Flash Media Chip Ready/Busy#. Signal High is Flash Media Ready signal. Low is Busy. This signal is an Active Low Flash Media Chip Read. This signal is an Active Low Flash Media Chip Write. This signal is an Active High Flash Media Chip Command Latch Enable. This signal is an Active High Flash Media Chip Address Latch Enable. These are Flash Media Chip Address/Data Bus pins. FAD7-FAD0 FCE4#-FCE0# O These are Active Low Flash Media Chip Enable pins. T3-3.7 1211 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 10 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications TABLE Symbol SCIDOUT SCIDIN SCICLK SCIEN# 3-4: SERIAL COMMUNICATION INTERFACE (SCI) Type O I I I Pin 1 2 3 50 Name and Functions This signal is SCI interface data output. This signal is SCI interface data input. This signal is SCI interface clock. This signal is Active Low SCI interface enable. T3-4.8 1211 TABLE Symbol 3-5: EXTERNAL CLOCK OPTION Type I I O Pin 20 36 37 Name and Functions Internal Clock enable pin. Signal low enables an internal clock, high enables external clock source. External Clock source input pin. External Clock source output pin. T3-5.1 1211 INTCLKEN# EXTCLKIN EXTCLKOUT TABLE Symbol VSS (IO) VSS (Core) VDD (IO) VDD (Core) VDDQ (IO) POR# TIE_UP TIE_DN DNU 3-6: MISCELLANEOUS Type PWR PWR PWR PWR PWR I I I Pin 5,19,35,44,55,64,88,96 26,72 14,38 23 60,78,91 24 75, 86 68,69,71,74,76,77,79,80,82 4,6,7,8,9,10,11,12,13,15,16, 17,18,21,22,87 Name and Functions Ground for I/O Ground for Core VDD (3.3V) VDD (3.3V) VDDQ (5V/3.3V) for Host interface Power On Reset. Active Low, Refer to Section 8.0. Pins need to be connected to VDDQ. Pins need to be connected to VSS. Do Not Use, must be left unconnected. T3-6.11 1211 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 11 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 4.0 CAPACITY SPECIFICATION Table 4-1 shows the default capacity and specific settings for heads, sectors and cylinders. Users can change the default settings in the Drive ID table (see Table 10-4) for customization. It should be noted that the total Flash Drive capacity should not exceed the total number of bytes listed in Table 4-1. TABLE 4-1: DEFAULT ATA FLASH DRIVE SETTINGS Total Bytes1 8,028,160 16,023,552 24,051,712 32,047,104 48,037,888 64,028,672 96,075,776 128,057,344 192,413,696 256,901,120 384,491,520 512,483,328 640,475,136 Cylinders 245 489 367 489 733 977 733 977 734 980 745 993 1241 Heads 2 2 4 4 4 4 8 8 16 16 16 16 16 Sectors 32 32 32 32 32 32 32 32 32 32 63 63 63 T4-1.4 1211 Capacity 8 MB 16 MB 24 MB 32 MB 48 MB 64 MB 96 MB 128 MB 192 MB2 256 MB2 384 MB2 512 MB2 640 MB2 1. C, H, and S can be user-configurable, but the total number of bytes should not exceed the default setting 2. Only SST55LD017B and SST55LD017C support these capacities. 4.1 Functional Specifications Table 4-2 shows the performance and the maximum capacity supported by each controller. TABLE Functions ATA Controller Supported Capacity ATA Controller PerformanceSustained Write speed Multi-tasking Enabled Support 2GB Through External Decoding 4-2: FUNCTIONAL SPECIFICATION SST55LD017A 8MB to 128MB Up to 1.2MB/sec No No OF SST55LD017A/SST55LD017B/SST55LD017C SST55LD017B SST55LD017C 8MB to 640MB, up to 2GB with External Decoding1 Up to 4.0 MB/sec with 4-chip multi-tasking2 Up to 3.2 MB/sec with 3-chip multi-tasking2 Yes Yes T4-2.2 1211 8MB to 640MB, up to 2GB with External Decoding1 Up to 2.4MB/sec with 2-chip multi-tasking2 Up to 1.2MB/sec with 1-chip operation Yes Yes 1. Please refer to the application note, Design Consideration for High Capacity Flash Drive 2. The ATA flash disk controller handles multiple flash operations. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 12 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 5.0 SERIAL COMMUNICATION INTERFACE The Serial Communication Interface is designed to enable the user to restart the self-initialization process and to customize the Drive Identification Information. The Serial Communication Interface consists of 4 signals: SCIDOUT, SCIDIN, SCICLK and SCIEN#. Please refer to the Design Consideration for ATA Flash Disk Controller's Serial Communication Interface application note for further details. 6.0 EXTERNAL CLOCK INTERFACE The External Clock interface allows an external clock source to drive the ATA flash disk controller. While the controller has an internal clock source, the External Clock interface allows slowing of the clock operation to limit the peak current. Please see the External Clock Operation for ATA Flash Disk Controller application note for further details. The External Clock interface consists of three signals: INTCLKEN#, EXTCLKIN, and EXTCLKOUT. The INTCLKEN# pin selects between external and internal clock sources for the ATA flash disk controller. If this pin is pulled low before device power-up, then the internal clock source is selected; otherwise, the external clock source is selected. The EXTCLKIN and EXTCLKOUT signals are the input and output clock signals, respectively. Please see Section 12.2 for the detailed circuit schematic. 7.0 CONFIGURABLE WRITE-PROTECT/POWER-DOWN MODES The WP_PD# pin can be used for either Write-Protect mode or Power-Down mode, but only one mode is active at any time. Either mode can be selected through the host command, Set-WP_PD#-Mode, explained in Section 10.2.1.18. Once the mode is set with this command, the device will stay in the configured mode until the next time this command is issued. Power-off or reset will not change the configured mode. 7.1 Write-Protect Mode When the device is configured in the Write-Protect mode, the WP_PD# pin offers extended data protection. This feature can be either selected through a jumper or host logic to protect the stored data from inadvertent system writes or erases, and viruses. The Write-Protect feature protects the full address space of the data stored on the flash media. In the Write-Protect mode, the WP_PD# pin should be asserted prior to issuing the destructive commands: FormatTrack, Write-Buffer, Write-Long-Sector, Write-Multiple, Write-Sector(s), or Write-Verify. This will force the ATA flash disk controller to reject any destructive commands from the ATA interface. All destructive commands will return 51H in the Status register and 04H in the Error register signifying an invalid command. All non-destructive commands will be executed normally. 7.2 Power-Down Mode When the device is configured in the Power-Down mode, if the WP_PD# pin is asserted during a command, the ATA disk controller completes the current command and returns to the standby mode immediately to save power. Afterwards, the device will not accept any other commands. Only a power-on reset or hardware reset will bring the device to normal operation with the WP_PD# pin de-asserted. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 13 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 8.0 POWER-ON AND BROWN-OUT RESET CHARACTERISTICS VDD 90% 90% POR# tw tD 540 ILL F04-1.8 FIGURE TABLE Item 8-1: POWER-ON AND BROWN-OUT RESET TIMING 8-1: POWER-ON AND BROWN-OUT RESET TIMING Min 0.1 30 Max Units ms s T8-1.1 1211 Symbol tw tD POR Wait Time Brown-out Delay Time 9.0 I/O TRANSFER FUNCTION The default operation for ATA flash disk controller is 16-bit. ATA flash disk controller, however, permits 8-bit data access if the host issues a Set Feature Command to enable 8-bit mode. The following table defines the function of various operations. TABLE 9-1: I/O FUNCTION CS3FX# VIL VIH VIH VIH VIH VIH VIL VIL VIL CS1FX# VIL VIH VIL VIL VIL VIL VIH VIH VIH A0-A2 X X 1-7H 1-7H 0 0 6H 6H 7H IORD# X X VIH VIL VIH VIL VIH VIL VIL IOWR# X X VIL VIH VIL VIH VIL VIH VIH D15-D8 Undefined High Z X High Z In1 Out1 X High Z High Z D7-D0 Undefined High Z Data In Data Out In Out Control In Status Out Data Out T9-1.2 1211 Function Code Invalid Mode Standby Mode Task File Write Task File Read Data Register Write Data Register Read Control Register Write Alt Status Read Drive Address 1. If 8-bit data transfer mode is enabled. In 8-bit data transfer mode, High Byte is undefined for Data Out. For Data In, X can be VIH or VIL, but no other value. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 14 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.0 SOFTWARE INTERFACE 10.1 ATA Flash Disk Controller Drive Register Set Definitions and Protocol 10.1.1 ATA Flash Disk Controller Addressing The I/O decoding for an ATA flash disk controller is as follows: TABLE 10-1: TASK FILE REGISTERS Registers CS3FX# 1 1 1 1 1 1 1 1 0 0 CS1FX# 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 1 A0 0 1 0 1 0 1 0 1 0 1 IORD# = 0 (IOWR#=1) Data (Read) Error Sector Count Sector Number (LBA 7-0) Cylinder Low (LBA 15-8) Cylinder High (LBA 23-16) Drive/Head Status Alternate Status Drive Address IOWR# = 0 (IORD#=1) Data (Write) Feature Sector Count Sector Number (LBA 7-0) Cylinder Low (LBA 15-8) Cylinder High (LBA 23-16) Drive/Head Command Device Control Reserved T10-1.6 1211 10.1.2 ATA Flash Disk Controller Registers The following section describes the hardware registers used by the host software to issue commands to the ATA flash disk controller. These registers are often collectively referred to as the "Task File" registers. The registers are only selectable through CS3FX#, CS1FX#, and A2-A0 signals. Please see Table 10-1 for register addressing. 10.1.2.1 Data Register (Read/Write) (See Table 10-1 for register addressing) This 16-bit register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format-Track command. Data transfer can be performed in PIO mode. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 15 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.1.2.2 Error Register (Read Only) (See Table 10-1 for register addressing) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined as follows: D7 BBK D6 UNC D5 0 D4 IDNF D3 0 D2 ABRT D1 0 D0 AMNF Reset Value 0000 0000b Symbol BBK UNC IDNF ABRT Function This bit is set when a Bad Block is detected. This bit is set when an Uncorrectable Error is encountered. The requested sector ID is in error or cannot be found. This bit is set if the command has been aborted because of an ATA flash disk controller status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. This bit is set in case of a general error. AMNF 10.1.2.3 Feature Register (Write Only) (See Table 10-1 for register addressing) This register provides information regarding features of the ATA flash disk controller that the host can utilize. 10.1.2.4 Sector Count Register (See Table 10-1 for register addressing) This register contains the numbers of sectors of data requested to be transferred on a Read or Write operation between the host and the ATA flash disk controller. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. 10.1.2.5 Sector Number (LBA 7-0) Register (See Table 10-1 for register addressing) This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any ATA flash disk controller data access for the subsequent command. 10.1.2.6 Cylinder Low (LBA 15-8) Register (See Table 10-1 for register addressing) This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of then Logical Block Address. 10.1.2.7 Cylinder High (LBA 23-16) Register (See Table 10-1 for register addressing) This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 16 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.1.2.8 Drive/Head (LBA 27-24) Register (See Table 10-1 for register addressing) The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined as follows: D7 1 D6 LBA D5 1 D4 D3 D2 D1 D0 Reset Value 1010 0000b DRV HS3 HS2 HS1 HS0 Symbol LBA Function LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows: LBA7-LBA0: Sector Number register D7-D0. LBA15-LBA8: Cylinder Low register D7-D0. LBA23-LBA16: Cylinder High register D7-D0. LBA27-LBA24: Drive/Head register bits HS3-HS0. DRV HS3 HS2 HS1 HS0 DRV is the drive number. When DRV=0 (Master), Master is selected. When DRV=1(Slave), Slave is selected. When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode. When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 17 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.1.2.9 Status & Alternate Status Registers (Read Only) (See Table 10-1 for register addressing) These registers return the ATA flash disk controller status when read by the host. Reading the Status register does clear a pending interrupt while reading the Alternate Status register does not. The meaning of the status bits are described as follows: D7 BUSY D6 RDY D5 DWF D4 D3 D2 D1 D0 Reset Value 1000 0000b DSC DRQ CORR 0 ERR Symbol BUSY Function The busy bit is set when the ATA flash disk controller has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. RDY indicates whether the device is capable of performing ATA flash disk controller operations. This bit is cleared at power up and remains cleared until the ATA flash disk controller is ready to accept a command. This bit, if set, indicates a write fault has occurred. This bit is set when the ATA flash disk controller is ready. The Data Request is set when the ATA flash disk controller requires that information be transferred either to or from the host through the Data register. This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector Read operation. This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands (such as Read-Sectors and Write-Sectors) that end with an error condition should have the address of the first sector in error in the command block registers. RDY DWF DSC DRQ CORR ERR 10.1.2.10 Device Control Register (Write Only) (See Table 10-1 for register addressing) This register is used to control the ATA flash disk controller interrupt request and to issue a software Reset. This register can be written to even if the device is BUSY. The bits are defined as follows: D7 X D6 X D5 X D4 D3 D2 D1 D0 Reset Value 0000 1010b X 1 SW Rst -IEn 0 Symbol SW Rst -IEn Function This bit is set to 1 in order to force the ATA flash disk controller to perform a software Reset operation. The chip remains in Reset until this bit is reset to `0.' 0: The Interrupt Enable bit enables interrupts 1: Interrupts from the ATA flash disk controller are disabled This bit is set to 1 at Power-On and Reset. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 18 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.1.2.11 Drive Address Register (Read Only) (See Table 10-1 for register addressing) This register contains the inverted drive select and head select addresses of the currently selected drive. The bits in this register are as follows: D7 X D6 D5 D4 D3 D2 D1 D0 Reset Value x111 1110b -WTG Function -HS3 -HS2 -HS1 -HS0 -DS1 -DS0 Symbol -WTG -HS3 -HS2 -HS1 -HS0 -DS1 -DS0 This bit is 0 when a Write operation is in progress, otherwise, it is 1. This bit is the negation of bit 3 in the Drive/Head register. This bit is the negation of bit 2 in the Drive/Head register. This bit is the negation of bit 1 in the Drive/Head register. This bit is the negation of bit 0 in the Drive/Head register. This bit is 0 when drive 1 is active and selected. This bit is 0 when drive 0 is active and selected. 10.1.2.12 Command Register (Write Only) (See Table 10-1 for register addressing) This register contains the command code being sent to the drive. Command execution begins immediately after this register is written. The executable commands, the command codes, and the necessary parameters for each command are listed in Table 10-2. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 19 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2 ATA Flash Disk Controller Command Description This section defines the software requirements and the format of the commands the host sends to the ATA flash disk controller. Commands are issued to the ATA flash disk controller by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command register. The manner in which a command is accepted varies. There are three classes (see Table 10-2) of command acceptance, all dependent on the host not issuing commands unless the ATA flash disk controller is not busy (BSY=0). 10.2.1 ATA Flash Disk Controller Command Set Table 10-2 summarizes the ATA flash disk controller command set with the paragraphs that follow describing the individual commands and the task file for each. TABLE 10-2: ATA FLASH DISK CONTROLLER COMMAND SET Class 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 2 3 1. 2. 3. 4. 5. 6. 7. 8. Command Check-Power-Mode Execute-Drive-Diagnostic Format-Track Identify-Drive Idle Idle-Immediate Initialize-Drive-Parameters Read-Buffer Read-Long-Sector Read-Multiple Read-Sector(s) Read-Verify-Sector(s) Recalibrate Seek Set-Features Set-Multiple-Mode Set-Sleep-Mode Set-WP_PD#-Mode Stand-By Stand-By-Immediate Write-Buffer Write-Long-Sector Write-Multiple Write-Sector(s) Write-Verify Code E5H or 98H 90H 50H ECH E3H or 97H E1H or 95H 91H E4H 22H or 23H C4H 20H or 21H 40H or 41H 1XH 7XH EFH C6H E6H or 99H 8BH E2H or 96H E0H or 94H E8H 32H or 33H C5H 30H or 31H 3CH FR1 Y Y - SC2 Y7 Y Y Y Y Y Y Y Y Y SN3 Y Y Y Y Y Y Y Y Y CY4 Y Y Y Y Y Y Y Y Y Y DH5 D8 D Y8 D D D Y D Y Y Y Y D Y D D D D D D D Y Y Y Y LBA6 Y Y Y Y Y Y Y Y Y Y T10-2.3 1211 FR - Features register SC - Sector Count register SN - Sector Number register CY - Cylinder registers DH - Drive/Head register LBA - Logical Block Address Mode Supported (see command descriptions for use) Y - The register contains a valid parameter for this command. For the Drive/Head register: Y means both the ATA flash disk controller and Head parameters are used; D means only the ATA flash disk controller parameter is valid and not the Head parameter. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 20 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.1 Check-Power-Mode - 98H or E5H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 98H or E5H This command checks the power mode. Because SST ATA flash disk controller can recover from sleep in 200 ns, Idle Mode is never enabled. ATA flash disk controller sets BSY, sets the Sector Count register to 00H, clears BSY and generates an interrupt. 10.2.1.2 Execute-Drive-Diagnostic - 90H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 90H X 3 2 1 0 This command performs the internal diagnostic tests implemented by the ATA flash disk controller. If the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master responding with status for both devices. The Diagnostic codes shown in Table 10-3 are returned in the Error register at the end of the command. TABLE 10-3: DIAGNOSTIC CODES Code 01H 02H 03H 04H 05H 8XH Error Type No Error Detected Formatter Device Error Sector Buffer Error ECC Circuitry Error Controlling Microprocessor Error Slave Error T10-3.1 1211 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 21 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.3 Format-Track - 50H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) Sector Count X 7 6 5 4 50H Head (LBA 27-24) 3 2 1 0 This command is accepted for host backward compatibility. The ATA flash disk controller expects a sector buffer of data from the host to follow the command with the same protocol as the Write-Sector(s) command although the information in the buffer is not used by the ATA flash disk controller. The use of this command is not recommended. 10.2.1.4 Identify-Drive - ECH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X X X Drive X X X X X 7 6 5 4 ECH X 3 2 1 0 The Identify-Drive command enables the host to receive parameter information from the ATA flash disk controller. This command has the same protocol as the Read-Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table 10-4. All reserved bits or words are zero. Table 10-4 gives the definition for each field in the Identify-Drive Information. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 22 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications TABLE 10-4: IDENTIFY-DRIVE INFORMATION Word Address 0 1 2 3 4 5 6 7-8 9 10-14 15-19 20 21 22 23-26 27-46 47 48 49 50 51 52 53 54 55 56 57-58 59 60-61 62-63 64 65-66 67 68 69-127 128-159 160-255 1. 2. 3. 4. 5. 6. Default Value 044AH bbbb1 0000H bbbb1 0000H 0000H bbbb1 nnnnH2 nnnnH dddd3 eeee4 0002H nnnnH 0004H aaaa5 cccc6 000nH 0000H 0200H 0000H 0n00H 0000H 000nH nnnnH nnnnH nnnnH nnnnH 010nH nnnnH 0000H 00nnH 0000H nnnnH nnnnH 0000H 0000H 0000H Total Bytes 2 2 2 2 2 2 2 4 2 10 10 2 2 2 8 40 2 2 2 2 2 2 2 2 2 2 4 2 4 4 2 4 2 2 138 64 192 Data Field Type Information General configuration bit-significant information Default number of cylinders Reserved Default number of heads Reserved Reserved Default number of sectors per track Number of sectors per card (Word 7 = MSW, Word 8 = LSW) Vendor Unique SST preset, unique ID in ASCII User-programmable serial number in ASCII Buffer type Buffer size in 512 Byte increments # of ECC bytes passed on Read/Write-Long-Sector Commands Firmware revision in ASCII. Big Endian Byte Order in Word User Definable Model number Maximum number of sectors on Read/Write-Multiple command Reserved Capabilities Reserved PIO data transfer cycle timing mode Reserved (DMA data transfer is not supported in ATA flash disk controller) Translation parameters are valid Current numbers of cylinders Current numbers of heads Current sectors per track Current capacity in sectors (LBAs) (Word 57 = LSW, Word 58 = MSW) Multiple sector setting Total number of sectors addressable in LBA Mode Reserved (DMA data transfer is not supported in ATA flash disk controller) Advanced PIO Transfer Mode Supported Reserved Minimum PIO transfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control Reserved Vendor unique bytes Reserved T10-4.10 1211 bbbb - default value set by controller. The selections could be user programmable. n - calculated data based on product configuration dddd - unique number of each device eeee - the default value is 2020H aaaa - any unique SST firmware revision cccc - default value is "xxxMB ATA Flash Disk" where xxx is the flash drive capacity. The user has an option to change the model number during manufacturing. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 23 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.4.1 General Configuration This field informs the host that this is a non-magnetic, hard sectored, removable storage device with a transfer rate greater than 10 MByte/sec and is not MFM encoded. 10.2.1.4.2 Default Number of Cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders. 10.2.1.4.3 Default Number of Heads This field contains the number of translated heads in the default translation mode. 10.2.1.4.4 Default Number of Sectors per Track This field contains the number of sectors per track in the default translation mode. 10.2.1.4.5 Number of Sectors This field contains the number of sectors per ATA flash disk controller. This double word value is also the first invalid address in LBA translation mode. 10.2.1.4.6 Serial Number The contents of this field are right justified and padded with spaces (20H). The first ten bytes are a SST preset, unique ID. The second ten bytes are a user-programmable value with a default value of spaces. 10.2.1.4.7 Buffer Type This field defines the buffer capability: 0002H: a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the ATA flash disk controller. 10.2.1.4.8 Buffer Size This field defines the buffer capacity in 512 Byte increments. SST's ATA flash disk controller has up to 2 sector data buffer for host interface. 10.2.1.4.9 ECC Count This field defines the number of ECC bytes used on each sector in the Read- and Write-Long-Sector commands. 10.2.1.4.10 Firmware Revision This field contains the revision of the firmware for this product. 10.2.1.4.11 Model Number This field is reserved for the model number for this product. 10.2.1.4.12 Read-/Write-Multiple Sector Count This field contains the maximum number of sectors that can be read or written per interrupt using the Read-Multiple or Write-Multiple commands. 10.2.1.4.13 Capabilities Bit 13: Standby Timer Bit 11: IORDY Support Bit 9: LBA support Bit 8: DMA Support Set to 0, forces sleep mode when host is inactive. Set to 0, indicates that this device may support IORDY operation. Set to 1, SST's ATA flash disk controllers support LBA mode addressing. This bit is set to 0. DMA mode is not supported. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 24 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.4.14 PIO Data Transfer Cycle Timing Mode This field defines the mode for PIO data transfer. ATA flash disk controller supports up to PIO Mode-4. 10.2.1.4.15 Translation Parameters Valid If bit 0 is 1, it indicates that words 54 to 58 are valid and reflect the current number of cylinders, heads and sectors. If bit 1 is 1, it indicates that words 64 to 70 are valid to support PIO Mode-3 and 4. 10.2.1.4.16 Current Number of Cylinders, Heads, Sectors/Track These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode. 10.2.1.4.17 Current Capacity This field contains the product of the current cylinders times heads times sectors. 10.2.1.4.18 Multiple Sector Setting This field contains a validity flag in the Odd Byte and the current number of sectors that can be transferred per interrupt for R/W Multiple in the Even Byte. The Odd Byte is always 01H which indicates that the Even Byte is always valid. The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this word by default contains a 00H which indicates that R/W Multiple commands are not valid. 10.2.1.4.19 Total Sectors Addressable in LBA Mode This field contains the number of sectors addressable for the ATA flash disk controller in LBA mode only. 10.2.1.4.20 Advanced PIO Data Transfer Mode ATA flash disk controller supports up to PIO Mode-4. 10.2.1.4.21 Minimum PIO Transfer Cycle Time Without Flow Control The ATA flash disk controller's minimum cycle time is 120 ns. 10.2.1.4.22 Minimum PIO Transfer Cycle Time With IORDY The ATA flash disk controller's minimum cycle time is 120 ns, e.g., PIO Mode-4. 10.2.1.5 Idle - 97H or E3H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X Timer Count (5 msec increments) X 3 2 X 1 0 97H or E3H This command causes the ATA flash disk controller to set BSY, enter the Idle Mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic Power-Down mode is enabled. If the sector count is zero, the automatic Power-Down mode is also enabled, the timer count is set to 3, with each count being 5 ms. Note that this time base (5 msec) is different from the ATA specification. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 25 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.6 Idle-Immediate - 95H or E1H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 95H or E1H This command causes the ATA flash disk controller to set BSY, enter the Idle Mode, clear BSY and generate an interrupt. 10.2.1.7 Initialize-Drive-Parameters - 91H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 0 X Drive X X X Number of Sectors X 7 6 5 4 91H Max Head (no. of heads-1) 3 2 1 0 This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Drive/Head registers are used by this command. 10.2.1.8 Read-Buffer - E4H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E4H X 3 2 1 0 The Read-Buffer command enables the host to read the current contents of the ATA flash disk controller's sector buffer. This command has the same protocol as the Read-Sector(s) command (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 26 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.9 Read-Multiple - C4H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 C4H Head (LBA 27-24) 3 2 1 0 Note: The current revision of the SST ATA flash disk controller can support up to a block count of 1 as indicated in the Identify-Drive Command information. The Read-Multiple command is similar to the Read-Sector(s) command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. Command execution is identical to the Read-Sectors operation except that the number of sectors defined by a Set Multiple command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the SetMultiple-Mode command, which must be executed prior to the Read-Multiple command. When the Read-Multiple command is issued, the Sector Count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where n = remainder (sector count/block count). If the Read-Multiple command is attempted before the Set-Multiple-Mode command has been executed or when Read-Multiple commands are disabled, the Read-Multiple operation is rejected with an Aborted Command error. Disk errors encountered during Read-Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read-Sector(s) command. This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. At command completion, the Command Block registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 27 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.10 Read-Long-Sector - 22H or 23H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X 3 2 1 0 22H or 23H Head (LBA 27-24) The Read-Long-Sector command performs similarly to the Read-Sector(s) command except that it returns 516 Bytes of data instead of 512 Bytes. During a Read-Long-Sector command, the ATA flash disk controller does not check the ECC bytes to determine if there has been a data error. Only singlesector Read-Long-Sector operations are supported. The transfer consists of 512 Bytes of data transferred in Word-Mode followed by 4 Bytes of ECC data transferred in Byte-Mode. This command has the same protocol as the Read-Sector(s) command. Use of this command is not recommended. 10.2.1.11 Read-Sector(s) - 20H or 21H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 20H or 21H Head (LBA 27-24) This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. When this command is issued and after each sector of data (except the last one) has been read by the host, the ATA flash disk controller sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 Bytes of data from the buffer. At command completion, the Command Block registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 28 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.12 Read-Verify-Sector(s) - 40H or 41H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 40H or 41H Head (LBA 27-24) This command is identical to the Read-Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the ATA flash disk controller sets BSY. When the requested sectors have been verified, the ATA flash disk controller clears BSY and generates an interrupt. Upon command completion, the Command Block registers contain the cylinder, head, and sector number of the last sector verified. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count register contains the number of sectors not yet verified. 10.2.1.13 Recalibrate - 1XH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive X X X X X 7 6 5 4 1XH X 3 2 1 0 This command is effectively a NOP command to the ATA flash disk controller and is provided for compatibility purposes. 10.2.1.14 Seek - 7XH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) X X 7 6 5 4 7XH Head (LBA 27-24) 3 2 1 0 This command is effectively a NOP command to the ATA flash disk controller although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 29 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.15 Set-Features - EFH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X Feature 7 6 5 4 EFH X 3 2 1 0 This command is used by the host to establish or select certain features. Table 10-5 defines all features that are supported. TABLE 10-5: FEATURES SUPPORTED Feature 01H 03H 55H 66H 69H 81H 96H 97H 9AH BBH CCH Operation Enable 8-bit data transfers. Set transfer mode based on value in Sector Count register. Table 10-6 defines the values. Disable Read Look Ahead. Disable Power on Reset (POR) establishment of defaults at software Reset. NOP - Accepted for backward compatibility. Disable 8-bit data transfer. NOP - Accepted for backward compatibility. Accepted for backward compatibility. Use of this Feature is not recommended. NOP - accepted for compatibility. 4 Bytes of data apply on Read/Write-Long-Sector commands. Enable Power on Reset (POR) establishment of defaults at software Reset. T10-5.1 1211 Features 01H and 81H are used to enable and clear 8-bit data transfer mode. If the 01H feature command is issued all data transfers will occur on the low order D7-D0 data bus and the IOCS16# signal will not be asserted for data register accesses. Features 55H and BBH are the default features for the ATA flash disk controller; thus, the host does not have to issue this command with these features unless it is necessary for compatibility reasons. Features 66H and CCH can be used to enable and disable whether the Power On Reset (POR) Defaults will be set when a software Reset occurs. TABLE 10-6: TRANSFER MODE VALUES Mode PIO default mode PIO default mode, disable IORDY PIO flow control transfer mode Reserved 1. Mode = transfer mode number, all other values are not valid Bits [7:3] 00000b 00000b 00001b Other Bits [2:0] 000b 001b mode1 N/A T10-6.1 1211 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 30 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.16 Set-Multiple-Mode - C6H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X Sector Count X 7 6 5 4 C6H X 3 2 1 0 This command enables the ATA flash disk controller to perform Read and Write-Multiple operations and establishes the block count for these commands. The Sector Count register is loaded with the number of sectors per block. Upon receipt of the command, the ATA flash disk controller sets BSY to 1 and checks the Sector Count register. If the Sector Count register contains a valid value (see Section 10.2.1.4.12 for details) and the block count is supported, the value is loaded for all subsequent Read-Multiple and Write-Multiple commands and execution of those commands is enabled. If a block count is not supported, an Aborted Command error is posted, and Read-Multiple and Write-Multiple commands are disabled. If the Sector Count register contains 0 when the command is issued, Read and Write-Multiple commands are disabled. At power on, or after a hardware or (unless disabled by a Set Feature command) software reset, the default mode is Read and Write-Multiple disabled. 10.2.1.17 Set-Sleep-Mode - 99H or E6H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 99H or E6H This command causes the ATA flash disk controller to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted but not required). Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the timer is 15 milliseconds. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 31 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.18 Set-WP_PD#-Mode - 8BH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X X X Drive 6EH 44H 72H 50H 55H or AAH 7 6 5 4 8BH X 3 2 1 0 This command configures the WP_PD# pin for either the Write-Protect mode or the Power-Down mode. When the host sends this command to the device with the value AAH in the feature register, the WP_PD# pin is configured for the Write-Protect mode described in Section 7.1. The Write-Protect mode is the factory default setting. When the host sends this command to the device with the value 55H in the feature register, WP_PD# is configured for the Power-Down mode. All values in the C/D/H register, the Cylinder Low register, the Cylinder High register, the Sector Number register, the Sector Count register, and the Feature register need to match the values shown above, otherwise, the command will be treated as an invalid command. Once the mode is set with this command, the device will stay in the configured mode until the next time this command is issued. Power-off or reset will not change the configured mode. 10.2.1.19 Standby - 96H or E2H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 96H or E2H This command causes the ATA flash disk controller to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 32 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.20 Standby-Immediate - 94H or E0H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 Drive X X X X X 3 2 X 1 0 94H or E0H This command causes the ATA flash disk controller to set BSY, enter the Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another command (a reset is not required). 10.2.1.21 Write-Buffer - E8H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E8H X 3 2 1 0 The Write-Buffer command enables the host to overwrite contents of the ATA flash disk controller's sector buffer with any data pattern desired. This command has the same protocol as the WriteSector(s) command and transfers 512 Bytes. 10.2.1.22 Write-Long-Sector - 32H or 33H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) X X 3 2 1 0 32H or 33H Head (LBA 27-24) This command is similar to the Write-Sector(s) command except that it writes 516 Bytes instead of 512 Bytes. Only single sector Write-Long-Sector operations are supported. The transfer consists of 512 Bytes of data transferred in Word-Mode followed by 4 Bytes of ECC transferred in Byte-Mode. Because of the unique nature of the solid-state ATA flash disk controller, the 4 Bytes of ECC transferred by the host may be used by the ATA flash disk controller. The ATA flash disk controller may discard these 4 Bytes and write the sector with valid ECC data. This command has the same protocol as the WriteSector(s) command. Use of this command is not recommended. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 33 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.23 Write-Multiple - C5H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X LBA X Drive Cylinder High Cylinder Low Sector Number Sector Count X 7 6 5 4 C5H Head 3 2 1 0 Note: The current revision of the SST ATA flash disk controller can support up to a block count of 1 as indicated in the Identify-Drive Command information. This command is similar to the Write-Sectors command. The ATA flash disk controller sets BSY within 400 ns of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by Set Multiple. Command execution is identical to the Write-Sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the SetMultiple-Mode command, which must be executed prior to the Write-Multiple command. When the Write-Multiple command is issued, the Sector Count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where: n = remainder (sector count/block). If the Write-Multiple command is attempted before the Set-Multiple-Mode command has been executed or when Write-Multiple commands are disabled, the Write-Multiple operation will be rejected with an aborted command error. Errors encountered during Write-Multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred and the Sector Count register contains the residual number of sectors that need to be transferred for successful completion of the command e.g. each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The Sector Count register contains 6 and the address is that of the third sector. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 34 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.1.24 Write-Sector(s) - 30H or 31H Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 7 6 5 4 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 3 2 1 0 30H or 31H Head (LBA 27-24) This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. When this command is accepted, the ATA flash disk controller sets BSY, then sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. 10.2.1.25 Write-Verify - 3CH Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X 7 6 5 4 3CH Head (LBA 27-24) 3 2 1 0 This command is similar to the Write-Sector(s) command, except each sector is verified immediately after being written. This command has the same protocol as the Write-Sector(s) command. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 35 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 10.2.2 Error Posting The following table summarizes the valid status and error value for all the ATA flash disk controller Command set. TABLE 10-7: ERROR Command Check-Power-Mode Execute-Drive-Diagnostic1 Format-Track Identify-Drive Idle Idle-Immediate Initialize-Drive-Parameters Read-Buffer Read-Multiple Read-Long-Sector Read-Sector(s) Read-Verify-Sector(s) Recalibrate Seek Set-Features Set-Multiple-Mode Set-Sleep-Mode Set-WP_PD#-Mode Standby Standby-Immediate Write-Buffer Write-Long-Sector Write-Multiple Write-Sector(s) Write-Verify Invalid-Command-Code 1. See Table 10-3 V = valid on this command AND STATUS REGISTER Error Register BBK UNC IDNF ABRT V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V AMNF RDY V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Status Register DWF DSC V V V V V V V V V V V V V V V V V V V V V V V V V V V V V CORR ERR V V V V V V V V V V V V V V V V V V V V V V V V V V T10-7.4 1211 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 36 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 11.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D.C. Voltage on any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. TABLE 11-1: ABSOLUTE MAXIMUM POWER PIN STRESS RATINGS Parameter Input Power Voltage on any flash media interface pin with respect to VSS Voltage on all other pins with respect to VSS Symbol VDDQ VDD Conditions -0.3V min to 6.5V max -0.3V min to 4.0V max -0.5V min to VDD + 0.5V max -0.5V min to VDDQ + 0.5V max T11-1.3 1211 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C OF VDD 3.135-3.465V 3.135-3.465V VDDQ 4.5-5.5V; 3.135-3.465V 4.75-5.25V; 3.135-3.465V AC CONDITIONS TEST Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figure 11-1 Note: All AC specifications are guaranteed by design. TABLE 11-2: RECOMMENDED SYSTEM POWER-UP TIMING Symbol TPU-INITIAL TPU-READY1 TPU-WRITE1 Parameter First-time Power-up/Reset to Ready Host Power-up/Reset to Ready Operation Host Power-up/Reset to Write Operation Typical 0.5 200 200 Maximum 1.5 500 500 Units sec/MB ms ms T11-2.5 1211 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 37 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications TABLE 11-3: CAPACITANCE Parameter CI/O1 CIN 1 (Ta = 25C, f=1 Mhz, other pins open) Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 15 9 Units pF pF T11-3.1 1211 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11-4: RELIABILITY CHARACTERISTICS Symbol ILTH 1 Parameter Latch Up Minimum Specification 100 + IDD Units mA Test Method JEDEC Standard 78 T11-4.1 1211 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 11.1 DC Characteristics In the table below, x refers to the characteristics described in Section 11.1.1. For example, I1U indicates a pull up resistor with a type 1 input characteristic. TABLE 11-5: INPUT CHARACTERISTICS, Type IxZ I5U I1U-I4U I2D Parameter Input Leakage Current Pull Up Resistor Pull Up Resistor Pull Down Resistor IL RPU2 RPU1 RPD1 VDD = VDDQ = 3.135-3.465V Symbol Conditions VIH = VDDQ Max; VIL = VSS VDD = VDDQ = VDD Max VDDQ = VDDQ Min; VDD = VDD Min VDDQ = VDDQ Min; VDD = VDD Min VDDQ = VDDQ Min; VDD = VDD Min Min -10 50 50 50 Max 10 500 1500 1500 Units A KOhm KOhm KOhm T11-5.7 1211 TABLE 11-6: INPUT CHARACTERISTICS, Type I1U-I4U I2D Parameter Pull Up Resistor Pull Down Resistor VDDQ = 4.5-5.5V, VDD = 3.135-3.465V Symbol RPU1 RPD1 Conditions VDDQ = VDDQ Min; VDD = VDD Min VDDQ = VDDQ Min; VDD = VDD Min Min 50 50 Max 700 700 Units KOhm KOhm T11-6.9 1211 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 38 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 11.1.1 Input Characteristics TABLE 11-7: INPUT VOLTAGE CHARACTERISTICS (Ta = 0C to +70C), VDD = VDDQ = 3.135-3.465V Type1 I1 I2 I3 I4 I5 I6 Parameter Input Voltage CMOS Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Input Voltage CMOS Schmitt Trigger Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Symbol VIH VIL VIH VIL VT+ VTVT+ VTVIH VIL VT+ VT1. I1-I4 are for host side interface only. I5-I6 are for flash media interface only. Min VDDQ-1.3 Max VDDQ-2.5 Units Volts Volts Conditions VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Min T11-7.2 1211 VDDQ-1.3 VDDQ-2.5 VDDQ-1.3 VDDQ-2.7 VDDQ-1.3 VDDQ-2.5 VDD-1.2 VDD-2.5 VDD-0.6 VDD-2.55 Volts Volts Volts Volts TABLE 11-8: INPUT VOLTAGE CHARACTERISTICS (Ta = 0C to +70C), VDDQ = 4.5-5.5V, VDD = 3.135-3.465V Type1 I1 I2 I3 I4 I5 I6 Parameter Input Voltage CMOS Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Input Voltage CMOS Schmitt Trigger Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Symbol VIH VIL VIH VIL VT+ VTVT+ VTVIH VIL VT+ VT1. I1-I4 are for host side interface only. I5-I6 are for flash media interface only. Min VDDQ-2.7 Max VDDQ-4.2 Units Volts Volts Conditions VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Min T11-8.2 1211 VDDQ-2.3 VDDQ-4.2 VDDQ-2.7 VDDQ-4.2 VDDQ-2.7 VDDQ-4.2 VDD-1.2 VDD-2.5 VDD-0.6 VDD-2.55 Volts Volts Volts Volts (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 39 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications TABLE 11-9: INPUT VOLTAGE CHARACTERISTICS (Ta = -40C to +85C), VDD = VDDQ = 3.135-3.465V Type1 I1 I2 I3 I4 I5 I6 Parameter Input Voltage CMOS Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Input Voltage CMOS Schmitt Trigger Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Symbol VIH VIL VIH VIL VT+ VTVT+ VTVIH VIL VT+ VT1. I1-I4 are for host side interface only. I5-I6 are for flash media interface only. Min VDDQ-1.3 Max VDDQ-2.5 Units Volts Volts Conditions VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Min T11-9.4 1211 VDDQ-1.3 VDDQ-2.5 VDDQ-1.3 VDDQ-2.7 VDDQ-1.3 VDDQ-2.5 VDD-1.2 VDD-2.5 VDD-0.6 VDD-2.55 Volts Volts Volts Volts TABLE 11-10: INPUT VOLTAGE CHARACTERISTICS (Ta = -40C to +85C), VDDQ = 4.5-5.5V, VDD = 3.135-3.465V Type1 I1 I2 I3 I4 I5 I6 Parameter Input Voltage CMOS Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Input Voltage CMOS Schmitt Trigger Input Voltage CMOS Input Voltage CMOS Schmitt Trigger Symbol VIH VIL VIH VIL VT+ VTVT+ VTVIH VIL VT+ VT1. I1-I4 are for host side interface only. I5-I6 are for flash media interface only. Min VDDQ-2.7 Max VDDQ-4.2 Units Volts Volts Conditions VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDDQ=VDDQ Max VDDQ=VDDQ Min VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Min T11-10.4 1211 VDDQ-2.3 VDDQ-4.2 VDDQ-2.7 VDDQ-4.2 VDDQ-2.7 VDDQ-4.2 VDD-1.2 VDD-2.5 VDD-0.6 VDD-2.55 Volts Volts Volts Volts (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 40 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 11.1.2 Output Characteristics TABLE 11-11: OUTPUT VOLTAGE CHARACTERISTICS (Ta = 0C to +70C), VDD = VDDQ = 3.135-3.465V Type1 O1 O2 O3 O4 Parameter Output Voltage Output Voltage Output Voltage Output Voltage Symbol VOH VOL VOH VOL VOH VOL VOH VOL VDDQ-1.0 VDDQ-2.9 VDD-0.9 VDD-3.0 Volts VDDQ-1.0 VDDQ-2.9 Volts Min VDD-0.9 VDD-3.0 Volts Max Units Volts Conditions IOH=-1.3 mA, VDD=VDDQ=VDDQ Min IOL=1.3 mA, VDD=VDDQ=VDDQ Min IOH=-2.5 mA, VDD=VDDQ=VDDQ Min IOL=2.5 mA, VDD=VDDQ=VDDQ Min IOH=-4 mA, VDD=VDDQ=VDDQ Min IOL=4 mA, VDD=VDDQ=VDDQ Min IOH=-5 mA, VDD=VDDQ=VDDQ Min IOL=5 mA, VDD=VDDQ=VDDQ Min T11-11.4 1211 1. O2 and O4 are for host side interface only. O1 and O3 are for flash media interface only. TABLE 11-12: OUTPUT VOLTAGE CHARACTERISTICS (Ta = 0C to +70C), VDDQ = 4.5-5.5V, VDD = 3.135-3.465V Type1 O1 O2 O3 O4 Parameter Output Voltage Output Voltage Output Voltage Output Voltage Symbol VOH VOL VOH VOL VOH VOL VOH VOL VDDQ-1.3 VDDQ-4.6 VDD-0.9 VDD-3.0 Volts VDDQ-1.3 VDDQ-4.6 Volts Min VDD-0.9 VDD-3.0 Volts Max Units Volts Conditions IOH=-1.3 mA, VDD=VDD Min, VDDQ=VDDQ Min IOL=1.3 mA, VDD=VDD Min, VDDQ=VDDQ Min IOH=-4 mA, VDD=VDD Min; VDDQ=VDDQ Min IOL=4 mA, VDD=VDD Min, VDDQ=VDDQ Min IOH=-4 mA, VDD=VDD Min, VDDQ=VDDQ Min IOL=4 mA, VDD=VDD Min, VDDQ=VDDQ Min IOH=-8 mA, VDD=VDD Min; VDDQ=VDDQ Min IOL=8 mA, VDD=VDD Min, VDDQ=VDDQ Min T11-12.2 1211 1. O2 and O4 are for host side interface only. O1 and O3 are for flash media interface only. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 41 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications TABLE 11-13: OUTPUT VOLTAGE CHARACTERISTICS (Ta = -40C to +85C), VDD = VDDQ = 3.135-3.465V Type1 O1 O2 O3 O4 Parameter Output Voltage Output Voltage Output Voltage Output Voltage Symbol VOH VOL VOH VOL VOH VOL VOH VOL VDDQ-1.0 VDDQ-2.9 VDD-0.9 VDD-3.0 Volts VDDQ-1.0 VDDQ-2.9 Volts Min VDD-0.9 VDD-3.0 Volts Max Units Volts Conditions IOH=-1.3 mA, VDD=VDDQ=VDDQ Min IOL=1.3 mA, VDD=VDDQ=VDDQ Min IOH=-2 mA, VDD=VDDQ=VDDQ Min IOL=2 mA, VDD=VDDQ=VDDQ Min IOH=-4 mA, VDD=VDDQ=VDDQ Min IOL=4 mA, VDD=VDDQ=VDDQ Min IOH=-4 mA, VDD=VDDQ=VDDQ Min IOL=4 mA, VDD=VDDQ=VDDQ Min T11-13.9 1211 1. O2 and O4 are for host side interface only. O1 and O3 are for flash media interface only. TABLE 11-14: OUTPUT VOLTAGE CHARACTERISTICS (Ta = -40C to +85C), VDDQ = 4.5-5.5V, VDD = 3.135-3.465V Type1 O1 O2 O3 O4 Parameter Output Voltage Output Voltage Output Voltage Output Voltage Symbol VOH VOL VOH VOL VOH VOL VOH VOL VDDQ-1.3 VDDQ-4.6 VDD-0.9 VDD-3.0 Volts VDDQ-1.3 VDDQ-4.6 Volts Min VDD-0.9 VDD-3.0 Volts Max Units Volts Conditions IOH=-1.3 mA, VDD=VDD Min, VDDQ=VDDQ Min IOL=1.3 mA, VDD=VDD Min, VDDQ=VDDQ Min IOH=-3 mA, VDD=VDD Min; VDDQ=VDDQ Min IOL=3 mA, VDD=VDD Min, VDDQ=VDDQ Min IOH=-4 mA, VDD=VDD Min, VDDQ=VDDQ Min IOL=4 mA, VDD=VDD Min, VDDQ=VDDQ Min IOH=-6 mA, VDD=VDD Min; VDDQ=VDDQ Min IOL=6 mA, VDD=VDD Min, VDDQ=VDDQ Min T11-14.7 1211 1. O2 and O4 are for host side interface only. O1 and O3 are for flash media interface only. TABLE 11-15: DC CHARACTERISTICS, VDDQ = 4.5-5.5V, VDD = 3.135-3.465V Symbol IDDactive1,2 ISP ISP Parameter Power supply current (Ta = -40C to +85C) Sleep/Standby/Idle current (Ta = 0C to +70C) Sleep/Standby/Idle current (Ta = -40C to +85C) Typ 35 50 75 Max 50 75 200 Units mA A A Conditions VDD=VDD Max; VDDQ=VDDQ Max VDD=VDD Max; VDDQ=VDDQ Max VDD=VDD Max; VDDQ=VDDQ Max T11-15.7 1211 1. Sequential data transfer for 1 sector read data from Host interface and write data to media. 2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 42 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 11.2 AC Characteristics VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 540 ILL F2-3.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <10 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 11-1: AC INPUT/OUTPUT REFERENCE WAVEFORMS 11.2.1 Host Side Interface I/O Input (Read) Timing Specification TABLE 11-16: HOST SIDE INTERFACE I/O READ TIMING Item Data Setup before IORD# Data Hold following IORD# IORD# Width Time Address Setup before IORD# Address Hold following IORD# IOCS16# Delay Falling from Address IOCS16# Delay Rising from Address Symbol tsu(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tdfIOCS16(ADR) tdrIOCS16(ADR) Min 20 5 70 25 10 Max 20 20 Units ns ns ns ns ns ns ns T11-16.6 1211 Note: The maximum load on IOCS16# is 1 LSTTL with 50pF total load. All AC specifications are guaranteed by design. Valid Address1 tsuA(IORD) tw(IORD) IORD# tsu (IORD) IOCS16# tdfIOCS16(ADR) th(IORD) DOUT 540 ILL F2-1.5 thA(IORD) tdrIOCS16(ADR) D15-D0 1. Valid Address consists of signals CS1FX#, CS3FX# and A2-A0. FIGURE 11-2: HOST SIDE INTERFACE I/O READ TIMING DIAGRAM (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 43 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 11.2.2 Host Side Interface I/O Output (Write) Timing Specification TABLE 11-17: HOST SIDE INTERFACE I/O WRITE TIMING SPECIFICATION Item Data Setup before IOWR# Data Hold following IOWR# IOWR# Width Time Address Setup before IOWR# Address Hold following IOWR# IOCS16# Delay Falling from Address IOCS16# Delay Rising from Address Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tdfIOCS16(ADR) tdrIOCS16(ADR) Min 20 10 70 25 10 Max 20 20 Units ns ns ns ns ns ns ns T11-17.5 1211 Note: The maximum load on IOCS16# is 1 LSTTL with 50pF total load. All AC specifications are guaranteed by design. Valid Address1 tsuA(IOWR) tw(IOWR) IOWR# tdrIOCS16(ADR) thA(IOWR) IOCS16# tdfIOCS16(ADR) tsu(IOWR) DIN Valid 540 ILL F2-2.5 th(IOWR) D15-D0 1. Valid Address consists of signals CS1FX#, CS3FX# and A2-A0. FIGURE 11-3: HOST SIDE INTERFACE I/O WRITE TIMING DIAGRAM (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 44 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 11.2.3 Media Side Interface I/O Timing Specifications TABLE 11-18: SST55LD017A/B/C TIMING PARAMETERS Item FCLE Setup Time FCLE Hold Time FCE# Setup Time FCE# Hold Time for Command/Data Write Cycle FCE# Hold Time for Sequential Read Last Cycle FWE# Pulse Width FWE# High Hold Time Write Cycle Time FALE Setup Time FALE Hold Time FAD[7:0] Setup Time FAD[7:0] Hold Time FRE# Pulse Width Ready to FRE# Low FRE# Data Setup Access Time Read Cycle Time FRE# High Hold Time FRE# High to Data Hi-Z Note: All AC specifications are guaranteed by design. Symbol TCLS TCLH TCS TCH TCHR TWP TWH TWC TALS TALH TDS TDH TRP TRR TREA TRC TREH TRHZ Min 30 30 30 30 30 30 60 30 30 25 25 30 30 20 60 30 5 Max 30 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns T11-18.9 1211 (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 45 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications TCLS FCLE TCS FCE# TWP FWE# TALS TALH FALE TDS FAD[7:0] TDH TCH TCLH Command 540 ILL F05.1 FIGURE 11-4: MEDIA COMMAND LATCH CYCLE FCLE FCE# XXXXXX XXXX TCS TWC TWC FWE# TALS FALE TWP TWH TWP TWH TWP TALH TDS FAD[7:0] TDH TDS A9-A16 TDH TDS A17-A23 TDH XXXXXXXXXXXX A0-A7 XXX XXX XXXXXX 540 ILL F06.0 FIGURE 11-5: MEDIA ADDRESS LATCH CYCLE (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 46 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications FCLE TCH FCE# TWC FALE XXXX TWP TWH TDS TDH TDS DIN 1 TDH TDS DIN 511 TDH TWP TWP FWE# FAD[7:0] XXXXXXXXXXXX DIN 0 XXX XXX XXXXXXXXX 540 ILL F07.0 FIGURE 11-6: MEDIA DATA LOADING LATCH CYCLE TRC FCE# TREA FRE# TREA TRP TRHZ DOUT TCHR TREA TREH TRHZ DOUT FAD[7:0] TRR FRBYbsy# DOUT 540 ILL F08.4 FIGURE 11-7: MEDIA DATA READ CYCLE (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 47 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 12.0 APPENDIX 12.1 Differences between SST ATA Flash Disk Controller and ATA/ATAPI-5 Specifications 12.1.1 Idle Timer The Idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value specified in ATA specifications. 12.1.2 Recovery from Sleep Mode For ATA flash disk controller devices, recovery from sleep mode is accomplished by simply issuing another command to the device. A hardware or software reset is not required. (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 48 Preliminary Specifications VDDq (5.0V or 3.3V) VDDq + C1 10uF C4 0.1uF HOST INTERFACE 0.1uF C5 C6 0.1uF C2 2.2uF C7 0.1uF + VDD VDD (3.3V) VDD R1 390 FCE4# CSEL WP_PD# DASP# INTRQ CS1FX# CS3FX# VDDq FCE3# D[15:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VDDq FCE2# IORD# IOWR# D14 D6 D13 D5 D12 D4 D11 D3 U1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 D15 D7 D0 D8 D1 D9 D2 D10 TIE_DN TIE_DN VDDq (IO) TIE_DN TIE_DN RESET# TIE_DN A2 A1 A0 TIE_UP DNU VSS (IO) PDIAG# IOCS16# VDDq (IO) D15 D7 D0 D8 VSS (IO) D1 D9 D2 D10 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 IORD# IOWR# RESET# RESET# A2 A1 A0 A2 A1 A0 CSEL WP_PD# DASP# INTRQ CS1FX# CS3FX# U6 CE# NAND R/B# FLASH U5 CE# NAND FLASH R/B# U4 U3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 FCE1# CE# NAND R/B# FLASH TIE_UP TIE_DN IOWR# VSS (CORE) TIE_DN IORD# TIE_DN TIE_DN CS3FX# CS1FX# INTRQ VSS (IO) DASP# WP_PD# CSEL VDDq (IO) D14 D6 D13 D5 VSS (IO) D12 D4 D11 D3 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C PDIAG# IOCS16# POR# PDIAG# IOCS16# POR# 55LD017A/B/C ATA CONTROLLER VDD FAD2 FAD1 FAD0 FALE FCLE FWE# FRE# SCIDout SCIDin SCICLK DNU VSS (IO) DNU DNU DNU DNU DNU DNU DNU DNU VDD (IO) DNU DNU DNU DNU VSS (IO) INTClkEn# DNU DNU VDD (CORE) POR# FWP# I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 NAND FLASH 12.2 Reference Design Schematics ALE CLE WE# RE# WP_PD# SE# VDD VCC C3 VSS 0.1uF VDD FWP# R2 0 FIGURE 12-1: SCHEMATIC R6 1 2 3 4 5 SCI HEADER SCIDout SCIDin# SCIClk SCIEN# R3 R4 0 0 EXTClkOut EXTClkIn FOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FR/B# ATA FLASH MODULE, Optional circuit for external clock. Remove R2, R6 and stuff R3, R4 if this circuit is used. SCIEN# FCE4# FCE3# FCE2# FCE1# FCE0# VSS (IO) FAD7 FAD6 FAD5 FAD4 FAD3 VDD (IO) EXTClkOut EXTClkIn VSS (IO) FAD2 FAD1 FAD0 FALE FCLE FWE# FRE# FRDYbsy# VSS (CORE) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 U2 FCE0# FAD7 FAD6 FAD5 FAD4 FAD3 CE# R/B# UP TO 640 MBYTE CE# NAND R/B# FLASH S71211-01-000 7/02 R5 487 C8 10pF 540 ILL F09.1 07- 3- 02 (c)2002 Silicon Storage Technology, Inc. 49 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 12.3 Bill of Materials TABLE 12-1: SAMPLE BILL Item U1 C1 C2 R1 Specification SST55LD017A/B/C ATA flash disk controller 10 F 2.2 F 390 T12-1.3 1211 OF MATERIALS U2 to U6 NAND Flash Media Chip C3 to C7 0.1 F TABLE 12-2: OPTIONAL COMPONENTS Item R5 R6 C8 Specification 487 0 10 pF T12-2.0 1211 R2 to R4 0 TABLE 12-3: SUPPORTED NAND FLASH MEDIA NAND Flash Media Density 32MB 64MB Manufacturer Samsung Samsung Samsung Samsung Toshiba Part Number KM29W32000T K9F3208W0A KM29U64000T K9F6408U0B TC58V64FT KM29U128T K9F2808U0B TC58128FT KM29U256T K9F5608U0A TC58256FT K9F1208U0M TC58512FT K9K1G08U0M TH58100FT T12-3.4 1211 128MB Samsung Samsung Toshiba 256MB Samsung Samsung Toshiba 512MB 1GB Samsung Toshiba Samsung Toshiba (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 50 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 13.0 PHYSICAL DIMENSIONS TOP VIEW Pin #1 Identifier 0.17 0.27 14.00 BSC 16.00 BSC 0.50 BSC DETAIL .95 1.05 1.10 0.10 14.00 BSC .05 .15 16.00 BSC .09 .20 .45 .75 0- 7 1.00 nominal NOTE: 1. Complies with JEDEC publication 95 MS-026 variant AED dimensions although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is 0.25 mm. 100-tqfp-TQW-ILL-0 100-LEAD THIN QUAD FLAT PACK (TQFP) SST PACKAGE CODE: TQW (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 51 ATA Flash Disk Controller SST55LD017A / SST55LD017B / SST55LD017C Preliminary Specifications 14.0 PRODUCT ORDERING INFORMATION SST 55 XX LD 017 A 40 XXX -C X TQW XXX Package Modifier W = 100 leads Package Type TQ = TQFP Operation Temperature C = Commercial: 0C to +70C I = Industrial: -40C to +85C Frequency 40 = 40 MHz Version Device Number 017 Voltage L = 3.3V Device Family XX XXXX X 14.1 Valid Combinations SST55LD017A-40-C-TQW SST55LD017A-40-I-TQW SST55LD017B-40-C-TQW SST55LD017B-40-I-TQW SST55LD017C-40-C-TQW SST55LD017C-40-I-TQW Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2002 Silicon Storage Technology, Inc. S71211-01-000 7/02 52 |
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