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HD66206
(80-Channel Column/Common Driver for Middle- or Large-sized Liquid Crystal Panel)
Rev 0.2 February 1996 Description
The HD66206 is an 80-channel LCD driver, which is used for liquid crystal dot matrix display. This product can drive various types of liquid crystal displays, from small-sized to monochrome VGA-sized displays. Since this product can function as a column and a common driver, an LCD panel can be configured only with this product.
Features
* * * * * Logic power supply voltage: 2.7 to 5.5V Display duty: 1/16 (1/5 bias) to 1/240 80 liquid crystal display drive circuits Liquid crystal display drive voltage: 6 to 28V Data transfer speed 8 MHz max (at 5-V operation) 6.5 MHz max (at 3-V operation) Chip enable signal automatic generation Standby function Controllers that can be used with HD64645/HD64646 (LCTC series) HD66841 (LVIC series) Packages TFP-100B No package (bare chip) CMOS process
* * *
*
*
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HD66206
Ordering information
Type name HD66206TE HCD66206 Package TFP-100B Bare chip
147
HD66206
Pin Arrangement
Y52 Y51 Y50 Y49 Y48 Y47 Y46 Y45 Y44 Y43 Y42 Y41 Y40 Y39 Y38 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77
HD66206TE (TFP-100B) (Top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3
148
Y78 Y79 Y80 E V1 V2 V3 V4 VEE M CL1 GND SHL VCC FCS TEST DISPOFF D3 D2 D1R D0L CL2 CAR Y1 Y2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 1 Pin Arrangement (HD66206TE)
HD66206
Block Diagram
Y80Y79Y78Y77Y76 V1 M V2 V3 Y1
V4
Liquid crystal display drive circuit
CL1
80-bit latch circuit
D0L D1R D2 D3
Data conversion circuit
80-bit bi-directional shift register (also used as a latch circuit)
Selector FCS E TEST CL2 SHL Test input Operating mode switchin circuit
Counter
CAR
Figure 2 Block Diagram
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HD66206
Block Functions
Liquid crystal display drive circuit Generates one of four levels V1 to V4 to the output pin to drive the liquid crystal display according to the combination of data of the 80-bit latch circuit and the M signal. 80-bit latch circuit Latches data of the 80-bit bi-directional shift register (also used as a latch circuit) at the falling edge of CL1, and transmits it to the liquid crystal display drive circuit. 80-bit bi-directional shift register (also used as a latch circuit) When FCS is low, this register functions as an 80-bit shift register. At this time, D0L and D1R are used as data input/output pins. When FCS is high, this register functions as a 20 x 4-bit unit latch circuit. At this time, data that is input in parallel to data input pin D0L, D1R, D2 and D3 is converted to 4-bit data, and then is latched to this register according to the latch signal generated by the selector. Data conversion circuit When FCS is low, D0L and D1R are used as data input/output pins. When FCS is high, D0L, D1R, D2, and D3 are input data. Selector Decodes output data from the counter and generates a latch signal. Functions when latching data at serial-latch operation (when FCS is high). At this time, after 80 bits of data Y1 to Y80 are completely latched, the operation of the selector terminates. Even if input data changes, data in the latch circuit is maintained. Operating mode switching circuit Switches common driver operation (when FCS is low) and column driver operation (when FCS is high).
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HD66206
Pin Function
Table 1 Pin Functions
Symbol VCC GND VEE V1 V2 V3 V4 Control signal CL1 Input/ Pin No. Pin Name Output Function 39 37 34 30 31 32 33 36 VCC GND VEE V1 V2 V3 V4 Clock 1 -- VCC-GND: Logic power supply VCC-VEE: Power supply for driving the liquid crystal display. Input Power supply voltage for liquid crystal display drive level. See Figure 3. Column driver data latch signal. Data is latched at the falling edge of this signal. Set this signal low in common driver operation. In column driver operation, used as a display data latch signal. In common driver operation, used as a line selection data shift signal. In both operations, this signal is valid at its falling edge. AC conversion signal for liquid crystal display drive output. Control signal for inverting data output destination. 1. In column driver operation See Figure 4. 2. In common driver operation SR1, SR2, SR3, ...., SR80 correspond to Y1, Y2, Y3, ...., Y80 outputs. When SHL is low, data is input to D0L pin and output from D1R pin. D2 and D3 are set low. When SHL is high, the relationships between D0L and D1R are reverse. See Table 2.
Classification Power supply
Input
CL2
47
Clock 2
Input
M SHL
35 38
M Shift left
Input Input
(
29
Enable
Input
When FCS is high, data latch starts by setting the ( signal low. When FCS is low, set the ( signal high. The relationships between the ( signal, the FCS signal, data latch operation, and driver function are as show in Table 3
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HD66206
Table 1 Pin Function (cont)
Pin No. 48 Pin Name Carry Input/ Output Function Output When FCS is high, a chip enable signal is transferred to the next IC from this pin. Connect this pin to ( of the next IC. When FCS is low, open this pin. When this signal is low, liquid crystal display drive output is set at V1 level and liquid crystal display is turned off. At this time, internal display data is not affected. When this signal is high, the operation returns to the normal status. In column driver operation, input display data to D0L, D1R, D2, and D3 pins. In common driver operation, when SHL is high, D0L and D1R pins are display data output and input pins, respectively, and vice versa when SHL is low. At this time, set D2 and D3 low. When display data is high, liquid crystal display drive output is selection level and the display is on, and when display data is low, they are non-selection level and off, respectively. Control signal to select each operating mode. When the FCS pin is high, the operating mode is column driver, and when it is low, the operation mode is common driver. Test pin. Set this pin low. Liquid crystal display drive output. One of four levels V1 to V4 is output according to the combination of the M signal and display data. See Figures 5 and 6.
Classification Symbol Control signal
&$5
',632))
42
Display off Input
D0L D1L
46 45
Data0 (L) Data1 (R)
Input/ output
D2 D3
44 43
Data2 Data3
Input
FCS
40
Function select
Input
TEST Liquid crystal display drive output Y1 to Y80
41 49 to 100 1 to 28
TEST Y1 to Y80
Input Output
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HD66206
V1 V3 V4 V2
V1 and V2: Selection level V3 and V4: Non-selection level
Figure 3 Liquid Crystal Display Drive Level
SHL Input data and latch address
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80
Last
2nd
High
D0L D1R D2 D3
D0L D1R D2 D3 D0L D1R D2 D3
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
2nd
Low
D0L D1R D2 D3
D3 D2 D1R D0L D3 D2 D1R D0L
Figure 4 Column Driver Operating Mode
Table 2
SHL Low High
Common Driver Operation
Shift Register Shift Direction D0L D1R SR 1 SR 80 SR .......... SR D1R 2 80 SR .......... SR 79 1 D0L Common Signal Scan Direction Y1 Y80 Y80 Y1
Table 3
FCS High
Relationship between FCS, , Data Latch Operation, and Driver Function
Low High
Data Latch Operation Enabled Disabled --
Driver Function Column driver
Low
High
Common driver
Last
1st
D3 D2 D1R D0L D3 D2 D1R D0L
Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80
1st
D0L D1R D2 D3 D0L D1R D2 D3
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HD66206
Output level to be selected 0 1 1 0 1 0
M Data
Output level
V1 V3 V2 V4
Figure 5 Liquid Crystal Display Drive Output in Column Driver Operation
Output level to be selected 0 1 1 0 1 0
M Data
Output level
V2 V3 V1 V4
Figure 6 Liquid Crystal Display Drive Output in Common Driver Operation
154
VCC
GND VCC VEE E D1R SHL
com1 com2 com3 80
Application Examples
Y80, Y79, ... Y2, Y1
LCD panel
D3 D2 CL1 CAR D0L
DISPOFF V1 HD66206 V4 V3 (1) V2 CL2 M FCS TEST
640 x 240 1/240 duty
Open
VCC
Controller
GND VCC VEE E D1R SHL Y80, Y79, ..., Y2, Y1 80 seg1 seg2 seg3 com239 com240
FLM CL1 M DISPOFF D0L, D1R, D2, D3 CL2
GND(0V)
Open Open
DISPOFF V1 HD66206 V4 V3 (3) V2 CL2 M FCS TEST D3 D2 CL1 CAR D0L
VCC(+3V)
VCC SHL SHL Y80, Y79, ..., Y2, Y1 80 VCC 80
VCC SHL
80 Y80, Y79, ..., Y2, Y1
Open
Y80, Y79, ..., Y2, Y1
R1
- + E CAR GND VCC VEE E V1 V3 V4 V2 CL1 CL2 M D0L, D1R, D2, D3 DISPOFF FCS TEST GND VCC VEE - + - + - +
HD66206 (1)
HD66206 (2)
CAR
E GND VCC VEE
HD66206 (8)
V1 V3 V4 V2 CL1 CL2 M D0L, D1R, D2, D3 DISPOFF FCS TEST
R2 R1 R1
Figure 7 shows an example when configuring the 640 x 240-dot LCD panel using the HD66206.
Figure 7 Application Example
R1 VEE(-25V)
Notes: 1. The resisances of R1 and R2 depend on the type of LCD panel used. For example, for an LCD panel with a 1/15 bias, R1 and R2 must be 3 k and 33 k, respectively. That is, R1/(4*R1 + R2) should be 1/15. . 2. To stabilize the power supply, place two 0.1-F capacitors near each LCD driver: one between VCC and GND, and the other between VCC and VEE. 3. In this example, the Y1 pin is located to the right as viewed from the front of the panel.
V1 V3 V4 V2 CL1 CL2 M D0L, D1R, D2, D3 DISPOFF FCS TEST
seg638 seg639 seg640 CAR
HD66206
155
HD66206
1
2
3
4
19
20
21
22
23
156
157
158
159
160
CL2 D0L D1R D2 D3 CAR (the first IC) CL1 Y1 (the first IC) Y80 (the first IC)
seg.4 seg.3 seg.2 seg.1 seg.8 seg.7 seg.6 seg.5 seg.12 seg.16 seg.11 seg.15 seg.10 seg.14 seg.9 seg.13
---------------------------------------------seg.76 seg.80 seg.84 seg.88 seg.92 seg.75 seg.79 seg.83 seg.87 seg.91 seg.74 seg.78 seg.82 seg.86 seg.90 seg.73 seg.77 seg.81 seg.85 seg.89
--------------------------------------------------------------------------------------------------------------seg.624 seg.628 seg.632 seg.636 seg.640 seg.623 seg.627 seg.631 seg.635 seg.639 seg.622 seg.626 seg.630 seg.634 seg.638 seg.621 seg.625 seg.629 seg.633 seg.637
The next IC is activated.
SEG.80 SEG.1
Figure 8 Timing Charts for Application Example in Column Driver Operation
1 2 3 4 237 238 239 240 1 2 3 4 237 238 239 240
CL1 FLM M
V3 V4 V2 V3 V4 V2
-------------------
-------------------
Y80 (the first IC) Y79 (the first IC)
V1 V4 V1 V4 V4
V3
Figure 9 Timing Charts for Application Example in Common Driver Operation
156
HD66206
Absolute Maximum Ratings
Item Symbol Ratings -0.3 to +7.0 VCC - 30.0 to VCC + 0.3 -0.3 to VCC + 0.3 VEE - 0.3 to VCC + 0.3 -20 to +75 -55 to +125 Unit V V V V C C 1 and 2 1 and 3 Note 1
Power supply Logic circuit VCC voltage Liquid crystal VEE display drive circuit Input voltage (1) Input voltage (2) Operating temperature Storage temperature VT1 VT2 Topr Tstg
Notes: 1. Measured relative to GND (0V). 2. Applies to CL1, CL2, M, SHL, (, D0L, D1R, D2, D3, FCS, TEST, and ',632)) pins. 3. Applies to V1 to V4 pins. 4. If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It should always be used within the limits of its electrical characteristics in order to prevent malfunction or unreliability.
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HD66206
Electrical Characteristics
DC Characteristics 1 (VCC = 5V 10%, GND = 0V, VCC - VEE = 6 to 28V, and Ta = -20 to 75 C, unless otherwise stated)
Item Input high level voltage Symbol VIH Applicable Pin CL1, CL2, M, SHL, (, D0L, D1R, D2, D3, FCS, TEST, and ',632)) Min. Typ. Max. VCC Unit Conditions V Note
0.7 x VCC --
Input low level VIL voltage Output high level voltage Output low level voltage Vi-Yj on resistance VOH VOL RON1 RON2 Input leakage current (1) IIL1
0
--
0.3 x VCC V -- 0.4 2.0 4.0 5 V V k k A VIN = VCC to GND IOH = -0.4 mA IOL = 0.4 mA ION = 100 A VCC - VEE = 28V 1 and 5 1 and 4
&$5, D0L, D1R &$5, D0L, D1R
Y1 to Y80, V1 to V4
VCC - 0.4 -- -- -- -- -- -- -- --
CL1, CL2, M, SHL, (, D0L, D1R, D2, D3, FCS, TEST, and ',632)) V1 to V4 --
-5
Input leakage current (2) Consumption current (1) Consumption current (2) Consumption current (3) Consumption current (4) Consumption current (5)
IIL2 IGND1
-25 --
-- --
25 3.0
A mA
VIN = VCC to VEE fCL2 = 8.0 MHz fCL1 = 50 kHz fM = 2.3 kHz VCC = 5V VCC - VEE = 28V Checker data FCS = high fCL1 = 50 kHz fM = 2.3 kHz VCC = 5V VCC - VEE = 28V FCS = low 2 and 4
IST IEE1 IGND2 IEE2
-- -- -- --
-- -- -- --
-- -- -- --
200 500 100 500
A A A A
2 to 4 2 and 4 2 and 5 2 and 5
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HD66206
DC Characteristics 2 (VCC = 2.7 to 4.5V, GND = 0V, VCC - VEE = 6 to 28V, and Ta = -20 to 75 C, unless otherwise stated)
Item Input high level voltage Symbol VIH Applicable pin Min. Typ. Max. VCC Unit V Conditions Note
Input low level VIL voltage Output high level voltage Output low level voltage Vi-Yj on resistance VOH VOL RON1 RON2 Input leakage IIL1 current (1)
0.8 x VCC -- CL1, CL2, M, SHL, (, D0L, D1R, D2, D3, FCS, TEST, 0 -- and ',632))
0.2 x VCC V -- 0.4 2.0 4.0 5 V V k k A VIN = VCC to GND IOH = -0.4 mA IOL = 0.4 mA ION = 100 A VCC - VEE = 2 8V 1 and 5 1 and 4
&$5, D0L, and
D1R D1R
VCC- 0.4 -- -- --
-- -- -- -- --
&$5, D0L, and
Y1 to Y80, and V1 to V4
CL1, CL2, M, SHL, (, D0L, D1R, D2, D3, FCS, TEST, and ',632)) V1 to V4 --
-5
Input leakage IIL2 current (2) Consumption IGND1 current (1) Consumption IST current (2) Consumption IEE1 current (3) Consumption IGND2 current (4) Consumption IEE2 current (5)
-25 --
-- --
25 1.5
A mA
VIN = VCC to VEE fCL2 = 6.5 MHz fCL1 = 40.6 kHz fM = 1.8 kHz VCC = 3.0V VCC - VEE = 28V Checker data FCS = high fCL1 = 40.6 kHz fM = 1.8 kHz VCC = 3.0V VCC - VEE = 28V FCS = low 2 and 4
-- -- -- --
-- -- -- --
-- -- -- --
100 500 50 500
A A A A
2 to 4 2 and 4 2 and 5 2 and 5
Notes: 1. Indicates the resistance between one pin from Y1 to Y80 and another pin from the V pins V1 to V4, when a load current is applied to the Y pin; defined under the following conditions: In column driver operation V1 and V3 = VCC - 2/10 (VCC - VEE) V4 and V2 = VEE + 2/10 (VCC - VEE) In common driver operation V1 and V3 = VCC - 2/10 (VCC - VEE) V4 and V2 = VEE + 2/10 (VCC - VEE) V1 and V3 should be near the VCC level, and V4 and V2 should be near the VEE level. All these voltage pairs should be separated by less than V, which is the range within which RON, the LCD drive circuits' output impedance, is stable. Note that V depends on power supply voltage VCC - VEE. See Figure 10.
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HD66206
2. Input and output currents are excluded. When a CMOS input is floating, excess current flows from the power supply through to the input circuit. To avoid this, VIH and VIL must be held to VCC and GND, respectively. 3. VCC - GND current at standby (( input = high) 4. Applies to column driver operation. 5. Applies to common driver operation.
V
V CC V1 V (V) V3 5.6
2.4 V V4 V2 V EE 6 28 VCC-VEE (V)
Figure 10 Relationship between Driver Output Waveform and Level Voltages
160
HD66206
Pin Configuration Each pin configuration is shown below.
Applicable pin: CL1, CL2, SHL M, E, FCS, and TEST VCC
Applicable pin: D2 and D3 PMOS
D3
D2 NMOS Input enable GND
Figure 11 Input Pin Configuration
VCC Applicable pin: D0L and D1R PMOS PMOS D0L NMOS NMOS PMOS GND D1R PMOS NMOS NMOS Input enable GND Output enable Output data Output enable VCC Output data
Figure 12 Input/Output Pin Configuration
VCC Applicable pin: CAR PMOS VCC PMOS Yn NMOS VCC NMOS VEE NMOS VEE GND Applicable pin: Y1-Y80 PMOS V1 V3 V4 V2
Figure 13 Output Pin Configuration
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HD66206
AC Characteristics 1 (In Column Driver Operation) (VCC = 5V 10%, GND = 0V, VCC - VEE = 6 to 28V, and Ta = -20 to +75 C, unless otherwise stated)
Item Clock cycle time Clock high level width Clock low level width Clock setup time Clock hold time Clock rise time Clock fall time Data setup time Data hold time Enable setup time Carry output delay time M phase difference CL1 cycle time Symbol tCYC tCWH tCWL tSCL tHCL tr tf tDS tDH tESU tCAR tCM tCL1 Applicable Pins CL2 CL2 and CL1 CL2 CL1 and CL2 CL1 and CL2 CL1 and CL2 CL1 and CL2 D0L, D1R, D2, D3, and CL2 D0L, D1R, D2, D3, and CL2 Min. 125 40 40 80 80 -- -- 20 20 20 -- -- tCYC x 50 Max. -- -- -- -- -- 1 1 -- -- -- 70 300 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1 1 Note
( and CL2 &$5 and CL2
M and CL1 CL1
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HD66206
AC Characteristics 2 (In Column Driver Operation) (VCC = 2.7 to 4.5V, GND = 0V, VCC - VEE = 6 to 28V, and Ta = -20 to +75 C, unless otherwise stated)
Item Clock cycle time Clock high level width Clock low level width Clock setup time Clock hold time Clock rise time Clock fall time Data setup time Data hold time Enable setup time Carry output delay time M phase difference CL1 cycle time Symbol tCYC tCWH tCWL tSCL tHCL tr tf tDS tDH tESU tCAR tCM tCL1 Applicable pins CL2 CL2 and CL1 CL2 CL1 and CL2 CL1 and CL2 CL1 and CL2 CL1 and CL2 D0L, D1R, D2, D3, and CL2 D0L, D1R, D2, D3, and CL2 Min. 152 65 65 80 120 -- -- 50 50 30 -- -- tCYC x 50 Max. -- -- -- -- -- 1 1 -- -- -- 100 300 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1 1 Note
( and CL2 &$5 and CL2
M and CL1 CL1
Notes: 1. Clock rise time (tr) and clock fall time (tf) must satisfy the following conditions: tr and tf < (tCYC - tCWH - tCWL)/2 tr and tf 50 2. Defined by connecting the load circuit shown in Figure 14.
Test point
30 pF
Figure 14 Load Circuit
163
HD66206
AC Characteristics 3 (In Common Driver Operation) (VCC = 2.7 to 5.5V, GND = 0V, VCC - VEE = 6 to 28V, and Ta = -20 to +75 C, unless otherwise stated)
Item Clock cycle time Clock high level width Clock low level width Clock rise time Clock fall time Data setup time Data hold time Data output delay time Symbol tCYC tCWH tCWL tr tf tDS tDH tDD Applicable Pins CL2 CL2 CL2 CL2 CL2 D0L, D1R, and CL2 D0L, D1R, and CL2 D0L, D1R, and CL2 10 80 1.0 -- -- 100 100 -- Min. Max. -- -- -- 30 30 -- -- 7.0 Unit s ns s ns ns ns ns s 1 Note
Note: Defined by connecting the load circuit shown in Figure 15.
Test point
30 pF
Figure 15 Load Circuit
164
HD66206
tr tCWH
VIH
tf
tCWL
tCYC
CL2
VIL
tDS
VIH
tDH
D0L, D1R, D2, and D3
VIL
tCWH
VIH
tCL1
VIL
CL1
tSCL
CL2
VIL
tHCL
VIH
tCAR
VOH
Last data tCAR
CAR
VOL
E
VIL
tESU
tCM
M
VIH VIL
Figure 16 Common Driver Operation Timing
165
HD66206
tf
CL2
VIH VIL
tCWL
tr
tCWH
tCYC
tDS
Data in (D0L, D1R)
VIH VIL
tDH
tDD
Data out (D0L, D1R)
VOH VOL
Figure 17 Common Driver Operation Timing
166

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