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CXA2164Q
US Audio Multiplexing Decoder
Description The CXA2164Q is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction, and sound processor. Various kinds of filters are built in this IC. Adjustment, mode control and sound processor control are all executed through I2C BUS. Features * Alignment-free VCO and filter * Audio multiplexing decoder, dbx noise reduction decoder, sound processor -- One external input -- Volume control are all included in a single chip. Almost any sort of signal processing is possible through this IC. * Input level, separation adjustments and each mode control are possible through I2C BUS. 48 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25C) 11 * Supply voltage VCC * Operating temperature Topr -20 to +75 * Storage temperature Tstg -65 to +150 * Allowable power dissipation PD 0.6 Range of Operating Supply Voltage 9 0.5
V C C W
V
Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC
Pin Configuration (Top View)
VEWGT VETC SAPIN SAPOUT VCATC VCAIN VEOUT
36 35 34 33 32 31 30 29 28 27 26 25 VCAWGT 37 NC 38 AUX-R 39 AUX-L 40 NC 41 NC 42 NC 43 NC 44 NC 45 LSOUT-R 46 LSOUT-L 47 SDA 48 1 2 3 4 5 6 7 8 9 10 11 12 24 NOISETC 23 STIN 22 SUBOUT 21 NC 20 VCC 19 NC
A license of the dbx-TV noise reduction system is required for the use of this device.
NC
NC
NC
NC
VE
18 SAPTC 17 GND
16 NC 15 IREF
14 VGR 13 NC
PCINT1
PCINT2
MANIN
DGND
SCL
NC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
MAINOUT
COMPIN
NC
PLINT
NC
NC
-1-
E00X21
Block Diagram
MAINOUT
PCINT1
PCINT2
AUX-L
40 39 TVSW EXT1/M1
PLINT
SUBOUT
8 11 4
9 22 3
LFLT 1/2 MATRIX FLT LPF VCA
VCO
1/4
VOL-L
COMPIN 12 LPF NRSW/FOMO/SAPC (+6dB)
VOL-R VOL-L
"STEREO" DeEm WIDEBAND
VOL-R
46 LSOUT-R 47 LSOUT-L
VCA
LPF
ATT LOGIC
STIND
VCC 20
GND 17 LPF DeEm "NOISE" "SAP" HPF RMSDET VE VCA
BPF
SAPVCO
NOISETC
24
NOISE DET
SAPTC 18
SAPIND SPECTRAL LPF LPF RMSDET AMP (+4dB)
IREF SW "PONRES" 1 25 48 27 23
I2C BUS I/F
14
MAININ
15
2
28
32
33
34
35
37
36
SCL
VGR
IREF
SDA
STIN
VE
SAPIN
VETC
DGND
VCAIN
SAPOUT
VEWGT
VEOUT
VCAWGT
VCATC
AUX-R
-2-
CXA2164Q
CXA2164Q
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
VCC 7.5k 35 2.1V 4k
(Ta = 25C, VCC = 9V) Description
1
SCL
--
10.5k x4 3k
Serial clock input pin. VIH > 3.0V VIL < 1.5V
1
2
DGND
--
2
Digital block GND.
VCC 10k
VCC
3
MAININ
4.0V
147 3 53k 4V VCC 15k x4 VCC 147 4
Input the (L + R) signal from MAINOUT (Pin 4).
4
MAINOUT
4.0V
(L + R) signal output pin.
200
1k
5 6 7
NC NC NC
-- -- --
5
-- -- --
6
7
-3-
CXA2164Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 147 8
Description
8
PCINT1
4.0V
30k
22k
VCC 147 9 10k 2k x2 4k 10k
Stereo block PLL loop filter integrating pin.
9
PCINT2
4.0V
10
NC
--
10 VCC 20k 20k
--
147
11
PLINT
5.1V
20k 20k
11
Pilot cancel circuit loop filter integrating pin. (Connect a 1F capacitor between this pin and GND.)
26
20k
50
10k
VCC 16k 16k
147 12
12
COMPIN
4.0V
50k 4V 16k
Audio multiplexing signal input pin.
13
NC
--
13
--
-4-
CXA2164Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
3k
147
14
VGR
1.3V
11k
9.7k
19.4k x4
VCC 11k 11k
Band gap reference output pin. (Connect a 10F capacitor between this pin and GND.)
14
2.06k
VCC 40k 40k 30k 30k 15k x2 30k
VCC
15
IREF
1.3V
30p 1.8k 15 147 6.3k
Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62k (1%) resistor between this pin and GND.)
16k
16 17
NC GND
-- --
VCC 8k
16
-- Analog block GND.
17
10k 3k 1k VCC 4k 50 18
18
SAPTC
4.5V
Set the time constant for the SAP carrier detection circuit. (Connect a 4.7F capacitor between this pin and GND.)
19 20 21
NC VCC NC
-- -- --
19
-- Supply voltage pin. --
20
21
-5-
CXA2164Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Vcc 2k 2k 10P 4k
Description
580
22
SUBOUT
4.0V
2k 2k
22 14.4k 580 147
(L-R) signal output pin.
2k
4k
1k
VCC
23
STIN
4.0V
23k
23k
Input the (L-R) signal from SUBOUT (Pin 22).
11.7k 147 23 147 27 18k 4V 20k 4V 18k
27
SAPIN
4.0V
Input the (SAP) signal from SAPOUT (Pin 25).
Vcc 8k 3.3k
10k 1k 2k 4k 4V 3k Vcc 3k
24
NOISETC
3.0V
x2
Set the time constant for the noise detection circuit. (Connect a 4.7F capacitor between this pin and GND.)
200k 24
Vcc 5P
580
25
SAPOUT
4.0V
580
10k 25 147
SAP FM detector output pin.
24k 10
4k 50
-6-
CXA2164Q
Pin No. 26
Symbol NC
Pin voltage --
Equivalent circuit
26 VCC 7.5k
Description --
28
VE
4.0V
147 28
Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3k resistor in series between this pin and GND.)
29 30 31
NC NC NC
-- -- --
29
-- -- --
Vcc
30
31
580
2.9V 4V 36k
32
VEWGT
4.0V
32 147 580
Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047F capacitor and a 3k resistor in series between this pin and GND.)
8k
30k 8
4k 50
Vcc
33
VETC
1.7V
x4
x4
33
4k 50
20k 7.5
Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3F capacitor between this pin and GND.)
-7-
CXA2164Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Vcc 5P 580
Description
34
VEOUT
4.0V
34 580 10k
Variable de-emphasis output pin. (Connect a 4.7F non-polar capacitor between Pins 34 and 35.)
VCC
47k 20k
47k
35
VCAIN
4.0V
VCC
35
VCA input pin. Input the variable de-emphasis output signal from Pin 34 via a coupling capacitor.
VCC
x4
36 x4
36
VCATC
1.7V
50
4k
7.5
20k
Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10F capacitor between this pin and GND.)
VCC 40k 40k 3p
580
37
VCAWGT
4.0V
37 2.9V 36k 580 147
Weight the VCA control effective value detection circuit. (Connect a 1F capacitor and a 3.9k resistor in series between this pin and GND.)
50
4k 8
30k
8k
-8-
CXA2164Q
Pin No. 38
Symbol NC
Pin voltage --
Equivalent circuit
38
Description --
39
AUX-R
4.0V
10k
VCC
Right channel external input pin.
39 23.5k 40
40
AUX-L
4.0V
23.5k 4V
Left channel external input pin.
41 42 43 44 45
NC NC NC NC NC
-- -- -- -- --
41
-- -- -- -- --
VCC 3k
42
43
44
45
46
LSOUT-R
4.0V
580 46 47 580
LSOUT right channel output pin.
47
LSOUT-L
4.0V
LSOUT left channel output pin.
VCC 7.5k 35 2.1V x2 4k x5
48
SDA
--
7.5k
4.5k
3k
Serial data I/O pin. VIH > 3.0V VIL < 1.5V
48
-9-
Electrical Characteristics COMPIN input level (100% modulation level)
Main (L + R) (Pre-Emphasis: OFF) = 245mVrms SUB (L - R) (dbx-TV: OFF) = 490mVrms Pilot = 49mVrms SAP Carrier = 147mVrms (Ta = 25C, VCC = 9V)
Mode Typ. 32 490 0 -1.2 -3.0 -- 46/47 46/47 46/47 22 20 log ('12k'/ '1k') 15kLPF 15kLPF 20 log ('100%'/ '0%') 20 log ('NRSW = 0'/ 'NRSW = 1')
ST-L (R) 1kHz, 100% mod., NR ON, SAP Carrier (5fH)
fH = 15.734kHz
No. Min. 23 46/47 20 log ('5k'/ '1k') 46/47 46/47 15kLPF 15kLPF 20 log ('100%'/ '0%') 15kLPF 440 --
No signal Mono 1kHz 100% mod. Pre-em. ON Mono 5kHz 30% mod. Pre-em. ON Mono 12kHz 30% mod. 20 log Pre-em. ON ('12k'/ '1k') Mono 1kHz 100% mod. Pre-em. ON Mono 1kHz 200% mod. Pre-em. ON Mono 1kHz, Pre-em. ON SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, NR OFF
Item
Signal
Input pin Input signal Filter
Measurement conditions Output pin
Max. 43 540 1.0
Unit mA mVrms dB
1 MONO MONO MONO MONO MONO MONO ST ST ST ST ST SAP ST 12 12 12 12 12 12 12 12 12 12 12 12 12
Current consumption
Icc
2
Main output level
Vmain
3
Main de-emphasis frequency characteristic
FCdeem
4
Main LPF frequency characteristic
FCmain
-1.0 0.1 -- 61 150 0.15 69 190
1.0 0.5 0.5 -- 230
dB % % dB mVrms
- 10 -
15kLPF 1kBPF SAP 1kHz 100% mod. 20 log ('NRSW NR ON, Pilot (fH) = 1'/ 'NRSW = 0') 1kBPF
5
Main distortion
THDm
6
Main overload distortion
THDmmax
7
Main S/N
SNmain
8
Sub output level
Vsub
9
Sub LPF frequency characteristic
FCsub
22 22 22 22 47 47
-3.0 -- -- 56 60 60
-0.5 0.1 0.2 64 70 70
1.0 1.0 2.0 -- -- --
dB % % dB dB dB
10
Sub distortion
THDsub
11
Sub overload distortion
THDsmax
12
Sub S/N
SNsub
13
Cross talk Stereo SAP
CTst
CXA2164Q
14
Cross talk SAP Stereo
CTsap
No. Mode Input pin 0dB = 49mVrms 20 log (`on level'/ 'off level') 2.0 130 -3.0 -- 46 -12.0 BUS RETURN 2.0 23 46/47 46/47 46/47 15kLPF EXT1 = '1' EXT1 = '1' M1 = '0' EXT1 = '1' EXT1 = '1' EXT1 = '1' EXT1 = '1' VOL-L = '0' VOL-R = '0' 39/40 Sine wave 1kHz, 490mVrms 1kBPF 15kLPF 15kLPF 15kLPF 1kBPF 46/47 46/47 46/47 46/47 46/47 46/47 46/47 23 23 15kLPF 23 440 -- -- -- 80 -- 55 -9.0 4.0 35 35 35 35 490 -90 0.01 0.03 88 -90 2.5 0 2.5 6.0 -- -6.5 6.0 -- -- -- -- 540 -80 0.3 0.3 -- -80 160 190 6.0 10.0 25 20 log ('10k'/ '1k') 25 15kLPF 25 25 20 log ('100%'/ '0%') 15kLPF 0dB = 147mVrms 20 log (`on level'/'off level') 15kLPF 15kLPF BUS RETURN dB mVrms dB % dB dB dB dB dB dB dB mVrms dB % % dB -9.0 dB -6.0 -3.0
Item
Symbol
Input signal Filter Min. Unit Typ. Max.
Measurement conditions Output pin
15 ST 12 Change PILOT (fH) Level
Stereo ON level
THst
16 SAP 12 12 12 12 SAP 1kHz, NR OFF SAP 1kHz 100% mod. NR OFF SAP 10kHz 30% mod. NR OFF SAP SAP SAP SAP 1kHz 100% mod. NR OFF
Stereo ON/OFF hysteresis
HYst
17
SAP output level
Vsap
18
SAP LPF frequency characteristic
FCsap
19
SAP distortion
THDsap
20
SAP S/N
SNsap
21 SAP 12 Change SAP Carrier (5fH) Level ST-L 300Hz 30% mod. NR ON ST-R 300Hz 30% mod. NR ON ST-L 3kHz 30% mod. NR ON ST-R 3kHz 30% mod. NR ON Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms Sine wave 1kHz, 2Vrms Sine wave 1kHz, 490mVrms
SAP ON level
CTsap
22 ST 12 12 12 12 39/40 39/40 39/40 39/40 39/40 ST ST ST EXT EXT EXT EXT EXT EXT
SAP ON/OFF hysteresis
THsap
- 11 -
23
ST separation 1 L R
HYsap
24
ST separation 1 R L
STLsep1
25
ST separation 2 L R
STRsep1
26
ST separation 2 R L
STLsep2
27
LSOUT output level
Vtv
28
LSOUT mute attenuation
MUls
29
LSOUT distortion
THDIs
30
LSOUT overload distortion
THDlsmax
31
LSOUT S/N
SNls
CXA2164Q
32
LSOUT volume maximum attenuation
VOLmin
dB
Electrical Characteristics Measurement Circuit
BUFF FILTERS 15kHz LPF fH BPF 1kHz BPF MEASURES S4 S3 S2 S1
TANTALUM
36 34 29 33 30 25 26
35
TANTALUM
C9 10 C12 3.3 C16 2700p 27 28 C17 4.7
C18 4.7 R4 3k C13 0.047 32 31 R7 3.3k
NC
VE
VETC
VCAIN
SAPIN
VCATC
VEOUT
37 VCAWGT NOISETC C23 4.7 C24 4.7 39 AUX-R SUBOUT 22 STIN 23 24
V4 AC
C4 4.7
38 NC
40 AUX-L NC 21
V3 AC VCC 20
C3 4.7 41 NC
VEWGT
SAPOUT
R1 3.9k
C2 1
NC
NC
NC
MAININ
NC
PCINT2
DGND
NC
PCINT1
SCL
MAINOUT
NC
NC
PLINT
R2 220 1 2 3 R3 220 I2C BUS DATA C11 4.7 DGND 4
5
6
7 R6 1MEG C14 5600p
8
9
10 C18 1
11 C19 4.7
COMPIN
- 12 -
42 NC 43 NC 44 NC 45 NC 46 LSOUT-R 47 LSOUT-L 48 SDA 12 R5 C15 100k 0.012 GND
C22 100 NC 19 GND SAPTC 18 C21 4.7 GND 17 GND NC 16 R8 62k IREF 15 METAL 1% VGR 14 C20 10 NC 13
VCC V6 9V
C6 4.7
C5 4.7
CXA2164Q
V5 SIGNAL AC GENERATOR
CXA2164Q
Adjustment Method 1. ATT adjustment 1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the LSOUT-L output level. Then, adjust the "ATT" data for ATT adjustment so that the LSOUT-L output goes to the standard value (490mVrms). 3) Adjustment range: 20% Adjustment bits: 4 bits 2. Separation adjustment 1) TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the "WIDEBAND" adjustment data to reduce LSOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3kHz and adjust the "SPECTRAL" adjustment data to reduce LSOUT-R output to the minimum. 4) The adjustments in 2 and 3 above are performed to optimize the separation. 5) "WIDEBAND" "SPECTRAL" Adjustment range: 30% Adjustment range: 15% Adjustment bits: 6 bits Adjustment bits: 6 bits Note) Adjust this IC through Tuner and IF when this IC is mounted in the set.
- 13 -
CXA2164Q
Register Specifications Slave address SLAVE RECEIVER SLAVE TRANSMITTER 84H (1000 0100) Register table SUB ADDRESS MSB LSB BIT7 EXT1 BIT6 BIT5 TEST-DA 0000 0001 0010 0011 0100 0101 DATA BIT4 TEST1 SPECTRAL WIDEBAND NRSW FOMO SAPC M1 BIT3 BIT2 ATT BIT1 BIT0 85H (1000 0101)
VOL-L VOL-R : Don't Care
Status Registers STA1 BIT7 STA2 BIT6 STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 -- STA6 BIT2 -- STA7 BIT1 -- STA8 BIT0 --
POWER STEREO ON RESET
Note) The microcomputer reads both SAP and NOISE status and judges SAP discrimination.
- 14 -
CXA2164Q
Description of Registers Control registers Register ATT SPECTRAL WIDEBAND TEST-DA TEST1 EXT1 NRSW FOMO M1 SAPC VOL-L VOL-R Number of bits 4 6 6 1 1 1 1 1 1 1 1 1 Classification1 A A A T T U U U U S U U Standard setting 9 1F 1F 0 0 0 0 0 1 0 3F 3F Input level adjustment Adjustment of stereo separation (3kHz) Adjustment of stereo separation (300Hz) DAC test mode Test mode Selection of TV mode or external input mode. Selection of the output signal (Stereo mode, SAP mode) Forced MONO (Left channel only is MONO during SAP output.) Selection of LSOUT mute function ON/OFF (0: mute ON, 1: mute OFF) Selection of SAP mode or L + R mode according to the presence of SAP broadcasting Left channel volume control Right channel volume control Contents
1 Classification U: User control A: Adjustment S: Proper to set T: Test Status registers Register PONRES STEREO SAP NOISE Number of bits 1 1 1 1 POWER ON RESET detection; Stereo discrimination of the COMPIN input signal; SAP discrimination of the COMPIN input signal; Noise level discrimination of the SAP signal; Contents 1: RESET 1: Stereo 1: SAP 1: Noise
- 15 -
CXA2164Q
Description of Control Registers ATT (4): Perform input level adjustment. 0 = Level min. F = Level max.
SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment. 0 = Level max. 3F = Level min. WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment. 0 = Level min. 3F = Level max. TEST-DA (1): Set DAC output test mode. 0 = Normal mode 1 = DAC output test mode In addition, the following output are present at Pin 47. LSOUT-L (Pin 47): DA control DC level TEST1 (1): Monitor SAP BPF and NR BPF output. 0 = Normal mode 1 = SAP BPF and NR BPF output In addition, the following outputs are present at Pins 47 and 46. LSOUT-L (Pin 47): SAP BPF OUT LSOUT-R (Pin 46): NR BPF OUT Select TV mode or external input mode 0 = TV mode 1 = External input mode Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode Mute the LSOUT-L and LSOUT-R output. 0 = Mute ON 1 = Mute OFF Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected - 16 -
EXT (1):
NRSW (1):
FOMO (1):
M1 (1):
SAPC (1):
CXA2164Q
VOL-L (6):
LSOUT-L output signal level control 0 = Volume min. 3F = Volume max. -1.25dB/STEP LSOUT-R output signal level control 0 = Volume min. 3F = Volume max. -1.25dB/STEP
VOL-R (6):
- 17 -
CXA2164Q
Description of Mode Control Mode control SAPC = 0 "Select dbx input and TV decoder output" Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) * During ST input: left channel: L, right channel: R * During other input: left channel: L + R, right channel: L + R NRSW = 1 (SAP output) * When there is "SAP" during SAP discrimination - left channel: SAP, right channel: SAP * When there is "No SAP", output is the same as when NRSW = 0. SAPC = 1 "Select dbx input and TV decoder output" Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left
NRSW
NRSW = 1 (SAP output) * Regardless of the presence of SAP discrimination, dbx input: "SAP" left channel: SAP, right channel: SAP However, when there is no SAP, SAPOUT output is soft muted (-7dB)
"Forced MONO" FOMO FOMO = 1 * During SAP output: left channel: L + R, right channel: SAP * During ST or MONO output: left channel: L + R, right channel: L + R Change the selection conditions for "MONO or ST output" and "SAP output". SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. "MUTE" M1 = 0: LSOUT-L, R output is muted.
SAPC
M1
- 18 -
CXA2164Q
Decoder Output and Mode Control Table 1 (SAPC = 1) Input signal mode ST 0 0 MONO 1 0 0 0 0 1 1 1 STEREO 1 1 1 1 1 1 0 0 MONO & SAP 0 0 0 0 1 1 STEREO & SAP 1 1 1 1 Mode detection SAP 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 NOISE 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Mode control NRSW 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 FOMO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L-R MUTE L-R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L-R MUTE SAP SAP (SAP) (SAP) Output Lch L+R SAP L+R L+R (SAP) L+R L L+R L L+R SAP L+R (SAP) L+R L+R L+R SAP L+R (SAP) L+R L L+R SAP L+R (SAP) L+R Rch L+R SAP SAP L+R (SAP) (SAP) R L+R R L+R SAP SAP (SAP) (SAP) L+R L+R SAP SAP (SAP) (SAP) R L+R SAP SAP (SAP) (SAP)
Note (SAP) : The SAPOUT output signal is soft muted (approximately -7dB). The signal is soft muted when NOISE = 1. : Don't care. 1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
- 19 -
CXA2164Q
Decoder Output and Mode Control Table 2 (SAPC = 0) Mode detection Input signal mode ST 0 0 MONO 1 0 0 0 1 1 1 STEREO 1 1 1 1 1 1 0 0 0 MONO & SAP 0 0 0 0 0 1 1 1 STEREO & SAP 1 1 1 1 1 SAP 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOISE 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 NRSW 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FOMO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mode control dbx input MUTE MUTE MUTE (SAP) (SAP) L-R MUTE L-R MUTE L-R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE (SAP) (SAP) L-R MUTE SAP SAP L-R MUTE (SAP) (SAP) Output Lch L+R L+R L+R (SAP) L+R L L+R L L+R L L+R (SAP) L+R L+R L+R SAP L+R L+R L+R (SAP) L+R L L+R SAP L+R L L+R (SAP) L+R Rch L+R L+R L+R (SAP) (SAP) R L+R R L+R R L+R (SAP) (SAP) L+R L+R SAP SAP L+R L+R (SAP) (SAP) R L+R SAP SAP R L+R (SAP) (SAP)
Note (SAP) : The SAPOUT output signal is soft muted (approximately -7dB). The signal is soft muted when NOISE = 1. : Don't care. 1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. - 20 -
CXA2164Q
Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV kHz 50 AM-DSB-SC 50
25
25
L-R dbx-TV NR
PILOT
15 SAP dbx-TV NR FM 10kHz 50 - 10kHz 2fH 3fH 4fH 5fH TELEMETRY FM 3kHz 3 6fH 6.5fH f
L+R 5 50 - 15kHz fH
fH = 15.734kHz
Fig. 1. Base band spectrum
I2C BUS DECODER MODE CONTROL (MAIN OUT) (MAIN IN)
PLL (VCO 8fH) STEREO LPF MVCA
2fHL0 fHL90 fHL0
PILOT DET
(COMPIN)
MAIN LPF DE.EM PILOT CANCEL SUB LPF L-R (DSB) DET
12
4
L+R WIDEBAND SUBVCA 4.7
3
MATRIX
(SUBOUT) (ST IN)
22
L-R 4.7
23
NR SW
(Lch) to TVSW
SAP BPF
SAP(FM) DET INJ. LOCK
A
SAP LPF (SAP OUT) (SAP IN)
dbx-TV BLOCK
B
(Rch)
25
4.7 NOISE DET
2
27
I 2C BUS DECODER
MODE CONTROL
SAP DET
I C BUS DECODER MODE CONTROL
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
(ST IN) FIXED VARIABLE DEEMPHASIS DEEMPHASIS
23
(SAP IN)
NR SW
A
(VE OUT) (VCA IN)
B
VCA to MATRIX
34
4.7 HPF LPF LPF RMS DET RMS DET
35
27
Fig 3. dbx-TV block - 21 -
CXA2164Q
(1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 12) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L - R (SUB) The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 25 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. (5) dbx-TV block Either the L - R signal or SAP signal input respectively from ST IN (Pin 23) or SAP IN (Pin 27) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix, TVSW The signals (L + R, L - R, SAP) input to "MATRIX" become the outputs for the ST-L, ST-R, MONO and SAP signals according to the mode control and whether there is ST / SAP discrimination. "TVSW" switches the "MATRIX" output signal and external input signal. (7) Others "MVCA" is a VCA which adjusts the input signal level to the standard level of this IC. "Bias" supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 15) with GND become the reference current. - 22 -
Application Circuit
4.7 3.3 0.047 4.7 26 25 32 31 30 29 2700p 27 28 34 33 3k 3.3k
TANTALUM
36
35
TANTALUM
10
NC
VE
VETC
VCAIN
SAPIN
VCATC
VEOUT
37 NOISETC 4.7 STIN 23 4.7 SUBOUT 22 24
VCAWGT
38 NC
4.7
39 AUX-R
AUX input NC 21
4.7
40 AUX-L
VEWGT
SAPOUT
3.9k
1
NC
NC
NC
+9V VCC 20 100 NC 19
41 NC
42 NC
43 NC
SAPTC 18 4.7 GND 17 GND NC 16 62k IREF 15 METAL 1% VGR 14 10
MAININ
NC
PCINT2
DGND
NC
PCINT1
SCL
MAINOUT
NC
NC
PLINT
1 2 3 4
5
6
7 1MEG
8
9
10 1 5600p 100k 0.012
11 4.7
220 4.7
220
CXA2164Q
-com
DGND
Composite baseband signal input
COMPIN
12
- 23 -
44 NC
45 NC
4.7
46 LSOUT-R
LS output
4.7
47 LSOUT-L
48 SDA
NC 13
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA2164Q
I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 High level input voltage Low level input voltage High level input current Low level input current Item Symbol VIH VIL IIH IIL Min. 3.0 0 -- -- 0 3 -- 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 10 10 0.4 -- 10 100 -- -- -- -- -- -- -- 1 300 -- ns s ns s s Unit V
A V mA pF kHz
Low level output voltage SDA (Pin 48) during 3mA inflow VOL Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation IOL CI fSCL tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSU: DAT tR tF tSU: STO
I2C BUS load conditions: Pull-up resistor 4k (Connect to +5V) Load capacity 200pF (Connect to GND)
- 24 -
CXA2164Q
I2C BUS Control Signal
SDA tBUF SCL P S tHD: STA tLOW tHIGH tSU: STA tSU: DAT Sr tSU: STO P tR tF tHD: STA
tHD: DAT
I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal. * Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
* I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S
Stop Condition P
SDA
SCL
- 25 -
CXA2164Q
* I2C data Write (Write from I2C controller to the IC)
L during Write MSB SDA HIZ MSB LSB HIZ
SCL S
1
2
3
4
5
6
7
8
9
1
8
9
Address MSB LSB HIZ HIZ
ACK
Sub Address
ACK
1
8
9
1
8
9
DATA (n)
ACK
DATA (n + 1)
ACK
DATA (n + 2)
HIZ
HIZ
8
9
1
8
9 P
Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically.
DATA
ACK
DATA
ACK
* I2C data Read (Read from the IC to I2C controller)
H during Read HIZ SDA
SCL S
1
6
7
8
9
1
7
8
9 P
Address
ACK
DATA
ACK
* Read timing
MSB IC output SDA LSB
SCL
9
1
2
3
4
5
6
7
8
9
Read timing
ACK
DATA
ACK
Data Read is performed during SCL rise.
- 26 -
CXA2164Q
Input level vs. Distortion characteristics 1 (MONO)
Input signal: MONO (Pre-emphasis on), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF Measurement point: LSOUT-L/R
Input level vs. Distortion characteristics 2 (Stereo)
Input signal: Stereo L = -R (dbx-TVNR ON), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, ST mode Measurement point: LSOUT-L/R
1.0
10
Distortion [%]
Distortion [%]
0.1 1.0 Standard level (100%) -10 0 Input level [dB] -10 0 Input level [dB] 10 Standard level (100%) 10
Input level vs. Distortion characteristics 3 (SAP)
Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, SAP mode Measurement point: LSOUT-L/R
10
Distortion [%]
1.0
Standard level (100%) -10 0 Input level [dB] 10
- 27 -
CXA2164Q
Stereo LPF frequency characteristics
10
Main LPF and Sub LPF frequency characteristics
30
5
Gain (FC main and FC sub) [dB]
20 10 0 -10 -20 -30 -40 -50
Gain [dB]
0
-5
-10
0
20
40
60
80
100
1
2
5
7
10
20
50 70 100
Frequency [kHz]
Frequency [kHz]
SAP frequency characteristics and group delay
100 20 5fH 10 Gain 90 80 -20 0
Volume charactiristics
Gain [dB]
60 0 50 40 -10 Group delay 3.8fH 20 40 60 80 30 20 -20 6.2fH 100 10 0 120
Group delay [s]
70
LSOUT output level [dB]
-40
-60
-80
AUXIN (Pins 39, 40) 1kHz, 490mVrms Output: LSOUT (Pins 46, 47) 0 1F 2F F Control data VOL-L, VOL-R 3F
Input:
-100
Frequency [kHz]
- 28 -
CXA2164Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 0.4 + 0.4 12.0 - 0.1 36 25 + 0.1 0.15 - 0.05 0.15
37
24
48
13
+ 0.2 0.1 - 0.1
0.8
+ 0.15 0.3 - 0.1
0.24
M
+ 0.35 2.2 - 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.7g
- 29 -
0.9 0.2
Sony Corporation
1
12
13.5

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