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LCZ-R00136-- 1 N o . LCY-00136 D A T E Jun.26.2001
TECHNICAL
LITERATURE
FOR Control IC for T F T -L C D m o d u l e
Model No.
LZ9FC22
The technical literature is subject to change without notice. So,please contact SHARP or its agency to start workings for Mass production.
SHARP CORPORATION TFT LIQUID CRYSTAL DISPLAY GROUP
Although this technical literature shows major applications of our products, this will not guarantee the extension of industrial prossession and other rights. And we won't have any responsibility to your trouble with third party over the industrial possession by using our products.
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LCZ-R00136-- 1
1. Introduction
This data sheet is to introduce the specification of LZ9FC22 , timing Control IC for TFT - LCD module.
Applicable TFT-LCD module : QVGA(Portrate / Landscape) pixel type module
Functions: Timing Control IC for TFT-LCD module (1)By inputting Clock signal, Horizontal sync. signal, Vertical sync. signal, the following signals Synchronized with above signal are generated; (A)Driving signal for source driver (B)Driving signal for gate driver (C)Signal for common electrode driving signal preparation (B)Signal for standard voltage preparation :CLK,SPL,SPR,LP,PS :CLS,SPS :REV :REVV0
(2)Horizontal and Vertical reverse scanning function
Input/Output signal timing chart for above cases : See Fig.1. Fig.2. Fig.3. Outline dimensions 2. Feature : See Fig.4.
Process Wafer substrate Package Operating Temperature Propagation delay time
: : : :
CMOS P-type silicon substrate -30*Z~ +85*Z 1ns/gate (Condition : VDD=3.3V, Topr=25*Z )
: 72QFP(0.5mm pin pitch)
*REMARK Not designed or rated as radiation harded
LCZ-R00136-- 2 3. Pin assignment
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
IC ICU ICD O2M
I/O IC ICU IC IC IC IC IC IC IC IC IC IC IC IC ICU IC IC IC IC IC IC ICU ICU ICD ICU O2M O2M O2M TO2M O2M TO2M O2M
Signal Name DCLK SETR R0 R1 R2 R3 R4 R5 GND N.C. G0 G1 G2 G3 G4 G5 TEST B0 B1 B2 B3 B4 B5 TEST HREV ENAB VDD GND TEST REV REVV0 PS SPR LBR SPL LP
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
I/O O3M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M O2M TO2M TO2M TO2M ICU IC IC O2M ICU IC IC
Signal Name CLK GND OB5 OB4 OB3 OB2 OB1 OB0 VDD GND OG5 OG4 OG3 OG2 OG1 OG0 GND OR5 OR4 OR3 OR2 OR1 OR0 GND CLS SPS VDD GND UBL VREV TEST SIZEC0 MOD REM HS VS
:Input buffer CMOS level :Input buffer CMOS level with PULL UP resistance :Input buffer CMOS level with PULL DOWN resistance :Output buffer IOL=0.8mA(VDD=3V)
TO2M :Tri-state Output buffer IOL=0.8mA(VDD=3V) VDD GND N.C. :Power supply pin :Earth pin :Non Connection pin
LCZ-R00136-- 3
4. Explanation of input/Output signal
Pin No. Signal Name 1 DCLK 2 SETR 3 R0 4 R1 5 R2 6 R3 7 R4 8 R5 9 GND 10 N.C. 11 G0 12 G1 13 G2 14 G3 15 G4 16 G5 17 TEST 18 B0 19 B1 20 B2 21 B3 22 B4 23 B5 24 TEST 25 HREV 26 27 28 29 30 31 32 33 34 ENAB VDD GND TEST REV REVV0 PS SPR LBR
35 36
SPL LP
Explanation Input terminal for data clock signal Input terminal for control signal for PS (SIZEC0 = "L" to the apploication) Input terminal for red data signal(LSB) Input terminal for red data signal Input terminal for red data signal Input terminal for red data signal Input terminal for red data signal Input terminal for red data signal(MSB) Ground Non connection Input terminal for green data signal(LSB) Input terminal for green data signal Input terminal for green data signal Input terminal for green data signal Input terminal for green data signal Input terminal for green data signal(MSB) Input terminal for test normal state:H level Input terminal for blue data signal(LSB) Input terminal for blue data signal Input terminal for blue data signal Input terminal for blue data signal Input terminal for blue data signal Input terminal for blue data signal(MSB) Input terminal for test (normal state:H level) Input terminal for setting up right/left reverse scanning H level : Normal L level : Reverse scanning Input terminal for signal to settle the Horizontal display position Input terminal for Power Supply voltage Input terminal for Ground Input terminal for test (normal state:H level) Signal output for common electrode driving signal preparation Signal output for standard voltage preparation Control signal output for sourve driver Start signal output for source driver (for right/left reverse scannning, normally high impedance) Output signal for right/left reverse scannning HREV=H : H level output =L : L level output Start signal output for source driver (for normal scanning. At right/left reverse scanning, high impedance) Data transferring signal output for source driver
I/O I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O
LCZ-R00136-- 4
Pin No. Signal Name 37 CLK 38 GND 39 OB5 40 OB4 41 OB3 42 OB2 43 OB1 44 OB0 45 VDD 46 GND 47 OG5 48 OG4 49 OG3 50 OG2 51 OG1 52 OG0 53 GND 54 OR5 55 OR4 56 OR3 57 OR2 58 OR1 59 OR0 60 GND CLS 61 62 SPS 63 VDD 64 GND 65 UBL
66 67 68
VREV TEST SIZEC0
69 70 71 72
MOD REM HS VS
Explanation I/O Clock signal output for source driver O Ground Blue data signal output for source driver(MSB) O Blue data signal output for source driver O Blue data signal output for source driver O Blue data signal output for source driver O Blue data signal output for source driver O Blue data signal output for source driver(LSB) O Power Supply voltage Ground Green data signal output for source driver(MSB) O Green data signal output for source driver O Green data signal output for source driver O Green data signal output for source driver O Green data signal output for source driver O Green data signal output for source driver(LSB) O Ground Red data signal output for source driver(MSB) O Red data signal output for source driver O Red data signal output for source driver O Red data signal output for source driver O Red data signal output for source driver O Red data signal output for source driver(LSB) O Ground Clock signal output for source driver O Start signal output for gate driver O Power Supply voltage Ground Output signal for up/down reverse scanning O VREV=H : H level output VREV=L : L level outuput Input terminal for setting up up/down reverse scannning O (H:Normal L:Reverse scanning) I Input terminal for test (normal state : L level) Input signal for drive condition change I SIZEC0 = H : Portrate QVGA(240RGB x 320) = L : Landscape QVGA(320RGB x 240) O Output signal for gate driver Input terminal for reset signal (Give the signal that becomes I H level fixation from the L level at the time of the power supply input ) I Input terminal for horizontal sync. signal Input terminal for vertical sync. Signal I
LCZ-R00136-- 5 5. Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage Operating temperature Strage temperature Symbol VDD VI VO Topr Tstg Rating -0.3 ~ 6.0 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -30 ~ +85 -55 ~ +150 Unit V V V *Z *Z
6. Electrical Specifications 6-1.Operating Conditions Parameter Supply voltage Operating temperature Symbol VDD Topr Min. 2.7 -30 Typ. 3.3 Max. 3.6 +85 Unit V *Z
6-2.Electrical Characteristics (VDD=+2.7~+3.6V, Ta= -30 ~ +85*Z ) Parameter Input "Low" voltage Input "High" voltage Input" High "current Input "High" current Input "Low" current Input "Low" current Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output Leakage current Symbol VIL1 VIH1 | IIH1 | | IIH2 | | IIL1 | | IIL2 | VOL1 VOH1 VOL2 VOH2 | IOZ | VI=VDD(V) VI=VDD(V) VI= 0 (V) VI= 0 (V) IOL1= 1.6 (mA) IOH1= - 0.8 (mA) IOL2= 0.8 (mA) IOH2= - 0.4 (mA) High-impedance state VDD-0.5 1.0 VDD-0.5 0.4 2.0 2.0 0.7*~ VDD 1.0 36.0 1.0 36.0 0.4 Test conditions Min. Typ. Max. 0.3*~ VDD Unit V V EA EA EA EA V V V V EA 8 7 2 3 4 5 6 * 1
*1 : Applied to Input pins (IC,ICU,ICD) *2 : Applied to Input pins (IC,ICU) *3 : Applied to Input pins (ICD) *4 : Applied to Input pins (IC,ICD) *5 : Applied to Input pins (ICU) *6 : Applied to Output pins (O2M,TO2M) *7 : Applied to Output pins (O2M, TO2M) *8 : Applied to Output pins (TO2M)
LCZ-R00136-- 6
7. Condition for signal input (1) Portrate QVGA(240RGBx320) : SIZEC0 = H level Parameter Symbol DCLK frequency fDCLK HS frequency fHS VS frequency fVS Min. 4.5 fDCLK /330 15 fHS /440 50 Typ. Max. 6.8 fDCLK /254 26 fHS /332 80 Unit MHz KHz KHz Hz Hz
(2) Landscape QVGA(320RGBx240) : SIZEC0 = L level Parameter Symbol DCLK frequency fDCLK HS frequency fHS VS frequency fVS Min. 4.5 fDCLK /440 12.5 fHS /330 50 Typ. Max. 6.8 fDCLK /334 20 fHS /248 82 Unit MHz KHz KHz Hz Hz
LCZ-R00136-- 7
1-1. Portrate type QVGA(240RGB x 320) (SIZEC0 = H level)
(Te + 242) ~ 330DCLK
HS
50 ~120ns 14DLK 50 ~120ns 0.4Tc ~ 0.6Tc
DCLK
Tc R0*5 G0*5 B0*5 Te=12 ~73DLK D1 D2 D3 D238 D239 D240
ENAB
10DLK
240DCLK
CLK
OR0*5 OG0*5 OB0*5
ODP
OD2
OD3
OD238 OD239 OD240
1DLK
SPL LP CLS
2DLK
1DLK
204DCLK 12DLK 30DCLK
PS
3DLK
REV REVV0 Fig.1-1 Horizontal counter timing chart-a (ENAB signal : valid)
1-2. Portrate type QVGA(240RGB x 320) (SIZEC0 = H level)
315 ~ 330DCLK
LCZ-R00136-- 8
HS
50 ~120ns
14DLK 50 ~120ns 0.4Tc ~ 0.6Tc
DCLK
Tc R0*5 G0*5 B0*5 73DLK D1 D2 D3 D238 D239 D240
ENAB
("L" level Fixed) 10DLK
CLK
OR0*5 OG0*5 OB0*5
ODP
OD2
OD3
OD238 OD239 OD240
1DLK
SPL LP CLS
2DLK
1DLK
204DCLK 12DLK 30DCLK
PS
3DLK
REV REVV0 Fig.1-2 Horizontal counter timing chart-a (ENAB signal : L level fixed)
2-1. Landscape type QVGA(320RGB x 240) (SIZEC0 = L level)
(Te + 322) ~ 440DCLK
LCZ-R00136-- 9
14DLK
HS DCLK
50 ~120ns
50 ~120ns 0.4Tc ~ 0.6Tc
Tc R0*5 G0*5 B0*5 Te = 12 ~73DLK D1 D2 D3 D318 D319 D320
ENAB
10DLK
320DCLK
CLK
OR0*5 OG0*5 OB0*5
ODP
OD2
OD3
OD318 OD319 OD320
1DLK
SPL LP CLS
12DLK 2DLK
1DLK
299DCLK 31DCLK
PS
(SETR="L") 68DCLK 22DCLK 22DCLK 23DCLK
PS
(SETR="H") 3DLK 14DCLK 13DCLK 189DCLK
REV REVV0 Fig.2-1 Horizontal counter timing chart-a (ENAB signal : valid)
2-2. Landscape type QVGA(320RGB x 240) (SIZEC0 = L level)
395 ~ 440DCLK
LCZ-R00136-- 10
HS
50 ~120ns
14DLK 50 ~120ns 0.4Tc ~ 0.6Tc
DCLK
R0*5 G0*5 B0*5 Te = 73DLK D1 D2 D3 D318 D319 D320
ENAB
("L" level fixed) 10DLK
CLK
OR0*5 OG0*5 OB0*5
ODP
OD2
OD3
OD318 OD319 OD320
1DLK
SPL LP CLS
12DLK 2DLK
1DLK
299DCLK 31DCLK
PS
(SETR="L") 68DCLK 22DCLK 22DCLK 23DCLK
PS
(SETR="H") 3DLK 14DCLK 13DCLK 189DCLK
REV REVV0 Fig.2-2 Horizontal counter timing chart-b (ENAB signal : L level fixed)
LCZ-R00136-- 11
3. Vertical counter timing chart
332H ~ 440H*iSIZEC0 = "H"*j 248H ~ 330H*iSIZEC0 = "L"*j 1H ~ 100H (TYP.3H)
VS
1.5 ~ 4Es
DATA
HS
8H*iSIZEC0 = "H"*j 4H*iSIZEC0 = "L"*j 2H
Vertical display period
SPS
320H*iSIZEC0 = "H"*j 240H*iSIZEC0 = "L"*j 0H
Fig.3 Vertical counter timing chart
LCZ-R00136-- 12
Fig.4. Outline dimentions

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