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8-Bit, 250 MSPS 3.3 V A/D Converter
AD9480
FEATURES
DNL = 0.25 LSB INL = 0.5 LSB Single 3.3 V supply operation (3.0 to 3.6 V) Power dissipation of 590 mW at 250 MSPS 1 V p-p analog input range Internal 1.0 V reference Single-ended or differential analog inputs LVDS outputs (ANSI 644 levels) Power-down mode Clock duty cycle stabilizer
FUNCTIONAL BLOCK DIAGRAM
VREF SENSE AGND DrGND DRVDD AVDD
REFERENCE
AD9480
VIN+ VIN-
T&H
8-BIT ADC PIPELINE CORE
8
LVDS
16
D7-D0 (LVDS)
CLK+ CLK-
CLOCK MGMT
DCO+ DCOLOGIC (LVDS)
04619-0-001
APPLICATIONS
Digital oscilloscopes Instrumentation and measurement Communications: Point-to-point radios Predistortion loops
PDWN S1
LVDSBIAS
Figure 1.
GENERAL DESCRIPTION
The AD9480 is an 8-bit, monolithic analog-to-digital converter optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a 250 MSPS conversion rate, with excellent linearity and dynamic performance over its full operating range. To minimize system cost and power dissipation, the AD9480 includes an internal reference and track-and-hold circuit. The user only provides a 3.3 V power supply and a differential encode clock. No external reference or driver components are required for many applications. The digital outputs are LVDS (ANSI 644) compatible with an option of twos complement or binary output format. The output data bits are provided in parallel fashion along with an LVDS output clock, which simplifies data capture. Fabricated on an advanced BiCMOS process, the AD9480 is available in a 44-lead surface-mount package (TQFP) specified over the industrial temperature range (-40C to +85C).
PRODUCT HIGHLIGHTS
1. Superior linearity. A DNL of 0.25 makes the AD9480 suitable for instrumentation and measurement applications. Power-down mode. A power-down function may be exercised to bring total consumption down to 15 mW. LVDS outputs (ANSI-644). LVDS outputs simplify timing and improve noise performance.
2.
3.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9480
TABLE OF CONTENTS
DC Specifications ............................................................................. 3 Digital Specifications........................................................................ 4 AC Specifications.............................................................................. 5 Switching Specifications .................................................................. 6 Timing Diagram ........................................................................... 6 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels........................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Definitions ......................................................................................... 9 Equivalent Circuits ......................................................................... 11 Application Notes ........................................................................... 12 Clocking the AD9480................................................................. 12 Analog Inputs.............................................................................. 12 Voltage Reference ....................................................................... 13 Digital Outputs ........................................................................... 14 Output Coding............................................................................ 14 Interleaving Two AD9480s........................................................ 14 Data Clock Out........................................................................... 14 Typical Performance Characteristics ........................................... 15 AD9480 Evaluation Board ............................................................ 19 Power Connector........................................................................ 19 Analog Inputs.............................................................................. 19 Gain.............................................................................................. 19 Optional Operational Amplifier............................................... 19 Clock ............................................................................................ 19 Optional Clock Buffer ............................................................... 19 Optional XTAL ........................................................................... 19 Voltage Reference ....................................................................... 20 Data Outputs............................................................................... 20 Evaluation Board Bill of Materials ............................................... 21 PCB Schematics .............................................................................. 22 PCB Layers ...................................................................................... 24 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27
REVISION HISTORY 7/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD9480
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = -40C, TMAX = +85C, AIN = -1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL) AD9480BSUZ-250 AD9480ASUZ-250 Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference REFERENCE Internal Reference Voltage Output Current2 IVREF Input Current3 ISENSE Input Current2 ANALOG INPUTS (VIN+, VIN-) Differential Input Voltage Range (FS = 1) 4 Common-Mode Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD Power Dissipation5 Power-Down Dissipation IAVDD5 IDRVDD5 Power Supply Rejection Ratio (PSRR) Temp Test Level Min AD9480-250 Typ 8 Guaranteed -40 -6.0 -0.5 -0.85 -0.9 0.28 0.35 0.26 30 0.03 .025 0.97 1.0 1.03 1.5 100 10 40 6.0 0.5 0.85 0.9 mV % FS LSB LSB LSB uV/C %FS/C mV/C V mA uA uA Vpp V k k pF MHz V V mW mW mA mA mV/V Max Unit Bits
Full 25C 25C Full Full Full Full Full Full Full 25C 25C 25C Full Full 25C Full 25C 25C Full Full 25C 25C Full Full 25C
VI I I VI VI VI V V V VI IV I I V VI I VI V V IV IV V V VI VI V
1.7 8.6 8.4
1 1.9 10 10 4 750 3.3 3.3 590 15 145 34 -4.2
2.1 10.7 11.2
3.0 3.0
3.6 3.6
156 38
1 2 3
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and a 1 V p-p differential analog input). Internal reference mode; SENSE = AGND. External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD. 4 In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other. 5 Power dissipation and current measured with rated encode and a dc analog input (outputs static). See Figure 29 for active operation.
Rev. 0 | Page 3 of 28
AD9480
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = -40C, TMAX = +85C, AIN = -1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 2.
Parameter CLOCK INPUTS (CLK+, CLK-) Differential Input Common-Mode Voltage1 Input Resistance Input Capacitance LOGIC INPUTS (PDWN, S1) Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current Logic 0 input Current Input Resistance Input Capacitance DIGITAL OUTPUTS Differential Output Voltage (VOD)2 Output Offset Voltage (VOS) Output Coding Temp Full Full Full 25C Full Full Full Full 25C 25C Full Full Full Test Level IV VI VI V IV IV VI VI V V VI VI IV Min 200 1.4 4.2 AD9480-250 Typ Max Unit mVpp V k pF V V uA uA k pF mV V
1.5 5.5 4
1.68 6.0
2.0 0.8 160 10 30 4 247 1.125 454 1.375 Twos complement or binary
1 2
The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK < 2.6 V. LVDSBIAS resistor = 3.74 k.
Rev. 0 | Page 4 of 28
AD9480
AC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = -40C, TMAX = +85C, AIN = -1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 3.
Parameter SIGNAL TO NOISE RATIO (SNR) fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz SIGNAL TO NOISE AND DISTORTION (SINAD) fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz WORST SECOND OR THIRD HARMONIC DISTORTION fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz WORST OTHER fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR)1 fIN = 19.7 MHz fIN = 70.1 MHz fIN = 170 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fIN1 = 69.3 MHz, fIN 2 = 70.3 MHz Temp 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Test Level V I I V I I V I I V I I V I I V I I V Min AD9480-250 Typ 47 47 46 46.5 46.5 46.5 7.5 7.5 7.5 -65 -65 -65 -70 -70 -70 -65 -65 -65 -68 Max Unit dB dB dB dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
45 45
44.8 44.8
7.2 7.2
-60 -60
-63 -63
-60 -60
1
Nyquist bin energy ignored.
Rev. 0 | Page 5 of 28
AD9480
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, unless otherwise noted. Table 4.
Parameter CLOCK Maximum Conversion Rate Minimum Conversion Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS Valid Time (tV)1 Propagation Delay (tPD)1 Rise Time (tR) 20% to 80% Fall Time (tF) 20% to 80% DCO Propagation Delay (tCPD) Data-to-DCO Skew (tPD - tCPD) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Temp Full Full Full Full Full Full Full Full Full Full 25C 25C 25C Test Level VI VI IV IV VI VI V V VI IV VI V V Min 250 20 1.2 1.2 1.9 2.8 0.5 0.5 2.7 0.1 8 1.5 0.25 3.8 2 2 AD9480-250 Typ Max Unit MSPS MSPS ns ns ns ns ns ns ns ns Cycles ns ps rms
1.9 0
3.7 0.6
1
Valid Time is approximately equal to minimum tPD. CLoad equals 5 pF maximum.
TIMING DIAGRAM
N-1 N N+9 AIN N+1 8 CYCLES N+8
tA
N+10
N+11
tEH
CLK+ CLK-
tEL
1/fS
tPD
DATA OUT N-8
tV
N-7 N N+1 N+2
tCPD
DCO+ DCO-
04619-0-002
Figure 2. Timing Diagram
Rev. 0 | Page 6 of 28
AD9480
ABSOLUTE MAXIMUM RATINGS
Thermal impedance (ja) = 46.4 C/W (4-layer PCB) Table 5.
Parameter ELECTRICAL AVDD (With respect to AGND) DRVDD (With respect to DRGND) AGND (With respect to DRGND) Digital I/O (With respect to DRGND) Analog Inputs (With respect to AGND) ENVIRONMENTAL Operating Temperature Junction Temperature Case Temperature Storage Temperature Min Rating -0.5 V -0.5 V -0.5 V -0.5 V -0.5 V Max Rating 4.0 V 4.0 V 0.5 V DRVDD + 0.5 V AVDD + 0.5 V
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
-40C
85C 150C 150C 150C
EXPLANATION OF TEST LEVELS
Table 6.
Level I II Description 100% production tested. 100% production tested at 25C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C and guaranteed by design and characterization for industrial temperature range.
III IV V VI
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD9480
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LVDSBIAS AGND AGND AGND AGND AVDD AVDD
44 43 42 41 40 39 38 37 36 35 34
CLK+ 1 CLK- 2 AVDD 3 AGND 4 DRVDD 5 DRGND
6 PIN 1
VREF
33 32 31
VIN+
VIN-
NC
SENSE AGND AVDD AGND PDWN S1 DRGND D7_T (MSB) D7_C (MSB) D6_T D6_C
04619-0-003
AD9480
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23
D0_C (LSB) 7 D0_T (LSB) 8 D1_C 9 D1_T 10 D2_C 11 NC = NO CONNECT
12 13 14 15 16 17 18 19 20 21 22
D3_C
D4_C
D5_C
D2_T
D3_T
D4_T
DCO+
DCO-
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Name CLK+ CLK- AVDD AGND DRVDD DrGND D0_C D0_T D1_C D1_T D2_C D2_T D3_C D3_T DRGND DCO- DCO+ DRVDD D4_C D4_T D5_C D5_T Description Input Clock--True Input Clock--Complement 3.3 V Analog Supply Analog Ground 3.3 V Digital Output Supply Digital Ground Data Ouput Bit 0--Complement (LSB) Data Output Bit 0--True (LSB) Data Output Bit 1--Complement Data Output Bit 1--True Data Output Bit 2--Complement Data Output Bit 2--True Data Output Bit 3--Complement Data Output Bit 3--True Digital Ground Data Clock Output--Complement Data Clock Output--True 3.3 V Digital Output Supply Data Output Bit 4--Complement Data Output Bit 4--True Data Output Bit 5--Complement Data Output Bit 5--True Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name D6_C D6_T D7_C D7_T DrGND S1 PDWN AGND AVDD AGND SENSE VREF AGND AVDD AGND VIN- VIN+ AGND AVDD LVDSBIAS AVDD AGND Description Data Output Bit 6--Complement Data Output Bit 6--True Data Output Bit 7--Complement (MSB) Data Output Bit 7--True (MSB) Digital Ground Data Format Select and Duty Cycle Stabilizer Selection. See . Power-Down Selection Analog Ground 3.3 V Analog Supply Analog Ground Reference Mode Selection. See Table 9. Voltage Reference Input/Output Analog Ground 3.3 V Analog Supply Analog Ground Analog Input--Complement Analog Input--True Analog Ground 3.3 V Analog Supply LVDS Output Current Adjust 3.3 V Analog Supply Analog Ground
Rev. 0 | Page 8 of 28
DRGND
DRVDD
D5_T
AD9480
DEFINITIONS
Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance; pulse width low is the minimum time clock pulse should be left in a low state. See timing implications of changing tEH in the section Clocking the AD9480. At a given clock rate, these specifications define an acceptable clock duty cycle. Crosstalk Coupling onto one channel being driven by a low level (-40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. Peak to peak differential is computed by rotating the inputs phase 180 and taking the peak measurement again. Then the difference is computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits The effective number of bits (ENOB) is calculated from the measured SINAD based on the equation (assuming full-scale input) Full-Scale Input Power Expressed in dBm. Computed using the following equation:
V 2 FULLSCALE rms Z INPUT PowerFULLSCALE = 10 log 0.001

Gain Error Gain error is the difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK- and the time when all output data bits are within valid logic levels. Noise (for any range within the ADC) This value includes both thermal and quantization noise.
FS - SNRdBc - SignaldBFS Vnoise = Z x .001 x 10 dBm 10

where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in dB below full scale.
Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage.
ENOB =
SINADMEASURED - 1.76 dB 6.02
Rev. 0 | Page 9 of 28
AD9480
Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (that is, degrades as signal level is lowered) or dBFS (that is, always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (that is, always relates back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dBc. Transient Response Time Transient response time is defined as the time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time Out of range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Rev. 0 | Page 10 of 28
AD9480
EQUIVALENT CIRCUITS
AVDD
AVDD
16.7k
16.7k
150 VIN+ 25k 1.2pF 25k
150 VIN- 1.2pF
04619-0-004
PDWN 30k
Figure 4. Analog Inputs
Figure 7. Power-Down Input
AVDD
DRVDD
DRVDD
12k CLK+ 150
12k CLK- 150
1.2V
K
10k
10k
3.7k
Figure 5. Clock Inputs
04619-0-005
Figure 8. LVDSBIAS Input
VDD
DRVDD
30k
V+ V- DX+ V+
04619-0-009
S1
DX-
04619-0-006
V-
Figure 6. S1 Input
Figure 9. LVDS Data, DCO Outputs
Rev. 0 | Page 11 of 28
04619-0-008
LVDSBIAS
ILVDSOUT
04619-0-007
AD9480
APPLICATION NOTES
The AD9480 uses a 1.5 bit per stage architecture. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 8-bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are LVDS (ANSI 644 compatible).
ANALOG INPUTS
The analog input to the AD9480 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN- should match. Optimal performance is obtained when the analog inputs are driven differentially. SNR and SINAD performance can degrade if the analog input is driven with a single-ended signal. The analog inputs self-bias to approximately 1.9 V; this common-mode voltage can be externally overdriven by approximately 300 mV if required. A wideband transformer, such as the Minicircuits ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Note that the filter and center-tap capacitor on the secondary side is optional and dependent on application requirements. An RC filter at the secondary side helps reduce any wideband noise getting aliased by the ADC.
(R, C OPTIONAL) 33 49.9 10pF 33 AVDD VIN+
CLOCKING THE AD9480
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Considerable care has been taken in the design of the CLOCK input of the AD9480, and the user is advised to give commensurate thought to the clock source. The AD9480 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLOCK and optimizes timing internally for sample rates between 100 MSPS and 250 MSPS. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 70 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically, requiring a wait time of 5 s after a dynamic clock frequency increase before valid data is available. The clock duty cycle stabilizer can be disabled at Pin 28 (S1). The clock inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. An MC100LVEL16 performs well in the circuit to drive the clock inputs (ac coupling is optional). If the clock buffer is greater than 2 inches from the ADC, a standard LVPECL termination may be required instead of the simple pull-down termination shown in Figure 10.
0.1F PECL GATE CLK- 0.1F 510k 510k
04619-0-010
AD9480
VIN-
04619-0-011
AGND 0.1F
Figure 11. Driving the ADC with an RF Transformer
For dc-coupled applications, the AD8138 or AD8351 can serve as a convenient ADC driver, depending on requirements. Figure 12 shows an example with the AD8138. The AD9480 PCB has an optional AD8351 on board, as shown in Figure 41 and Figure 42. The AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz.
49.9 499 499 1.3k 33 AVDD VIN+
AD8138
523
20pF 33
AD9480
VIN- AGND
04619-0-012
AD9480
CLK+
0.1F 2k
499
Figure 12. Driving the ADC with the AD8138
Figure 10. Clocking the AD9480
Table 8. S1 Voltage Levels
S1 Voltage 0.9*AVDD- > AVDD 2/3 AVDD (0.1*AVDD) 1/3 AVDD (0.1*AVDD) AGND- >(0.1*AVDD) Data Format Offset binary Offset binary Twos complement Twos complement Duty Cycle Stabilizer Disabled Enabled Enabled Disabled
Rev. 0 | Page 12 of 28
AD9480
The AD9480 can be easily configured for different full-scale ranges. See the Voltage Reference section for more information. Optimal performance is achieved with a 1 V p-p analog input.
SENSE = GND
Fixed Reference
The internal reference can be configured for a differential span of 1 V p-p (see Figure 17). It is recommended to place a 0.1uF capacitor as close as possible to the VREF pin; a 10 uF capacitor is also required (see the PCB layout for guidance). If the internal reference of the AD9480 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 17 depicts how the internal reference voltage is affected by loading.
1.0085 1.0080
VIN+
500mV 2.0V
2.0V
VIN-
1.0075
DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s
04619-0-013
1.0070
VREF (V)
1.0065 1.0060 1.0055 1.0050 1.0045 1.0040 1.0035 -40 -20 0 20 40 TEMPERATURE (C) 60 80
04619-0-049
Figure 13. Analog Input Full Scale
VOLTAGE REFERENCE
A stable and accurate 1.0 V reference is built into the AD9480. Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. Figure 15 shows the typical reference variation with temperature. Table 9 summarizes the available reference configurations.
VIN+ VIN-
Figure 15. Typical Reference Variation with Temperature
VREF
ADC CORE
10F
0.1F
04619-0-016
SENSE
VREF 10F +
Figure 16. Internal Fixed Reference (1 V p-p)
0.1F 7k SELECT LOGIC
0
% CHANGE IN VREF VOLTAGE
SENSE
-0.1
04619-0-014
7k
0.5V
-0.2
-0.3
Figure 14. Internal Reference Equivalent Circuit
-0.4
04619-0-017
-0.5 0 0.5 1.0 1.5 IREF (mA) 2.0 2.5
3.0
Figure 17. Internal VREF vs. Load Current
Table 9. Reference Configurations
SENSE Voltage AVDD 0.5 V (Self Biased) AGND to 0.2 V Resulting VREF N/A (external reference input) 0.5 x (1 + R1/R2) V 1.0 V Reference External Programmable Internal fixed Differential Span 1 x external reference voltage 1 x VREF (0.75 V p-p to 1.5 V p-p) 1 V p-p
Rev. 0 | Page 13 of 28
AD9480
External Reference
An external reference can be used for greater accuracy and temperature stability when required. The gain of the AD9480 can also be varied using this configuration. A voltage output DAC can be used to set VREF, providing for a means to digitally adjust the full-scale voltage. VREF can be externally set to voltages from .75 V to 1.5 V; optimum performance is typically obtained at VREF = 1 V. (See the Typical Performance Characteristics section.)
MAY REQUIRE RC FILTER EXTERNAL REFERENCE OR DAC INPUT AVDD SENSE
04619-0-018
OUTPUT CODING
Table 10.
Code 255 255 254 * * 129 128 127 * * 2 1 0 0 (VIN+) - (VIN-) > 0.512 V 0.512 V 0.508 V * * 0.004 V 0.0 V -0.004 V * * -0.504 V -0.508 V -0.512 V < -0.512 V Offset Binary 1111 1111 1111 1111 1111 1110 * * 1000 0001 1000 0000 0111 1111 * * 0000 0010 0000 0001 0000 0000 0000 0000 Twos Complement 0111 1111 0111 1111 0111 1110 * * 0000 0001 0000 0000 1111 1111 * * 1000 0010 1000 0001 1000 0000 1000 0000
VREF
Figure 18. External Reference
Programmable Reference
The programmable reference can be used to set a differential input span anywhere between 0.75 V p-p and 1.5 V p-p by using an external resistor divider. The sense pin will self-bias to 0.5 V, and the resulting VREF is equal to 0.5 x (1 + R1/R2). It is recommended to keep the sum of R1+R2 10 k to limit VREF loading (for VREF=1.5 V, set R1 equal to 7 k and R2 equal to 3.5 k).
INTERLEAVING TWO AD9480s
Instrumentation applications may prefer to interleave, or ping-pong, two AD9480s to achieve twice the sample rate, or 500 MSPS. In these applications, it is important to match the gain and offset of the two ADCs. Varying the reference voltage allows the gain of the ADCs to be adjusted; external dc offset compensation can be used to reduce offset mismatch between two ADCs. The sampling phase offset between the two ADCs is extremely important as well, and requires very low skew between clock signals driving the ADCs (< 2 pS clock skew for a 100 MHz analog input frequency).
VREF 10F 0.1F R1
04619-0-019
SENSE R2
DATA CLOCK OUT
An LVDS data clock is available at DCO+ and DCO-. These clocks can facilitate latching off-chip, providing a low skew clocking solution. The on-chip delay of the DCO clocks tracks with the on chip delay of the data bits, (under similar loading) such that the variation between Tpd and Tcpd is minimized. It is recommended to keep the trace lengths on the data and DCO pins matched and to 3 to 4 inches maximum. The output and DCO outputs should be designed for a differential characteristic impedance of 100 , and terminated differentially at the receiver with 100 .
Figure 19. Programmable Reference
DIGITAL OUTPUTS
LVDS outputs are available when a 3.7 k RSET resistor is placed at Pin 42 (LVDSBIAS) to ground. The RSET resistor current (~ 1.2 V/RSET) is ratioed on-chip setting the output current at each output equal to a nominal 3.5 mA with an RSET of 3.74 k. Varying the RSET current also linearly changes the LVDS output current, resulting in a variable output swing for a fixed termination resistance. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor as close to the receiver as possible. Keep the trace length 3 to 4 inches maximum and the differential output trace lengths as equal as possible.
Rev. 0 | Page 14 of 28
AD9480
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, DRVDD=3.3V, T = 25C, AIN differential drive, FS = 1, unless otherwise noted.
0 -10 -20 -30 -40 -50 -60 -70
04619-0-020
0
SNR = 46.2dB H2 = 72.8dBc H3 = 73.2dBc SFDR = 69.8dBc
-10 -20 -30 -40 -50 -60 -70 -80 -90 0
SNR = 45.9dB H2 = 71.9dBc H3 = 67dBc SFDR = 67dBc
dB
dB
-80 -90 0 20 40 60 MHz 80 100 120
20
40
60 MHz
80
100
120
Figure 20. FFT: fS = 250 MSPS, AIN = 10.3 MHz @ -1 dBFS
Figure 23. FFT: fS = 250 MSPS, AIN =170 MHz @ -1 dBFS
0 -10 -20 -30 SNR = 46.1dB H2 = 71.4dBc H3 = 74.3dBc SFDR = 68.7dBc
90 85 H3 80 75 70
dB
dB
-40 -50
65 60
SFDR
H2
-60 -70
04619-0-021
55 50 45 40 0 50 100 150 200 250 AIN (MHz) SNR SINAD 300 350
04619-0-024
-80 -90 0 20 40 60 MHz 80 100 120
400
Figure 21. FFT: fS = 250 MSPS, AIN = 70 MHz @ -1 dBFS
Figure 24. Analog Input Frequency Sweep, AIN = -1dBFS, FS=1V, fS = 250 MSPS
80
0 -10 -20 -30 SNR = 45.9dB H2 = 67dBc H3 = 73.3dBc SFDR = 67dBc
H3 75 H2 70 65
dB
-40
SFDR
dB
60 55 50
-50 -60 -70
04619-0-022
-80 -90 0 20 40 60 MHz 80 100 120
45 40 0 50 100 150 200 250 AIN (MHz) 300
SNR SINAD 350
400
Figure 22. FFT: fS = 250 MSPS, AIN = 70, MHz @ -1 dBFS, Single-Ended Input
Figure 25. Analog Input Frequency Sweep, AIN =-1 dBFS, FS =.75 V, fS = 250 MSPS
Rev. 0 | Page 15 of 28
04619-0-025
04619-0-023
AD9480
75 180 160 140 65 SFDR 60 70
CURRENT IN mA
120 IAVDD 100 80 60 40 IDRVDD
04619-0-029
dB
55 50 SNR 45 40 0 50 100 150 200 SAMPLE CLOCK (MHz) 250
04619-0-026
SINAD
20 0 0 50 100 150 200 ENCODE (MSPS) 250
300
300
Figure 26. SNR, SINAD, SFDR vs. Sample Clock Frequency, AIN = 70 MHz -1 dBFS
Figure 29. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF AIN = 70 MHz @ -1 dBFS
80 70 SFDRdBFS 60
50 49 48 DCS ON 47
50
46
dB
40 30 20 10 0 -70 65dB REF LINE -60 -50 -40 -30 -20 -10 ANALOG INPUT DRIVE LEVEL (dBFS) 0
04619-0-027
dB
45 44 43
046190-0-030
DCS OFF
SFDRdBc
42 41 40 20 30 40 50 60 70 CLOCK POSITIVE DUTY CYCLE (%)
80
Figure 27. SFDR vs. AIN Input Level; AIN = 70 MHz at 250 MSPS
Figure 30. SNR, SINAD vs. Clock Pulse Width High, AIN = 70 MHz @ -1 dBFS, 250 MSPS, DCS On/Off
50.0 80 SNR
0 -10 -20 F1, F2 = -7dBFS 2F2-F1 = -71.1dBc 2F1-F2 = -68dBc
47.5
75 SINAD
SNR, SINAD dB
-30 -40 -50 -60 -70 -80 -90 0 20 40 60 MHz 80 100 120
04619-0-028
45.0
70
SFDR 42.5 65
04619-0-031
40.0 0.5
0.7
0.9 1.1 1.3 1.5 1.7 EXTERNAL VREF VOLTAGE (V)
1.9
50
Figure 28. Two-Tone Intermodulation Distortion (69.3 MHz and 70.3 MHz; fS = 250 MSPS)
Figure 31. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, AIN = 70 MHz @ -1 dBFS, 250 MSPS
Rev. 0 | Page 16 of 28
SFDR dB
dB
AD9480
3 FS = 1V EXT REF 2 65 SFDR 70
GAIN ERROR (%)
1 60 0 FS = 1V INT REF
dB
55
-1 50
04619-0-032
SNR
04619-0-035
-2
-3 -40
-20
0
20 40 TEMPERATURE (C)
60
80
45 SINAD 3.0 3.1
3.2
3.3 AVDD (V)
3.4
3.5
3.6
Figure 32. Full-Scale Gain Error vs. Temperature, AIN = 70.3 MHz @ -0.5 dBFS, 250 MSPS, FS=1
Figure 35. SNR, SINAD, and SFDR vs. Supply Voltage, AIN = 70.3 MHz @ -1 dBFS, 250 MSPS,
75 SFDR 1V INT REF
0.5 0.4
70 0.3 65 60 0.2 0.1
LSB
dB
0 -0.1 -0.2
55 50 SINAD 1V INT REF 45 40 -40
04619-0-033
-0.3 -0.4 -0.5 0 50 100 CODE 150 200 250
04619-0-036
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 33. SINAD, SFDR vs. Temperature, AIN = 70 MHz @ -1 dBFS, 250 MSPS
Figure 36. Typical DNL Plot, AIN = 10.3 MHz @ -0.5 dBFS, 250 MSPS
0.50 0.10
0.05
0.25
CHANGE IN VREF (%)
LSB
0
0
-0.05 -0.25
04619-0-037
-0.10
04619-0-034
-0.50 0 50 100 CODE 150 200 250
-0.15 2.7
2.8
2.9
3.0
3.1 3.2 AVDD (V)
3.3
3.4
3.5
3.6
Figure 34. VREF Sensitivity to AVDD
Figure 37. Typical INL Plot, AIN = 10.3 MHz @ -0.5 dBFS, 250 MSPS
Rev. 0 | Page 17 of 28
AD9480
0.30 0.25
DELAY SENSITIVITY (nS)
0.20 0.15 0.10 0.05 0 -0.05 -0.10 -40
04619-0-038
-20
0
20 40 TEMPERATURE (C)
60
80
Figure 38. Propagation Delay Adder vs. Temperature
900 800 VOS 700 600
1.4 1.3 1.2 1.1 1.0 0.9 VOD 0.8 0.7 0.6
04619-0-039
VDIF (mV)
500 400 300 200 100 0 0 2 4 6 8 10 12 14 RSET (k)
0.5
Figure 39. LVDS Output Swing, Common-Mode Voltage vs. RSET, Placed at LVDSBIAS
Rev. 0 | Page 18 of 28
VOS (V)
AD9480
AD9480 EVALUATION BOARD
The AD9480 evaluation board offers an easy way to test the device. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC and a data-ready signal. The digital outputs and output clocks are available at a 40-pin connector, P10. The board has several different modes of operation and is shipped in the following configuration: * Offset binary * Internal voltage reference
CLOCK
The clock input is terminated to ground through 50 at SMA Connector J1. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter, fast edge rates needed for best performance. J1 input should be > 0.5 V p-p. Power to the LVEL16 is set to VCTRL (default) or AVDD by jumper placement at the device.
OPTIONAL CLOCK BUFFER
The PCB has been designed to accommodate the SNLVDS1 line driver. The SNLVDS1 is used as a high speed LVDS-level optional encode clock. To use this clock, please remove C2, C5, and C6. Place a 0.1 uF capacitor on C34, C35, and C26. Place a 10 resistor on R48 and place a 100 resistor on R6. Place R49 and R53 with a 0 resistor. For best results using the LVDS line driver, J1 input should be >2.5 V p-p.
POWER CONNECTOR
Power is supplied to the board via 2 detachable 4-pin power strips.
Table 11. Power Connector
Terminal AVDD1 3.3 V DRVDD1 3.3 V VCTRL1 3.3 V Op amp, ext. ref
1 2
Comments Analog supply for ADC ~ 150 mA Output supply for ADC ~ 40 mA Supply for support clock circuitry ~ 50 mA Optional supply for op amp and ADR510 reference
OPTIONAL XTAL
The PCB has been designed to accommodate an optional crystal oscillator which can serve as a convenient clock source. The footprint can accept both through-hole and surface-mount devices, including Vectron XO-400 and Vectron VCC6 family oscillators.
AVDD, DRVDD, and VCTRL are the minimum required power connections. LVEL16 clock buffer can be powered from AVDD or VCTRL LVEL16 buffer jumper.
ANALOG INPUTS
The evaluation board accepts a 700 mV p-p analog input signal centered at ground at SMB Connector J3. This signal is terminated to ground through 50 by R22. The input can be alternatively terminated at the T1 transformer secondary by R21 and R28. T1 is a wideband RF transformer providing the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. An optional transformer, T4, can be placed if desired (remove T1, as shown in Figure 41 and Figure 42). The analog signal can be low-pass filtered by R31, C8, and R29, C9 at the ADC input.
VCC
OUT+
OUT- GND VCC
04619-0-040
GAIN
Full scale is set by the sense jumper. This jumper applies a bias to the sense pin to vary the full-scale range; the default position is sense = ground, setting the full scale to 1 V p-p.
Figure 40. XTAL Footprint
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional AD8351 op amp which can serve as a convenient solution for dc-coupled applications. To use the AD8351 op amp, remove R29, R31, and C3. Populate R40, R43, and R47 with 25 resistors, and populate C24, C28, C29, C30, C31, and C32 with 0.1 uF capacitors. Populate R38, R39, and R51 with a 10 resistor, and R44 and R45 with a 1 k resistor. Populate R41 with a 1.2 k resistor and R42 with a 100 resistor. Populate R52 with a 10 k resistor.
To use either crystal, populate C26 and C27 with 0.1 uF capacitors. Populate R49 and R53 with 0 resistors. Place R54, R55, R56, and R57 with 1 k resistors. Remove C6 and C5. If the Vectron VCC6 family crystal is being used, populate R48 with a 10 resistor. If using the XO-400 crystal, place jumper E21 or E22 to E23.
Rev. 0 | Page 19 of 28
AD9480
VOLTAGE REFERENCE
The AD9480 has an internal 1 V reference mode. The ADC uses the internal 1 V reference as the default when sense is set to ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the sense jumper to AVDD, by placing a jumper on E20 to E3, and by placing a 0 resistor on R36. When using an external programmable reference, (R20, R30) remove the sense jumper.
DATA OUTPUTS
The off-chip drivers provide LVDS compatible output levels with an LVDS RSET resistor of 3.74 k. The ADC digital outputs can be terminated on the board by 100 resistors at the connector if receiving logic does not have the required termination resistance. (The on-chip LVDS output drivers require a far-end 100 differential termination.)
Rev. 0 | Page 20 of 28
AD9480
EVALUATION BOARD BILL OF MATERIALS
Table 12.
No. 1 Quantity 23 Reference Designator C1, C2, C3, C4, C5, C6, C10, C11, C12, C17, C18, C19, C20, C21, C22, C23, C26, C27, C28, C31, C32, C33, C35 C13 C7, C14, C15, C16 J1, J3 P12, P13 P12, P13 R22, R27 R2, R3, R4, R5, R7, R8, R9, R10, and R15 (Not placed) R42 R1, R44, R45, R50, R58, R59 R41 R40, R43, R47 R38, R39, R51 R25, R26 R23, R24 R32, R34 R29, R31 R33, R52 R63 T1 U13 U2 U14 U15 U1 U12 U11 T2 C8, C9, C24, C25, C29, C30, and C34 (All not placed) R6, R20, R21, R28, R30, R36, R46, R48, R49, R51, R55, R56, and R57 (All not placed) E73, E74, E75, E76, E77, E78, E79, E80, E81, E82, E83, E84, E17, E5, E6, E7, E8, E35 Device Capacitor Package 0402 Value 0.1 uF
2 3 4 5 6 7 8
1 4 2 2 2 2 8
Capacitor Capacitor SMA 4-pin power connector post 4-pin power detachable connector Resistor Resistor
Tant (3528) Tant (6032) Z5.531.3425.0 25.602.5453.0 0603 0603
10 uF 10 uF Wieland Wieland 50 100
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
6 1 3 2 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 11 20
Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Transformer AD8351 SN65LVDS1 ADR510 VCC6PECL6 XO-400 AD9480 MC100LVEL16D ETC1-1-13 Capacitor Resistor
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 CD542 MSOP-10 SN65LVDS1 DBV SOT-23 VCC6-QAB-250M000 Dip4(14) TQFP-44 S08NB 1-1 TX 0402 0603
1000 1200 25 10 130 510 82 zero 10 k 3.74 k Minicircuits T1-1WT Not placed Not placed Not placed Not placed
Not placed Not placed User-determined
30
16
Jumper
Rev. 0 | Page 21 of 28
AD9480
POWER CONN. P13 P12 PTMICRO4 PTMICRO4
P1 P2 P3 P4 P1 P2 P3 P4
EXTVREF
1 2
4 3 2 1 4 3 2 1
V+ V- TRIM/NC
3
R33 10k
GND
VCTRL GND VAMP GND DRVDD GND AVDD GND
ADR510
U14 VCTRL GND E2 E1
GND AVDD GND PWDN S1
VAMP GND E13 E15 R2 100 D7C
GND
E20 E14 E16 R30 XX D6T R3 100 D6C D5T R4 100 D5C
34 35 36 37 38 39 17 16 15 14 13 12 19 18
E3 R20 XX D7T
PCB SCHEMATICS
R36 X
FOR ON BOARD EXT. REF JUMPER E13 TO 14 AND E20 TO E3 PLACE R36 0 AND R33 10k
C1 0.1F C13 + 10F C12 0.1F
33 32 31 30 29 28 27 26 25 24 23
GND
SENSE AGND AVDD AGND PWDN S1 DRGND D7T D7C D6T D6C
GND
GND
D5T 22 21 D5C D4T 20 R5 100 DRVDD R15 100
D4T OUTPUT DATA CONN. D4C DR+
E17
GND AVDD GND
R36 1k OPTIONAL VCTRL
41 42 43 44
E7
40
AD9480
GND
40 38
39 37
R63 GND 3.7k AVDD GND GND
DR- D3T R7 100 D3C D2T R10 100
36 34 32 30 28 26 24 22 20
35 33 31 29 27 25 23 21 19
OPTIONAL TRANSFORMER T1+ CM U 12
1 2 3 4 56 7 8
TIN1 C8 X
CLK+ CLK- AVDD AGND DRVDD DRGND D0C D0T D1C D1T D2C
6
1
AMPOUT AMPOUT C9 X GND R31 00 R28 X GND FOR OP AMP CONFIGURATION REMOVE RESISTORS R29, R31, AND C3 C10 0.1F
VREF AGND AVDD AGND VIN- VIN+ AGND AVDD LVDSBIAS NC AGND D4C DRVDD DCO+ DCO- DRGND D3T D3C D2T
CM T1- T1-
6 5 4 3 2 1
5
2
ANALOG INPUT R29 00
AVDD GND DRVDD GND
Figure 41. PCB Schematic (1 of 2)
GND
Rev. 0 | Page 22 of 28
9 10 11
GND
4
3
GND DR+ GND D7C D6C D5C D4C D3C D2C D1C D0C D2C D1T R9 100 D1C D0T R8 100 D0C GND
GND DR- GND D7T D6T D5T D4T D3T D2T D1T D0T
18 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1
GND CM R21 X T1+
E8
R22 50 J3
CM
C10 AMPIN 0.1F GND
P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2
P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 C40MS P10 PROBE POINTS
GND
AVDD E10 GND E11
2 100LVEL16 3 6 1 8
E9 R34 82 VCTRL C6 0.1F E17
C11 0.1F VCTRL
VCTRL R VCC 7 CLK Q R26 130 R25 130 GND C4 0.1F GND R32 82 CLKN Q VBB VEE
5
CLK+
CLK- PADS FOR SHORTING EL16, P14 P15
J1
CLKINPUT
CLK
GND R24 4 510 U11 GND
C11 0.1F
E17 C5 0.1F
R6 X
CLK P16 CLKN P6 E35 P7 C33 0.1F GND P17
D+ D-
GND GND GND GND GND GND GND GND
E77 E78 E79 E81 E80 E82 E83 E84
R27 R23 50 510
GND
04619-0-041
AVDD AVDD GND VCTRL
E4 E70 E12 E32
VCTRL AVDD VCC D 4 GND Z SN65LVDS1 OPTIONAL OUT+ P4 P3VAMP R38 VAMPF AVDD C7 + 10F C17 0.1F C18 0.1F GND C19 0.1F C20 0.1F C35 0.1F X C32 0.1F C16 + 10F S1 GND VIVIS OUT+ Y GND 3 2 1 5
E24
E25
U2
PWDN
C34
CLKINPUT
X
VCTRL
E26
E28
R59 1k
E36
E34
R58 1k
E27
E29
R50 1k
E30
E31
GND DRVDD X= NOT NORMALLY POPULATED XX = USER SELECTED, IS NOT NORMALLY POPULATED GND C14 + 10F C21 0.1F C22 0.1F VCTRL C15 + 10F GND C23 0.1F
OPTIONAL OPTIONAL XTALS C28 0.1F GND VAMPF U13 AD8351 10 9 8 VAMPF R46 X 7 6 GND C29 X COMM OPLO VPOS OPHI VOCM C24 X AMPOUT GND C25 X AMPOUT VCTRL R48 X R41 X GND R44 X R45 X GND AVDD VCTRL E22 E23 E21 C27 X 14 7 GND GND VCTRL C23 X VCC 6 PECL6 1 2 3 R55 X 6 OUT- 5 4 OUT+ R54 X VCTRL R57 X GND GND R56X R49 X CLK- CLK+ R53 X
Figure 42. PCB Schematic (2 of 2)
Rev. 0 | Page 23 of 28
3 4
VAMPF
U1 XO-400 VCC OUT VEE -OUT 8 1
R52 X
C30 X
PWUP 1 RGP1 2
AMPIN
INHI
R39 X
INLO
R40 X
C31 X
R51 X
RPG2 5
GND
R42 X
04619-0-042
AD9480
AD9480
PCB LAYERS
Figure 43. PCB Top-Side Silkscreen
04619-0-043
Figure 45. PCB Ground Layer
04619-0-044
Figure 44. PCB Top-Side Copper Routing
Figure 46. PCB Split Power Plane
Rev. 0 | Page 24 of 28
04619-0-046
04619-0-045
AD9480
Figure 47. PCB Bottom-Side Copper Routing
04619-0-047
Figure 48. PCB Bottom-Side Silkscreen
Rev. 0 | Page 25 of 28
04619-0-048
AD9480
OUTLINE DIMENSIONS
1.20 MAX 0.75 0.60 0.45
44 1 PIN 1
12.00 SQ
34 33
TOP VIEW
(PINS DOWN)
10.00 SQ
1.05 1.00 0.95
0 MIN
0.15 0.05
SEATING PLANE
0.20 0.09 VIEW A 7 3.5 0 0.08 MAX COPLANARITY
11 12 22
23
0.80 BSC
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026ACB
0.45 0.37 0.30
Figure 49. 44-Lead Thin Plastic Quad Flat Package [TQFP] (SU-44) Dimensions shown in millimeters
Rev. 0 | Page 26 of 28
AD9480
ORDERING GUIDE
Model AD9480BSUZ-2501, 2 AD9480ASUZ-2501 AD9480-LVDS/PCB3 Temperature Range -40C to +85C -40C to +85C Description TQFP TQFP Evaluation Board Package Option SU-44 SU-44
1 2
Z = Pb-free part. Optimized Differential Nonlinearity. 3 Evaluation Board shipped with AD9480BSUZ-250 installed.
Rev. 0 | Page 27 of 28
AD9480
NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04619-0-7/04(0)
Rev. 0 | Page 28 of 28

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