View FAN5069_407051.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FAN5069 PWM and LDO Controller Combo
October 2005
FAN5069 PWM and LDO Controller Combo
Features
General Purpose PWM Regulator and LDO Controller Input Voltage Range: 3V to 24V Output Voltage Range: 0.8V to 15V VCC - 5V - Shunt Regulator for 12V Operation Support for Ceramic Cap on PWM Output Programmable Current Limit for PWM Output Programmable Switching Frequency (200KHz to 600KHz) RDS(ON) Current Sensing Internal Synchronous Boot Diode Soft-Start for both PWM and LDO Multi-Fault Protection with Optional Auto-restart 16-pin TSSOP Package
Description
The FAN5069 combines a high efficiency PWM controller and a LDO (Low DropOut) linear regulator controller. Synchronous rectification provides high efficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET's RDS(ON) to sense current. Both the linear and PWM regulator soft-start are controlled by a single external capacitor, to limit in rush current from the supply when the regulators are first enabled. Current limit for PWM is also programmable. The PWM regulator employs a Summing-Current-Mode control with external compensation to achieve fast load transient response and provide system design optimization. FAN5069 is offered in both industrial temperature grade (-40C to +85C) as well as commercial temperature grade (-10C to +85C)
Applications
PC/Server Motherboard Peripherals - VCC_MCH (1.5V), VDDQ (1.5V) and VTT_GTL(1.25V) Power Supply for - FPGA, DSP, Embedded Controllers, Graphic Card Processor, and Communication Processors Industrial Power Supplies High Power DC-to-DC Converters
Ordering Information
Part Number Operating Temp. Range Pb-Free
FAN5069MTCX FAN5069EMTCX -10C to +85C -40C to +85C Yes Yes
Package
16-Lead TSSOP 16-Lead TSSOP
Packing Method
Tape and Reel Tape and Reel
Qty/Reel
2500 2500
Note: Contact Fairchild Sales for availability of other package options.
FAN5069 Rev. 1.1.0
(c)2005 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Typical Application
RVCC
+12V VCC
C9
3 TO 24V
15
FAN5069
+5V EN
C3
14 11
R(RAMP) BOOT
C5
R8
7 4 3 2 8
SS R4 R5 ILIM R(T) AGND PWM OUT Q3
Q1 HDRV SW Q2 13 12 LDRV PGND FB
C2
C4
C7
PWM
10 9
L1
PWM OUT C6
R1
GLDO FBLDO
16 1
6
LDO OUT
C8
R7 R6
ULDO CONTROL
5
C1
R2
COMP
R3
Figure 1. Typical Application Diagram
FAN5069 Rev. 1.1.0
2
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Pin Assignment
Top View
FBLDO R(T) ILIM SS COMP FB EN AGND 1 2 3 4 5 6 7 8 FAN5069 16 15 14 13 12 11 10 GLDO VCC R(RAMP) LDRV PGND BOOT HDRV
9 SW 16-Lead TSSOP
Figure 2. Pin Assignment
Pin Description
Pin No.
1 2 3 4
Pin Name
FBLDO R(T) ILIM SS
Pin Description
LDO Feedback. This node is regulated to VREF. Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased. Current Limit. A resistor from this pin to GND sets the current limit. Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the LDO during initialization. It also sets the time by which the converter will delay when restarting after a fault occurs. SS has to reach 1.2V before fault shut-down feature is enabled. The LDO is enabled when SS reaches 2.2V. COMP. The output of the error amplifier drives this pin. Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP pin, to compensate the feedback loop of the converter. Enable. Enables operation when pulled to logic high. Toggling EN will also reset the regulator after a latched fault condition. This is a CMOS input whose state is indeterminate if left open and hence needs to be properly biased at all times. Analog Ground. The signal ground for the IC. All internal control voltages are referred to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and drain of low-side MOSFET. High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET is turned off. Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect to bootstrap capacitor as shown in Figure 1. Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET. Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET is turned off. Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage feed-forward. VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic capacitor as close to this pin as possible. This pin has a shunt regulator which will draw current when the input voltage is above 5.6V. Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.
5 6 7
COMP FB EN
8 9 10
AGND SW HDRV
11 12 13
BOOT PGND LDRV
14 15
R(RAMP) VCC
16
GLDO
FAN5069 Rev. 1.1.0
3
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Absolute Maximum Ratings (Note1)
Parameter
VCC to PGND BOOT to PGND SW to PGND Continuous Transient (t < 50nS, F < 500kHz) HDRV (VBOOT--VSW) LDRV All Other Pins Maximum Shunt Current for VCC Electrostatic Discharge Protection (ESD) Level (Note 2) HBM CDM 2 0.4 -0.5 -0.3 -0.5 -3
Min.
Max.
6 33 33 33 6 6 VCC+0.3 150
Unit
V V V V V V V mA kV
Thermal Information
Parameter
Storage Temperature Lead Soldering Temperature, 10 Seconds Vapor Phase, 60 Second Infrared, 15 Seconds Power Dissipation (PD), TA = 25C Thermal Resistance- Junction to Case(JC) Thermal Resistance- Junction to Ambient (JA) (Note 3) 37 100
Min.
-65
Typ.
Max.
150 300 215 220 715
Unit
C C C C mW C/W C/W
Recommended Operating Conditions
Parameter
Supply Voltage (VCC) Ambient Temperature (TA) Junction Temperature (TJ)
Conditions
VCC to GND Commercial Industrial
Min.
4.5 -10 -40
Typ.
5
Max.
5.5 85 85 125
Unit
V C C C
Notes:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to AGND. 2. Using Mil Std. 883E, method 3015.7(Human Body Model) and EIA/JESD22C101-A (Charge Device Model). 3. Junction to ambient thermal resistance, JA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat sink characteristics.
FAN5069 Rev. 1.1.0
4
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Electrical Characteristics
Unless otherwise noted, VCC = 5V, TA = 25C, using circuit in Figure 1. The `*' denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Supply Current
IVCC IVCC(SD) IVCC(OP) VSHUNT
Parameter
VCC Current (Quiescent) VCC Current (Shutdown) VCC Current (Operating) VCC Voltage (Note 6)
Conditions
HDRV, LDRV Open EN = 0V, VCC = 5.5V EN = 5V, VCC = 5.0V Sinking 20mA to 100mA at VCC Pin
Min.
Typ.
3.2 200 10
Max.
3.8 400 15 5.9
Unit
mA A mA V
* *
2.6
5.5
UVLO
UVLO(H) UVLO(L) Rising VCC UVLO Threshold Falling VCC UVLO Threshold VCC UVLO Threshold Hysteresis
* *
4.0 3.6
4.25 3.75 0.5
4.5 4.0
V V V
Soft-Start
ISS VSSOK Current PWM Protection Enable threshold R(T) = 56K 1% R(T) = Open Frequency Range VRAMP Ramp Amplitude (Peak-toPeak) Minimum ON Time R(RAMP) = 330K F = 200kHz 10 2.2 1.2 A V V VLDOSTART LDO Start threshold
Oscillator
FOSC Frequency 240 160 160 0.4 200 300 200 360 240 600 KHz KHz KHz V nS.
Reference
VREF Reference Voltage (Measured TA = 0C to 70C at FB Pin) TA = -40C to 85C Current Amplifier Reference (at SW node)
* *
790 788
800 800 160
810 812
mV mV mV
Error Amplifier
DC Gain GBWP S/R Gain-BW Product Slew Rate Output Voltage Swing IFB FB Pin Source Current 10pF across COMP to GND No Load 80 25 8 dB MHz V/S. 4.0 1 V A
*
0.5
Gate Drive
RHUP RHDN RLUP RLDN HDRV Pull-up Resistor HDRV Pull-down Resistor LDRV Pull-up Resistor LDRV Pull-down Resistor Sourcing Sinking Sourcing Sinking
* * * *
1.8 1.8 1.8 1.2
3 3 3 2
FAN5069 Rev. 1.1.0
5
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Electrical Characteristics (Contd.)
Unless otherwise noted, VCC = 5V, TA = 25C, using circuit in Figure 1. The `*' denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
ILIM ISWPD VUV VOV
Parameter
ILIMIT Source Current SW Pull-down Current SW Pull-down Current Under-voltage Shutdown
Conditions
Min.
9
Typ.
10 10 75 115
Max.
11 80 120
Unit
A mA % %
Protection/Disable
SW = 1V, EN = 0V As % of set point. 2S noise filter As % of set point. 2S noise filter
* *
65 110
Supply Current
Thermal Shutdown Enable Threshold Voltage Enable Threshold Voltage Enable Source Current Enable Condition Disable Condition VCC = 5V 160 C V 0.8 50 V A
* *
2.0
LDO (See Note 7)
VLDOREF Reference Voltage (measured TA = 0C to 70C at FBLDO pin) TA = -40C to 85C Regulation VLDO_DO Drop-out Voltage External Gate Drive Gate Drive Source Current Gate Drive Sink Current
0A I LOAD 5A I LOAD 5Aand R DS - ON < 50m
* * * * *
775 770 1.17
800 800 1.2
825 830 1.23 0.3 4.5 5.3
mV mV V V V V mA A
VCC = 4.75V VCC = 5.6V
1.2 400
Notes:
4. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control. 5. AC specifications guaranteed by design/characterization (not production tested). 6. For a case when VCC is higher than the typical 5V VCC. Voltage observed at VCC pin when the internal shunt regulator is sinking current to keep voltage on VCC pin constant. 7. Test Conditions: VLDO_IN = 1.5V and VLDO_OUT = 1.2V
FAN5069 Rev. 1.1.0
6
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics
Figure 3. Dead Time Waveform
Figure 6. PWM Load Transient (0 to 15A)
Figure 4. PWM Load Transient (0 to 5A)
Figure 7. LDO Load Transient (0 to 2A)
Figure 5. PWM Load Transient (0 to 10A)
Figure 8. LDO Load Transient (0 to 5A)
FAN5069 Rev. 1.1.0
7
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Contd.)
Figure 9. PWM/LDO Power Up
Figure 12. Enable ON (IPWM = 5A)
Figure 10. PWM/LDO Power Down
Figure 13. Enable OFF (IPWM = 5A)
Figure 11. Auto Restart
FAN5069 Rev. 1.1.0
8
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Contd.)
PWM Line Regulation (VOUT = 1.5V)
1.54 IL = 0A IL = 5A
1.210
LDO Load Regulation (VOUT = 1.203V)
Output Voltage (V)
1.52
Output Voltage (V)
IL = 10A
1.205
1.50
1.200
1.48
1.195
VIN = 8V VIN = 12V VIN = 15V
1.46
VIN = 20V 1.190
6 8 10 12 14 16 18 20
0
1
2
3
4
5
Input Voltage (V)
Load Current (A)
Figure 14. PWM Line Regulation
LDO Line Regulation (VOUT = 1.203V)
1.210 IL = 0A IL = 2A IL = 5A 1.205
Figure 17. LDO Load Regulation
Master Clock Frequency
700
600
Output Voltage (V)
Frequency (kHz)
500
1.200
400
300
1.195
200
1.190 8 10 12 14 16 18 20
100 0 100 200 300 400
Input Voltage (V)
RT (K)
Figure 15. LDO Line Regulation
PWM Load Regulation (VOUT = 1.50V)
VIN = 8V VIN = 12V VIN = 15V
80
Figure 18. RT vs. Frequency
Efficiency vs. Input Voltage
1.510
100
Output Voltage (V)
1.505
VIN = 20V
VIN = 8V
Efficiency (%)
VIN = 12V 60 VIN = 15V VIN = 20V 40
1.500
1.495
20
0
1.490 0 2 4 6 8 10
2
4
6
8
10
Load Current (A)
Load Current (A)
Figure 16. PWM Load Regulation
Figure 19. 1.5V PWM Efficiency
FAN5069 Rev. 1.1.0
9
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Block Diagram
Vcc
Shunt Reg Internal Vcc 5.6V Max. Internal Boot Diode Current Limit Comparator
CBOOT
BOOT
10A
RILIM
ILIM
VIN
COMP FB Vref
Vcc Error Amplifier PWM Comparator
PWM
RQ S
HDRV
Adaptive Gate Drive Circuit
LO
Vout
CO
10A
OSC
SW
Current Sense Amplifier
SS
VIN
LDRV
RRAMP
Summing Ramp Generator
Amplifier Enable
R(RAMP) EN
PGND
Figure 20. Block Diagram
Detailed Operation Description
FAN5069 combines a high efficiency fixed-frequency PWM controller designed for single phase synchronous buck Point-OfLoad converters with an integrated LDO controller to support GTL type of loads. This controller is ideally suited to deliver low voltage, high current power supplies needed in desktop computers, notebooks, workstations and servers. The controller comes with an integrated boot diode which helps reduce component cost and increase space savings. With this controller, the input to the power supply can be varied from 3V to 24V and the output voltage can be set to regulate at 0.8V to 15V on the switcher output. The LDO output can be configured to regulate between 0.8V to 3V and the input to the LDO can be from 1.5V to 5V, respectively. An internal shunt regulator at the VCC pin facilitates the controller operation from either a 5V or 12V power source.
PWM Operation
Refer to Figure 20 for the PWM control mechanism. The FAN5069 uses the summing mode method of control to generate the PWM pulses. The amplified output of the current sense amplifier is summed with an internally generated ramp and the combined signal is amplified and compared with the output of the error amplifier to get the pulse width to drive the high-side MOSFET. The sensed current from the previous cycle is used to modulate the output of the summing block. The output of the summing block is also compared against the voltage threshold set by the RLIM resistor to limit the inductor current on a cycleby-cycle basis. The controller facilitates external compensation for enhanced flexibility.
VCC Bias Supply
The FAN5069 is capable of operating from either a 5V or 12V supply. The internal shunt regulator at the VCC pin is capable of sinking 150mA of current to ensure that the controller's internal VCC is maintained at 5.6V Max. To operate from a 12V supply, an external resistor must be used between the 12V supply and the Vcc pin as shown in Figure 1. Select a resistor such that: It is rated to handle the power dissipation Current sunk within the controller is minimized to prevent temperature rise.
Initialization
When the PWM is disabled, the SW node is connected to GND through an internal 70 MOSFET to slowly discharge the output. As long as the PWM controller is enabled, this internal MOSFET remains OFF.
Soft-Start (PWM and LDO)
When VCC exceeds the UVLO threshold and EN is high, the circuit releases SS and enables the PWM regulator. The capacitor connected to the SS pin and GND is now charged by a 10A internal current source causing the voltage on the capacitor to rise. When this voltage exceeds 1.2V, all protection circuits are enabled. When this voltage exceeds 2.2V, the LDO output is enabled. The input to the error amplifier at the non-inverting pin is clamped by the voltage on the SS pin until it crosses the reference voltage. The time it takes the PWM output to reach regulation (TRise) is calculated using the following equation:
T RISE = 8 x 10
-2
PWM Section
The FAN5069's PWM controller combines the conventional voltage mode control and current sensing through lower MOSFET RDS_ON to generate the PWM signals. Although this method of current sensing is loss-less and cost effective, for more accurate current sense requirements an optional external resistor can be connected with the bottom MOSFET in series.
x C SS (CSS is in f)
(EQ. 1)
FAN5069 Rev. 1.1.0
10
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Oscillator Clock Frequency (PWM)
The clock frequency on the oscillator is set using an external resistor, connected between R(T) pin and ground. The frequency follows the graph as shown in Figure 18. The minimum clock frequency is 200KHz which is when R(T) pin is left open. Select the value of R(T) as shown in the equation below. This equation is valid for all FOSC > 200kHz.
5 x 10 R ( T ) = ---------------------------------------------------- ( F OSC - 200 x 10 3 )
9
Over Current Limit (PWM)
The PWM converter is protected against overloading through a cycle-by-cycle current limit set by selecting RILIM resistor. An internal 10A current source sets the threshold voltage for the output of the summing amplifier. When the summing amplifier output exceeds this threshold level, the current limit comparator trips and the PWM starts skipping pulses. If the current limit tripping occurs for 16 continuous clock cycles, a fault latch is set and the controller shuts down the converter. This shut down feature is disabled during the start-up until the voltage on the SS capacitor crosses 1.2V. To achieve current limit, the FAN5069 monitors the inductor current during the OFF time by monitoring and holding the voltage across the lower MOSFET. The voltage across the lower MOSFET is sensed between the PGND and the SW pins. The output of the summing amplifier is a function of the inductor current, RDS_ON of the bottom FET and the gain of the current sense amplifier. With the RDS_ON method of current sensing, the current limit can vary widely from unit to unit. RDS_ON not only varies from unit to unit, but also has a typical junction temperature coefficient of about 0.4%/C (consult the MOSFET datasheet for actual values). Hence, the set point of the actual current limit decreases in proportion to increase in MOSFET die temperature. A factor of 1.6 in the current limit set point typically compensates for all MOSFET RDS_ON variations, assuming the MOSFET's heat sinking will keep its operating die temperature below 125C. For more accurate current limit setting, use resistor sensing. In a resistor sensing scheme, an appropriate current sense resistor is connected between the source terminal of the bottom MOSFET and PGND. Set the current limit by selecting RILIM as follows:
R ILIM K1 x I xR V x 33.2 x 10 11 MAX DS - ON 1.8 OUT = 128 + ------------------------------------------------------------- + 1 - --------- x ------------------------------------------------------ K 0.0625 V F xR IN SW RAMP
(EQ. 2)
Where FOSC is in Hz. For example for FOSC = 300kHz, R(T) = 50K.
RRAMP Selection and Feed Forward Operation
The FAN5069 provides for feed forward function through RRAMP. The value of RRAMP effectively changes the slope of the internal ramp keeping the gain of the modulator constant for changes in input voltage. RRAMP also affects the current limit as explained in the later sections. The minimum value recommended to use for RRAMP is 400K at maximum input voltage of 24V. For other input voltages (E.g. 8V), calculate RRAMP resistor using the following equation:
V IN - 1.8 R RAMP = ------------------------6 55 x 10
(EQ. 3)
Gate Drive Section
The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals and provides necessary amplification, level shifting, and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since the MOSFET switching time can vary dramatically from device to device and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. A low impedance path between the driver pin and the MOSFET gate is recommended for the adaptive dead-time circuit to work properly. Any delay along this path reduces the delay generated by the adaptive dead-time circuit thereby increasing the chances for shoot-through.
(EQ. 4)
Where RILIM is in K, IMAX is the maximum load current. K1 is a constant to compensate for the variation of MOSFET RDS_ON. Typically, this value is 1.6. With K1=1.6, IMAX=10A, RDS_ON=7m, VIN=24V, VOUT=1.5V, FSW = 300KHz, and RRAMP=400K, RILIM equals 168.18 K.
Auto Restart (PWM)
The FAN5069 supports two modes of response when the internal fault latch is set. The user can configure it to keep the power supply latched in the OFF state OR in the Auto Restart mode. When the EN pin is tied to VCC, the power supply is latched OFF. When the EN pin is terminated with a 100nF to GND, the power supply is in Auto Restart mode. The table below describes the relationship between PWM restart and setting on EN pin. Do not leave the EN pin open without any capacitor.
Protection
In the FAN5069, the converter is protected against extreme over load, short circuit, over voltage, and under voltage conditions. All of these extreme conditions generate an internal "fault latch" which shuts down the converter. For all fault conditions both the high-side and the low-side drives are off except in the case of OVP where the low-side MOSFET is turned on until the voltage on the FB pin goes below 0.4V. The fault latch can be reset either by toggling the EN pin or recycling VCC to the chip.
EN Pin
Pull to GND VCC Cap to GND
PWM/Restart
OFF No restart after fault Restart after TDELAY (Sec.) = 0.85 x C Where C is in F
FAN5069 Rev. 1.1.0
11
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
The fault latch can also be reset by recycling the VCC to the controller.
rent and the MOSFET chosen. It is recommended to use low enhancement voltage MOSFETs for the LDO. The soft-start on the LDO output (ramp) is controlled by the capacitor on the SS pin to GND. The LDO output is enabled only when the voltage on the SS pin reaches 2.2V. Refer to figure 9 for startup waveform.
Under Voltage Protection (PWM)
The PWM converter output is monitored constantly for under voltage at the FB pin. If the voltage on the FB pin stays lower than 75% of internal Vref for 16 clock cycles, the fault latch is set and the converter shuts down. This shutdown feature is disabled during startup till the voltage on the SS capacitor reaches 1.2V.
Design Section
General Design Guidelines
Establishing the input voltage range and the maximum current loading on the converter before choosing the switching frequency and the inductor ripple current is highly recommended. There are design tradeoffs in choosing an optimum switching frequency and the ripple current. The input voltage range should accommodate the worst-case input voltage with which the converter may ever operate. This voltage needs to account for the cable drop encountered from the source to the converter. Typically, the converter efficiency tends to be higher at lower input voltage conditions. When selecting maximum loading conditions, consider the transient and steady state (continuous) loading separately. The transient loading affects the selection of the inductor and the output capacitors. Steady state loading affects the selection of MOSFETs, input capacitors, and other critical heat generating components. The selection of switching frequency is tricky. While higher switching frequency results in smaller components, it also results in lower efficiency. Ideal selection of switching frequency takes into account the maximum operating voltage. The MOSFET switching losses are directly proportional to FSW and the square function of the input voltage. When selecting the inductor, consider the min. and max. load conditions. Lower inductor values produce better transient response but result in higher ripple & lower efficiency due to high RMS currents. Optimum minimum inductance value enables the converter to operate at the boundary of continuous and discontinuous conduction modes.
Over Voltage Protection (PWM)
The PWM converter output voltage is monitored constantly at the FB pin for over voltage. If the voltage on the FB pin stays higher than 115% of internal Vref for 2 clock cycles, the controller turns OFF the upper MOSFET and turns ON the lower MOSFET. This crowbar action stops when the voltage on the FB pin comes down to 0.4V to prevent the output voltage from becoming negative. This OVP protection feature is active as soon as the voltage on the EN pin becomes high. Turning ON the low-side MOSFETs on an OVP condition pulls down the output resulting in a reverse current which starts to build up in the inductor. If the output over-voltage is due to failure of the high-side MOSFET, this crowbar action pulls down the input supply or blow its fuse, protecting the system which is very critical. During soft-start, if the output overshoots beyond 115% of Vref, then the output voltage is brought down by the low-side MOSFET till the voltage on the FB pin goes below 0.4V. The fault latch is NOT set until the voltage on the SS pin reaches 1.2V. Once the fault latch is set, the converter shuts down.
115% Vref FB ILIM UV OV V SS>1.2V S Q 0.4V R LS Drive
EN
S Q R
Delay 2 Clks
Fault Latch
Figure 21. Over Voltage Protection Thermal Fault Protection
The FAN5069 features thermal protection where the IC temperature is monitored. When the IC junction temperature exceeds +160C, the controller shuts down and when the junction temperature gets down to +125C, the converter restarts.
Setting the Output Voltage (PWM)
The internal reference for the PWM controller is at 0.8V. The output voltage of the PWM regulator can be set in the range of 0.8V to 90% of its power input by an external resistor divider. The output is divided down by an external voltage divider to the FB pin (for example, R1 and RBIAS as in Figure 24.). Thus the output voltage is given by the following equation:
R1 V OUT = 0.8V x 1 + ---------------- R BIAS
LDO Section
The LDO controller is designed to provide ultra low voltages, as low as, 0.8V for GTL type of loads. The regulating loop employs a very fast response feedback loop. Hence, small capacitors can be used to keep track of the changing output voltage during transients. For stable operation, the minimum capacitance on the output needs to be 100F and the typical ESR needs to be around 100m. The maximum voltage at the gate drive for the MOSFET can reach close to 0.5V below the VCC of the controller. For example, for a 1.2V output, the minimum enhancement voltage required with 4.75V on VCC is 3.05V (4.75V-0.5V-1.2V = 3.05V). The drop-out voltage for the LDO is dependent on the load cur-
(EQ. 5)
To minimize noise pickup on this node, keep the resistor to GND (RBIAS) below 10K.
Inductor Selection (PWM)
When the ripple current, switching frequency of the converter, and the input-output voltages are established, select the inductor using the following equation:
V OUT 2 V OUT - --------------- V IN L MIN = --------------------------------------------I Ripple x F SW
(EQ. 6)
FAN5069 Rev. 1.1.0
12
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Where IRipple is the ripple current. Typically this number varies between 20% to 50% of the maximum steady state load on the converter. When selecting an inductor from the vendors, select the inductance value which is close to the value calculated at the rated current (including half the ripple current).
For loss calculation, refer to Fairchild's Application Note AN6005 and the associated Excel spreadsheet.
High-Side Losses
Losses in the MOSFET can be understood by following switching interval of the MOSFET as shown in Figure 22. MOSFET Gate drive equivalent circuit is shown in Figure 23.
Input Capacitor Selection (PWM)
The input capacitors must have an adequate RMS current rating to withstand the temperature rise caused by the internal power dissipation. The combined RMS current rating for the input capacitor should be greater than the value calculated using the following equation:
V OUT V OUT 2 I INPUT ( RMS ) = I LOAD ( MAX ) x --------------- - --------------- V IN V IN
C ISS VDS C GD C ISS
ID
(EQ. 7)
Common capacitor types used for such application include aluminum, ceramic, POS CAP, and OSCON.
VSP
QGS
QGD
4.5V
Output Capacitor Selection (PWM)
The output capacitors chosen must have low enough ESR to meet the output ripple and load transient requirements. The ESR of the output capacitor should be lower than both of the values calculated below to satisfy both the transient loading and steady state ripple conditions as given by the following equation:
V STEP ESR ------------------------------------ and I LOAD ( MAX ) V Ripple ESR -------------------I Ripple
VTH
VGS
t1 t2
QG(SW)
t3 t4 t5
Figure 22. Switching Losses and QG
5V VIN CGD RD HDRV RGATE G CGS SW
(EQ. 8)
Typically, in case of aluminum and polymer based capacitors, the output capacitance is higher than normally required to meet these requirements. While selecting the ceramic capacitors for the output, although lower ESR can be achieved easily, higher capacitance values are required to meet the VOUT(MIN) restrictions during a load transient. From the stability point of view, the zero caused by the ESR of the output capacitor plays an important role in the stability of the converter.
Figure 23. Drive Equivalent Circuit
The upper graph in Figure 22 represents Drain-to-Source Voltage (VDS) and Drain Current (ID) waveforms. The lower graph details Gate-to-Source Voltage (VGS) vs. time with a constant current charging the gate. The x-axis therefore is also representative of Gate Charge (QG). CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). Obtain the gate charge (QG) parameters shown on the lower graph from the MOSFET data sheets. Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses occur during the shaded time when the MOSFET has voltage across it and current through it. These losses are given by (EQ. 9), (EQ. 11), and (EQ. 11): PUPPER = PSW + PCOND
V DS x I L P SW = ---------------------- x 2 x t s F SW 2 V OUT 2 P COND = --------------- x I OUT x R DS ( ON ) V IN
Output Capacitor Selection (LDO)
For stable operation, the minimum capacitance of 100F with ESR around 100m is recommended. For other values, contact the factory.
Power MOSFET Selection (PWM)
The FAN5069 is capable of driving N-Channel MOSFETs as circuit switch elements. For better performance, the MOSFET selection should address the following key parameters: The maximum drain to source voltage should be at least 25% higher than the worst-case input voltage. The MOSFETs chosen should have low QG, QGD, and QGS The RDS_ON of the MOSFETs be as low as possible. In typical applications for a buck converter, the duty cycles are lower than 20%. So, to optimize the selection of MOSFETs for both the high-side and low-side, follow different selection criteria. Select the high-side MOSFET to minimize the switching losses and the low-side MOSFET to minimize the conduction losses due to the channel and the body diode losses. Note that the gate drive losses also affect the temperature rise on the controller.
(EQ. 9) (EQ. 10)
(EQ. 11)
Where: PUPPER is the upper MOSFET's total losses, and PSW and PCOND are the switching and conduction losses for a given
FAN5069 Rev. 1.1.0
13
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and equals t2+t3 (Figure 22.). The driver's impedance and CISS determine t2 while t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP we can assume a constant current for the driver to simplify the calculation of tS using the following equation:
Q G ( SW ) Q G ( SW ) t s = --------------------- -----------------------------------------------I Driver V CC - V SP ------------------------------------------ R Driver + R Gate
Selection of MOSFET Snubber Circuit
The Switch node (SW) ringing is caused by fast switching transitions due to the energy stored in the parasitic elements . This ringing on the SW node couples to other circuits around the converter if they are not handled properly. To dampen this ringing, an R-C snubber is connected across the SW node and the source of the low-side MOSFET. R-C components for the snubber are selected as follows: a) Measure the SW node ringing frequency (Fring) with a low capacitance scope probe. b) Connect a capacitor (CSNUB) from SW node to GND so that it reduces this ringing by half. c) Place a resistor (RSNUB) in series with this capacitor. RSNUB is calculated using the following equation:
2 R SNUB = ----------------------------------------------- x F ring x C SNUB
(EQ. 12)
Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS - QTH where QTH is the gate charge required to get the MOSFET to its threshold (VTH). Note that for the high-side MOSFET, VDS equals VIN, which can be as high as 20V in a typical portable application. Also include the power delivered to the MOSFET's (PGATE) in calculating the power dissipation required for the FAN5069. PGATE is determined by the following equation:
P Gate = Q G x V CC x F SW
(EQ. 16)
d) Calculate the power dissipated in the snubber resistor as shown in the following equation:
P R ( SNUB ) = C SNUB x V IN ( MAX ) x F SW
2
(EQ. 17)
Where, VIN(MAX) is the maximum input voltage and FSW is the converter switching frequency. The snubber resistor chosen should be adequately de-rated to handle the worst-case power dissipation. Do not use wire wound resistors for RSNUB.
(EQ. 13)
where QG is the total gate charge to reach VCC.
Low-Side Losses
Q2, however, switches on or off with its parallel schottky diode simultaneously conducting. Hence, the VDS 0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and we can select Q2 based on RDS(ON) alone. Conduction losses for Q2 are given by the following equation:
P COND = ( 1 - D ) x I OUT x R DS ( ON )
2
(EQ. 14)
where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and D=VOUT/VIN is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1-D) 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the low-side MOSFET, the JA, and the maximum allowable ambient temperature rise. PD(MAX) is calculated using the following equation:
T J ( MAX ) - T A ( MAX ) P D ( MAX ) = --------------------------------------------------- JA
(EQ. 15)
JA depends primarily on the amount of PCB area that is devoted to heat sinking.
FAN5069 Rev. 1.1.0
14
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
VIN
Current Sense Amplifier
VIN
Q1 L RDC C Q2 RES
RRAMP
Ramp Generator Summing
Amplifier
PWM & DRIVER
VOUT RL
C2 C1 RBIAS
Reference
R2 C3 R1 R3
Figure 24. Closed Loop System with Type 3 Network Loop Compensation
Typically, the closed loop crossover frequency (Fcross) where the overall gain is unity, should be selected to achieve optimal transient and steady state response to disturbances in line and load conditions. It is recommended to keep Fcross, below 1/5th of the switching frequency of the converter. Higher phase margin tends to have a more stable system with more sluggish response to load transients. Optimum phase margin is about 60, a good compromise between steady state and transient responses. A typical design should address variations over a wide range of load conditions and over a large sample of devices. FAN5069 has a high gain error amplifier around which the loop is closed. Figure 24 shows a type 3 compensation network. For type 2 compensation, R3 and C3 are not used. Since the FAN5069 architecture employs summing current mode, type 2 compensation can be used for most applications. For type 2 compensation networks, refer to the following reference for further information: Venable, H. Dean, "The K factor: A new mathematical tool for stability analysis and synthesis", Proceedings of Powercon, March 1983. For critical applications requiring wide loop bandwidth using very low ESR output capacitors, use type 3 compensation.
R L = load resistance T s = Switching Period V i = input voltage F SW = switching frequency
Equations: Effective current sense resistance = R i = 7 x R DSON
R Ri
(EQ. 18)
L Current modulator DC gain = M i = ------
(EQ. 19)
Effective ramp amplitude =
V m = 2.34 x 10
10
( V i - 0.8 ) x T s x ----------------------------------R ramp V Vm
(EQ. 20)
i Voltage modulator DC gain = M v = -------
(EQ. 21)
v Plant DC gain = M o = M v || M i = -------------------i
M xM Mv + Mi
(EQ. 22)
Sampling gain natural frequency = n = ----Ts M xR n x Qz
(EQ. 23)
Type 3 Feedback Component Calculations
Use the following steps to calculate feedback components: Notation:
C 0 = net output filter capacitance G p ( s ) = net gain of plant = control-to-output transfer function L = inductor value R DSON = on-state Drain-to Source resistance of Low-side MOSFET R es = net ESR of the output filter capacitors
O v Effective inductance = L e = ------- x L + -------------------i
M Mv
(EQ. 24)
Mv x Ri x RL R p = ------------------------------- = ( M v x R i ) || R L Mv x Ri + RL
(EQ. 25)
FAN5069 Rev. 1.1.0
15
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Poles and Zeros of Plant Transfer Function:
K R2 = -------------------------------------------------2 x x F cross x C2
(EQ. 38)
1 Plant zero frequency = fz = ----------------------------------------2 x x C o x R es
(EQ. 26)
R1 R3 = ----------------(K - 1)
(EQ. 39)
1 Plant 1st pole frequency = f p1 = --------------------------------------------------------Le 2 x x C o x R p + ------ R L
(EQ. 27)
Layout Considerations
The switching power converter layout needs careful attention and is critical to achieving low losses and clean and stable operation. Below are specific recommendations for a good board layout: Keep the high current traces and load connections as short as possible. Use thick copper boards whenever possible to achieve higher efficiency. Keep the loop area between the SW node, low-side MOSFET, inductor and the output capacitor as small as possible. Route high dV/dt signals such as SW node away from the error amplifier input/output pins. Keep components connected to these pins close to the pins. Place ceramic de-coupling capacitors very close to VCC pin. All input signals are referenced with respect to AGND pin. Dedicate one layer of the PCB for a GND plane. Use at least 4 layers for the PCB. Minimize GND loops in the layout to avoid EMI related issues. Use wide traces for the lower gate drive to keep the drive impedances low. Connect PGND directly to the lower MOSFET source pin. Use wide land areas with appropriate thermal vias to effectively remove heat from the MOSFET's. Use snubber circuits to minimize high frequency ringing at the SW nodes. Place the output capacitor for the LDO close to the source of the LDO MOSFET.
Plant 2nd pole frequency = f p2
Rp 1 1 = ------------ x ------------------- + ------ 2 x Co x RL Le xL 2 x x Rp
2
(EQ. 28)
n e Plant 3rd pole frequency = f p3 = -------------------------
(EQ. 29)
Plant gain (magnitude) response:
f2 1 + --- f z G p (f) = 20 x log M 0 + 10 x log ------------------------------------------------------------------------------------------------------f2 f2 f2 1 + ------ x 1 + ------ x 1 + ------ f p1 f p2 f p3
(EQ. 30) Plant phase response:
-1 f -1 f -1 f -1 f G P (f) = tan --- - tan ------ - tan ------ - - tan ------ f z f p1 f p2 f p3
(EQ. 31)
Choose R1, RBIAS to set the output voltage using EQ.5. Choose the zero cross over frequency Fcross of the overall loop. Typically Fcross should be less than 1/5th of Fsw. Choose the desired phase margin. Typically this number should be between 60 to 90. Calculate plant gain at Fcross using EQ.28 by substituting Fcross in place of f. The gain that the amplifier needs to provide to get the required cross over is given by
1 G AMP = --------------------------------G p (F cross )
(EQ. 32)
The phase boost required is calculated as given in (EQ. 33).
Phase Boost = M - P - 90
(EQ. 33)
Where, M is the desired phase margin in degrees and P is the modulator phase shift in degrees at the time of crossover. The feedback component values are now calculated as given in equations below:
Boost K = Tan ---------------- + 45 4
2
(EQ. 34)
1 C1 = ------------------------------------------------------------------------2 x x F cross x G AMP x R1 C2 = C1 x ( K - 1 ) 1 C3 = ----------------------------------------------------------------2 x x F cross x K x R3
(EQ. 35) (EQ. 36) (EQ. 37)
FAN5069 Rev. 1.1.0
16
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Application Board Schematic ( VIN = 3 to 24V; VOUT =1.5V @20A)
+5V or +12V Vcc J1 R9 200 PWM OUT C7 0.22uF U1 15 VCC R(RAMP) 14 R6 453K FDD6296 16 GLDO HDRV 10 C6 Q2 0.1uF C10 + C11 + 820uF 3-24V
J2 VIN J3 GND
LDO
J7 LDO_Out C4 0.1uF C17 + 560uF
Q1 FDD6530A
820uF
R8 5K R7 10K R4 50K R5 243K C5 0.1uF TP2 C9 0.01uF TP1
1
FBLDO
BOOT
11 C8 0.22uF 9
FDD6606 FDD6606
PWM OUT L1 R11 2.2 C16 3.3nF C1 1500pF 1.8uH C12 C13 + C14 +
J6 GND
2
R(T)
SW
J4 SW_Out + C15 0.1uF J5 GND
3
ILIM
LDRV
13
Q3
Q4
560uF 560uF 560uF
4
SS
PGND
12
7
EN
COMP
5
R2 12.7k
R3 825 R1 5.11K
C3 3300pF
8
AGND FAN5069
FB
6
C2 220pF
R10
5.83K
Figure 25. Application Board Schematic
Bill of Materials
Part Description Capacitor, 1500pF, 20%, 25V , 0603,X7R Capacitor, 220pF, 5%, 50V , 0603,NPO Capacitor, 3300pF, 10%, 50V , 0603,X7R Capacitor, 0.1uF, 10%, 25V , 0603,X7R Capacitor, 0.22uF, 20%, 25V , 0603,X7R Capacitor, 0.01uF, 10%, 50V , 0603,X7R Capacitor, 820uF, 20%, 10X20, 25V ,20mOhm,1.96A Capacitor, 820uF, 20%, 8X8, 2.5V ,7mOhm,6.1A Capacitor, 560uF, 20%, 8X11.5, 4V ,7mOhm,5.58A Capacitor, 3300pF, 10%, 50V , 0603,X7R Connector Header 0.100 V ertical, Tin - 2 Pin Terminal Quickf it Male .052"Dia.187" Tab Inductor, 1.8uH, 20%, 26A mps Max, 3.24mOhm MOSFET N-CH, 32 mOhm, 20V , 21A , D-PA K, FSID: FDD6530A MOSFET N-CH, 8.8 mOhm, 30V , 50A , D-PA K, FSID: FDD6296 MOSFET N-CH, 6 mOhm, 30V , 75A , D-PA K, FSID: FDD6606 Resistor , 5.11K , 1% , 1/16W Resistor , 12.7K , 1% , 1/16W Resistor , 825 , 1% , 1/16W Resistor , 49.9KK , 1% , 1/16W Resistor , 243K , 1% , 1/16W Resistor ,453K , 1% , 1/16W Resistor ,10K , 1% , 1/16W Resistor , 4.99K , 1% , 1/16W Resistor , 200 , 1% , 1/8W Resistor , 5.90K , 1% , 1/16W Resistor , 2.2 , 1% , 1/8W Connector Header 0.100 V ertical, Tin - 1 Pin IC, System Regulator, TSSOP16, FSID: FA N5069 Quantity 1 1 1 4 2 1 2 1 3 1 1 6 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 3 1 C1 C2 C3 C4, C5, C6, C15 C7, C8 C9 C10, C11 C17 C12, C13, C14, C16 J1 J2 - J7 L1 Q1 Q2 Q3, Q4 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 TP1,TP2, Vcc U1 Designator Vendor Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Nippon-Chemicon Nippon-Chemicon Nippon-Chemicon Panasonic Molex Keystone Inter-Technical Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Molex Fairchild Semiconductor Vendor Part Number PCC1774CT-ND PCC221ACVCT-ND PCC1778CT-ND PCC2277CT-ND PCC1767CT-ND PCC1784CT-ND KZH25VB820MHJ20 PSC2.5VB820MH08 PSA4VB560MH11 PCC332BNCT-ND W M6436-ND 1212K-ND SC5018-1R8M FDD6530A FDD6296 FDD6606 P5.11KHCT-ND P12.7KHCT-ND P825HCT-ND P49.9KHCT-ND P243KHCT-ND P453KHCT-ND P10.0KHCT-ND P4.99KHCT-ND P200FCT-ND P5.90KHCT-ND P2.2ECT-ND W M6436-ND FAIRCHILD
FAN5069 Rev. 1.1.0
17
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Typical Application Board Layout
Figure 26. Assembly Diagram
Figure 29. Mid Layer 2
Figure 27. Top Layer
Figure 30. Bottom Layer
Figure 28. Mid Layer 1
FAN5069 Rev. 1.1.0
18
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Mechanical Dimensions
16-Lead TSSOP
7.72 TYP 4.16 TYP. DIMENSIONS METRIC ONLY 5.0 0.1 -A(1.78 TYP) 0.42 TYP
8
16
0.65 TYP LAND PATTERN RECOMMENDATION
6.4
4.4 0.1 -B3.2 0-8
1 8 0.2 C B A ALL LEAD TIPS
GAGE PLANE 0.25
PIN #1 IDENT.
TYPICAL, SCALE: 40X
SEATING PLANE 0.6 0.1 DETAIL A
SEE DETAIL A
0.1 C ALL LEAD TIPS
(0.90) 1.1 MAX TYP
0.65 TYP
-C-
0.100.05 TYP (0.19-0.30 TYP)
0.13 M A B S C S
(0.09-0.20 TYP)
FAN5069 Rev. 1.1.0
19
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM FACT Quiet SeriesTM ActiveArrayTM FAST(R) BottomlessTM FASTrTM CoolFETTM FPSTM CROSSVOLTTM FRFETTM DOMETM GlobalOptoisolatorTM EcoSPARKTM GTOTM E2CMOSTM HiSeCTM EnSignaTM I2CTM FACTTM ImpliedDisconnectTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM
DISCLAIMER
ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM
POPTM Power247TM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM
SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I7
FAN5069 Rev. 1.1.0
20
www.fairchildsemi.com

▲Up To Search▲

Price & Availability of FAN5069

	To Download FAN5069 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .