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Semiconductor
SD60C31/P, SD60C51/P
CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER
Description
The AUK 60C31/P 60C51/P is a high-performance micro controller fabricated with AUK high-density CMOS technology. The AUK CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS. The 60C51 contains a 4K x 8 ROM, a 128 x 8 RAM, 32 I/O lines, two 16-bit counter/timers, a five-source, two-priority level nested interrupt structure, a serial I/O port for either multiprocessor communication, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device has two software selectable modes of power reduction idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning.
Features
* * * * * * * 8-bit CPU optimized for control applications. * Power control modes. Pin-to-pin compatible with intel's 80C51/80C31. 60C51 low power mask programmable ROM * 60C31 low power CPU only 64K Program Memory Space, Data Memory space 32K programmable I/O lines. * Two 16bit timer/counters High performance CMOS process. * 5 interrupt sources. 2 Level programmable serial port * 3.5 to 12MHz @ 5V 20%
Ordering Information
Type NO. SD60C31 SD60C51 Marking SD60C31 SD60C51 Package Code PLCC44 PLCC44 Type NO. SD60C31P SD60C51P Marking SD60C31 SD60C51 Package Code DIP40 DIP40
Outline Dimensions
40
0 .6 95 0 .6 85 0 .6 56 0 .6 50 (1 7.6 53 ) (1 7.3 99 ) (1 6.6 62 ) (1 6.5 10 ) 0.042(1.067) 45 0.048 (1.219)
unit :
21
mm
13.4 0.2
1 5.24
0.695 (17.653) 0.685 (17.399)
0.656 (16.662) 0.650 (16.510)
1
20
50.7 0. 2
MIN 0.020 (0.508)
SEATING PLANE
BASE PLANE
0.5 MIN
0 .0 50 (1 .27 0)
4. 5 0.3
0.180 (4.572) 0.165 (4.191) 0.120 (3.048) 0.090 (2.286)
0 .6 30 (16 .0 02 ) 0 .5 90 (14 .9 06 )
1 .2 2T YP
2 .5 4
1. 40. 1
0. 50. 1
PLCC44
DIP40
KSI-W001-000
3.5 0.3
0.2 5
15 MA
X
o
1
SD60C31/P SD60C51/P
Absolute Maximum Ratings
Characteristic
Ambient temperature under bias Storage temperature Voltage on any pin to Vss Maximum IOL per I/O pin Power dissipation
Rating
0 ~+70 -65 ~ +150 -0.5~Vcc + 0.5 15 1
Unit
C C V Watt
Block Diagram
External Interrupts
Interrupt Control
4K ROM
SFR
128 RAM
Timer 1 Timer 0
Counter Input
CPU
Osc
Bus Control
Four I/O Ports
Serial Port
TxD P0 P2 P1 P3
RxD
Address/Data
- F Figure M C 6 0 C 5 1 B lo c k D ia g ra m ig u r e D 60C51L Block Diagram
Description
The AUK 60C31/P 60C51/P is a high-performance micro controller fabricated with AUK high-density CMOS technology. The AUK CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS. The 60C51 contains a 4Kx8 ROM, a 128x8 RAM, 32I/O lines, two 16-bit counter/times, a five-source, two-priority level nested interrupt structure, a serial I/O port for either multiprocessor communication, I/O expansion or full duplex UART, and on-chip oscillator and clock circuists. In addition, the device has tow software selectable modes of power reduction idle mode and powerdown mode. The idle mode freezes the CPU while allowing the RAM, times, serial port, and interrupt system to continue functioning.
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SD60C31/P SD60C51/P
Pin Configuration
T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
39 38 37 36 35 34 33 32
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
7 8 9 10 11 12 13 14 15 16 17
44
43
42
41
40
6
5
4
3
2
1
P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
T2/P1.0
1
40
VCC
39 38 37 36 35
40DIP DIP40
31 30 29 28 27 26 25 24 23 22 21
44PLCC PLCC44
34 33 32 31 30 29
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
21
22
24
25
18
19
20
23
26
27
Pin Description
VCC : PIN 40 (DIP40), PIN 44 (PLCC44) Supply voltage during normal, Idle and power down operations. VSS : PIN 20 (DIP40), PIN 22 (PLCC44) Circuit ground. Port 0 : PIN 32~39 (DIP40), PIN 36~43 (PLCC44) Port 0 is an 8bit open drain bi-directional I/O port. Port 0 pins that have 1's written to the them float, and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullups when emitting 1's.
KSI-W001-000
WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4
28
3
SD60C31/P SD60C51/P
Pin Description(continued)
Port 1 : PIN 1~8 (DIP40), PIN 2~9 (PLCC44) Port 1 is an 8-bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pullups. Port 2 : PIN 21~28 (DIP40), PIN 24~31 (PLCC44) Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1's. During accesses to external data memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register Port 3 : PIN 10~17 (DIP40), PIN 13~19 (PLCC44) Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the pullups. Port 3 also serves the function of various special feature of the MCS-51 Family, as listed below :
Port PIN
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
PIN NO.
10 11 12 13 14 15 16 17
Alternate Function
RxD (Serial input port) TxD (Serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe)
RST
: PIN 9 (DIP40), PIN 10 (PLCC44) Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits Power-On
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reset using only an external capacitor to VCC.
SD60C31/P SD60C51/P
Pin Description(continued)
ALE : PIN 30 (DIP40), PIN 33 (PLCC44) Address latch enable output pulse for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing of clocking purposes. Note : However, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX instruction. Otherwise, the pin is weakly pulled high. PSEN : PIN 29 (DIP40), PIN 32 (PLCC44) Program store enable is the read strobe to external program memory. When the 60C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA : PIN 31 (DIP40), PIN 35 (PLCC44) External access enable. FFFFH. If EA is strapped to VCC the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. XTAL1 : PIN 19 (DIP40), PIN 21 (PLCC44) Input to the inverting oscillator amplifier and input to the internal clock generator circuits. NC : PIN1, 12, 23, 34 (PLCC44) Non connection pins. XTAL2 : PIN 18 (DIP40), PIN 20(PLCC44) Output from the inverting oscillator amplifier EA must be strapped to VSS in order to enable the device to fetch code from external program memory locations starting at 0000H up to
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SD60C31/P SD60C51/P
Pin Description(continued)
* Crystal oscillator
XTAL2 30pF 30pF XTAL1 VSS
Idle Mode
In the Idle mode, the CPU puts itself to sleep while all the on chip peripherals stay active. The instruction that invokes the Idle mode is the last instruction executed in the normal operating mode before Idle mode is activated. The content of the on-chip RAM and all the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt, at which time the process is picked up at the interrupt service routine and continued, or by a hardware reset which starts the processor the same as a power on reset.
Power Down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and special function register retain Reset redefines the SFRs but does not their values until the power down mode is terminated. The only exit from power down is a hardware reset. change the on-chip RAM. restart and stabilize. The control bits for the reduced power modes are in the special function register PCON. Table Status of the external pins during Idle and power down modes. The reset should not be activated before VCC is restored to its
normal operating level and must be held active long enough to allow the oscillator to
Mode
Idle Idle Power down Power down
Program memory
Internal External Internal External
ALE
1 1 0 0
PSEN
1 1 0 0
PORT 0
Data Float Data Float
PORT 1
Data Data Data Data
PORT 2
Data Address Data Data
PORT 3
Data Data Data Data
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SD60C31/P SD60C51/P
Electrical Characteristics(DC)
(TA = 0 ~ 70 or -40 ~ 85, VCC = 5V 20%, VSS=0V)
SYMBOL
VIL VILI VIH VIHI VOL VOLI VOH
PARAMETER
Input low voltage, except EA Input low voltage to EA Input high voltage, except XTAL1,RST Input high voltage to XTAL1, RST Output low voltage to ports 1,2,3 Output low voltage to ports 0, ALE, PSEN Output high voltage to ports 1,2,3,ALE,PSEN Output high voltage (port 0 in external bus mode) Logical 0 input current to ports 1,2,3 Logical 1 to 0 transition current to port 1,2,3 Input leakage current to port 0, EA Power supply current Active mode @ 12MHz Idle mode @ 12MHz Power-down mode Internal reset pull-down resistor Pin capacitance
TEST CONDITIONS
MIN
-0.5 0 0.2VCC+ 0.9 0.7 VCC
LIMITS TYP. MAX
0.2VCC0.1 0.2VCC0.3 VCC+0.5 VCC+0.5 0.45 0.45
UNIT
V V V V V V V
IOL=1.6 IOL=3.2 IOH=-60 IOH=-25 IOH=-10 IOH=-800 IOH=-300 IOH=-80 VIN=0.45V VIN=2V 0.45VOHI IIL ITL ILI ICC RRST C10
V -50 -650 10 20 5 50 150 10 A A A mA mA A kohm pF
Note
:
1.
See figure 8 through 11 for ICC test conditions. Minimum VCC for power down is 2V.
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SD60C31/P SD60C51/P
Electrical AC Characteristics(AC)
(TA = 0 or -40 ~ 85, VCC = 5V 20%, VSS=0V)
SYM FIGU -BOL RE
1/tCLC
L
PARAMETER
Oscillator frequency versions 60C31/60C51 ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time : Speed
12MHz CLOCK MIN MAX
127 28 48 234 43 205 145 0 59 312 10 400 400 252 0 97 517 585 200 203 23 33 0 43 20 20 20 20 123 300
VARIABLE CLOCK MIN
3.5 2tCLCL-40 tCLCL-55 tCLCL-35 4tCLCL-100 tCLCL-40 3tCLCL-45 3CLCL-105 0 tCLCL-25 5tCLCL-105 10 6tCLCL-100 6tCLCL-100 5tCLCL-165 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL-50 4tCLCL-130 tCLCL-60 tCLCL-50 0 tCLCL-40 20 20 20 20 tCLCL+40 3tCLCL+50
UNIT
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX
12
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQZ tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL
1 1 1 1 1 1 1 1 1 1 1 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 4 4 4 4
Data Memory
External Clock
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SD60C31/P SD60C51/P
Timing Diagram
tLHLL
ALE
tAVLL tLLIV tLLPL tPLPH
PSEN
tLLAX
tPLIV tPLAZ tPXIX
INSTR IN
tPXIZ
PORT0
A0 - A7
A0 - A7
tAVIV
PORT2
A0 - A15
A8 - A15
Figure 1. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLWL
tLLDV tRLRH
RD
tAVLL tLLAX tRLDV tRLAX tRHDX
DATA IN A0 - A7 FROM PCL INSTR IN
tRHDZ
PORT0
A0 - A7 FROM RI OR DPL
tAVWL tAVDV
PORT2
P2.0 - P2.7 OR A8 - A15 FROM DPH
A0 - A15 FROM PCH
Figure 2. External Data Memory Read Cycle
KSI-W001-000
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SD60C31/P SD60C51/P
Timing Diagram(Continued)
ALE
tWHLH
PSEN
tLLWL tWLWH
WR
tAVLL tLLAX tQVWX tWHQX
PORT0
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
INSTR IN
tAVWL
PORT2
P2.0 - P2.7 OR A8 - A15 FROM DPH
A0 - A15 FROM PCH
Figure 3. External Data Memory Write Cycle
VCC
- 0.5
0.7VCC 0.2VSS
-0.1 tCLCX tCHCX tCLCH tCHCL
0.45V
tCLCL
Figure 4. Ex ternal Clock Drive
VCC
-0.5
VLOAD+ 0.2VCC
+0.9
+ 0.1V TIMING REFERENCE POINTS
VOH VOL
- 0.1V
VLOAD VLOAD
- 0.1V
+ 0.1V
0.45V
-0.1 0.2VCC
NOTE : AC Inputs during testing are driv en at V CC-0.5 for a logic '1' and 0.45V for a logic '0'. Timing measurements are made at V IH min for a logic '1' and V IL for a logic '0'
NOTE : For timing purposes, a port is no longer floating when a 100mV change from load v oltage occurs, and begings to float when a 100mV change from the loaded V OH /V OL lev el occurs. IOH/IOL 20mA
Figure 5. AC T es ting Input/ Output
Figure 6. Float Waveform
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SD60C31/P SD60C51/P
Timing Diagram(Continued)
45
40
35
30 MAX ACTIVE MODE 25
I CC
20
15
TYP ACTIVE MODE
10 MAX IDLE MODE 5 TYP IDLE MODE 4MHz 8MHz FREQ AT XTAL1 12MHz 16MHz
Figure 7. Icc vs. FREQ Valid only within frequency specifications of the device under test
VCC ICC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS RST VCC P0 EA VCC ICC
VCC
VCC
Figure 8. I CC Test Condition, Active Mode All other pins are disconnected
Figure 9. I CC Test Condition, Idle Mode All other pins are disconnected
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SD60C31/P SD60C51/P
Timing Diagram(Continued)
VCC
- 0.5
0.7VCC 0.2VSS tCHCL
- 0.1
0.45V
tCLCX tCLCL
tCHCX tCLCH
Figure 10. Clock Signal Waveform for Icc Tests in Active and Idle Modes tCLCH = tCHCL = 5
VCC ICC RST VCC VCC P0 EA (NC) XTAL2 XTAL1 VSS
Figure 11. Icc Test Condition, Power down Mode All other pins are disconnected, Vcc = 2V to 5.5V
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