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Am79Q4457/5457
Quad Subscriber Line Audio Processing CircuitNon-Programmable (QSLACTM-NP) Devices
DISTINCTIVE CHARACTERISTICS
n n n n
Performs the function of four Codec/Filters A-law or -law coding Single PCM port -- Up to 4.096 MHz operation (64 channels) Hardware programmable (via external components) -- Transhybrid balance impedance -- Transmit and receive gains
n
Additional Am79Q4457 device capabilities (per channel, set external) -- Three selectable transmit gains -- Three selectable receive gains -- Two selectable balance networks -- Simple serial control interface Separate PCM and Master clocks 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz master clock options -- Internal timing automatically adjusted based on MCLK and frame sync signal Low power 5.0 V CMOS technology 5.0 V only operation
n n n n
GENERAL DESCRIPTION
The Am79Q4457/5457 Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) device integrates the key functions of analog linecards into a high-performance, four-channel Codec/Filter device. The QSLAC-NP devices are based on the proven design of the reliable Am79C02/03/031(A) Dual Sub scr ibe r Line Aud io-Processing Circu it (DSLAC TM ) devices, and the Am79C202 Advanced Subscriber Line Audio-Processing Circuit (ASLAC TM) device. The advanced architecture of the QSLAC-NP devices implements four independent channels in a single integrated circuit, providing a cost-effective solution for the audio-processing function of Plain Old Telephone Service (POTS) linecards. The Am79Q4457/5457 QSLAC-NP device provides four industry-standard Codec/Filter devices in a single integrated circuit. The Am79Q4457/5457 device provides a transmit and receive frame synchronization input per channel. A-law or -law compression is selected via a device pin. In addition, the Am79Q4457 device provides the ability to select one of three independent gain settings (both transmit and receive) and one of two balance networks on a per-channel basis. The transmit and receive gain leve ls ar e set once fo r th e device via exte r na l components. Gain level selection and the balance network selection is achieved through an integrated serial shift register and latch per channel. The Am79Q5457 device provides four industr ystandard Codec/Filter devices in a 32-pin PLCC or 44pin TQFP package. The Am79Q4457 device provides four industr y-standard Codec/Filter devices and selectable gain and balance functions in a 44-pin PLCC or 44-pin TQFP package. Advanced submicron CMOS technology enables the Am79Q4457/5457 QSLAC-NP device to have both the functionality and the low power consumption required in linecard designs, maximizing linecard density at a minimum cost. When used with four Legerity SLICs, a QSLAC-NP device provides a complete solution to the BORSCHT function of a POTS linecard.
Although the name and logo have changed, the data contained herein remains the same as the most recent AMD revision of this document.
Publication# 20031 Rev: D Amendment: /0 Issue Date: January 2000
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams (PLCC packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams (44-pin TQFP packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supply for the Am79Q4457/5457 Devices: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics over operating ranges (unless otherwise noted) . . . . . . . . . . . . . . . . . 12 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Variation of Gain with Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Total Distortion, Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Discrimination against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Discrimination against 12 kHz and 16 kHz Metering Signals . . . . . . . . . . . . . . . . . . . . . . . 19 Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Switching Characteristics over operating ranges (unless otherwise noted). . . . . . . . . . . . . . . . . 20 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input and Output Waveforms for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Control Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Control Interface (Output Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PCM Highway Timing (Short Frame Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCM Highway Timing (Long Frame Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating The QSLAC-NP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Control of the Am79Q4457/5457 QSLAC-NP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Parallel Control (Am79Q5457 Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial Control Register (Am79Q4457 Device Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Setting Gain Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gain Settings for the Am79Q4457 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gain Settings for the Am79Q5457 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Calculation of Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Considerations For Connection To Slics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Effects of CRX and CTX Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Placement of the Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SLIC Connection Consideration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PL032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PL044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PQT044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2
Am79Q4457/5457 Data Sheet
List of Figures
Figure 1. Figure 2. Figure 3a. Figure 3b. Figure 4a. Figure 4b. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9a. Figure 9b. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 A-law Gain Tracking with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . 16 m-law Gain Tracking with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . 16 A-law Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . 17 m-law Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . 17 Discrimination against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Am79Q4457 QSLAC-NP Device Serial Control Interface . . . . . . . . . . . . . . . . . 26 QSLAC-NP Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Am79Q4457JC Device (Channel 1 Shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Am79Q5457 Device (Channel 1 Shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Am79Q4457JC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AM79Q5457JC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Balance Network Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Alternate Balance Network Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of Tables
Table 1. Table 2. Table 3. 0 dBm0 Voltage Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transmit Gain Select (Am79Q4457 Device Only). . . . . . . . . . . . . . . . . . . . . . . . 28 Receive Gain Select (Am79Q4457 Device Only) . . . . . . . . . . . . . . . . . . . . . . . . 29
SLAC Products
3
BLOCK DIAGRAM
Quad SLAC-NP Device Analog I1 IN1 I2IN1 VOUT1 I1IN2 I2IN2 VOUT2 I1IN3 I2IN3 VOUT3 I1 IN4 I2IN4 VOUT4 Signal Processing Channel 1 (CH 1) Signal Processing Channel 2 (CH 2) Single PCM Highway DXA DRA PCM Interface TSCA
*2
*2
*2
Signal Processing Channel 3 (CH 3) Signal Processing Channel 4 (CH 4)
*2
A/
Clock & Reference Circuits
FSR1-4 FSX1-4 PCLK MCLK
IREF1 IREF2*2 IREF3*2 VREF1 VREF2*2 VREF3*2
PDN1-4*1 Control Interface
20031A-001
VCCA Notes: *1 = Am79Q5457 only. *2 = Am79Q4457 only.
AGND
VCCD
DGND
CO
*2
CS1-4
*2
CI
*2
CCLK
*2
4
Am79Q4457/5457 Data Sheet
ORDERING INFORMATION Standard Products
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am79Q4457/5457
J
C TEMPERATURE RANGE *C = Commercial (0C to 70C; Relative Humidity = 15% to 95%) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) --Am79Q4457 Only 32-Pin Plastic Leaded Chip Carrier (PL 032) --Am79Q5457 Only V = 44-Pin Thin Quad Flat Pack (PQT 044) --Am79Q4457 and Am79Q5457
DEVICE NUMBER/DESCRIPTION Am79Q4457/5457 Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Device
Valid Combinations Am79Q4457 Am79Q5457 Am79Q4457 Am79Q5457 JC JC VC VC
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on Legerity's standard military-grade products.
Note: * The performance specifications contained in this data sheet for 0C to +70C operation are guaranteed by 100% factory testing at 65C. Extended temperature range specifications (-40C to +85C) are guaranteed by characterization and periodic sampling of production units.
SLAC Products
5
CONNECTION DIAGRAMS (PLCC PACKAGES) Top View
CS4 MCLK PCLK I1IN1 VOUT1 I2IN1 VREF1
6 5 4 3 2 1 44 43 42 41 40
I1IN2 VOUT2 I2IN2 IREF2
VREF2 CS1 CS2 CS3
VCCA IREF1 AGND IREF3 I2IN3 VOUT3 I1IN3
7 8 9 10 11 Am79Q4457JC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
VREF3 A/ RSRVD I1IN4 VOUT4 I2IN4
39 38 37 36 35 34 33 32 31 30 29 28
CI CCLK TSCA DGND CO DXA VCCD DRA FSR1 FSX 1 FSR 2
FSX4 FSR4 FSX3 FSR3 FSX2
20031A-002
4 I1IN1 I1IN2 VOUT2 VCCA IREF1 AGND VOUT3 I1IN3 I1IN4 5 6 7 8 9 10 11 12 13
VREF1
3
2
1
32 31 30 29 28 27 26 PCLK TSCA DGND DXA VCCD DRA FSR1 FSX1 FSR2
AM79Q5457JC
MCLK 25 24 23 22 21 FSX2
20031A-003
PDN1
PDN2
PDN3 FSX3
14 15 16 17 18 19 20 FSX4 FSR4 FSR3 VOUT4 A/
Note: Pin 1 is marked for orientation.
6
Am79Q4457/5457 Data Sheet
PDN4
VOUT1
CONNECTION DIAGRAMS (44-PIN TQFP PACKAGES) Top View
44 43 42 41 40 39 38 37 36 35 34 I1IN2 VOUT2 I2IN2 IREF2 VCCA IREF1 AGND IREF3 I2IN3 VOUT3 I1IN3 1 2 3 4 5 6 7 8 9 10 11 Am79Q4457VC 33 32 31 30 29 28 27 26 25 24 23 CI CCLK TSCA DGND CO DXA VCCD DRA FSR1 FSX1 FSR2
12 13 14 15 16 17 18 19 20 21 22 VREF3 FSX4 FSR4 FSX3 FSR3 FSX2 MCLK PCLK I1IN4 I2IN4 VOUT4 A/U N/C
PDN1
44 43 42 41 40 39 38 37 36 35 34 I1IN2 VOUT2 N/C N/C VCCA IREF1 AGND N/C N/C VOUT3 I1IN3 1 2 3 4 5 6 7 8 9 10 11 Am79Q5457VC 33 32 31 30 29 28 27 26 25 24 23 N/C N/C TSCA DGND N/C DXA VCCD DRA FSR1 FSX1 FSR 2
12 13 14 15 16 17 18 19 20 21 22 VOUT4 N/C N/C A/U I1IN4 N/C FSX4 FSR4 FSX3 FSR3 FSX2
Note: Pin 1 is marked for orientation.
SLAC Products
PDN2 PDN3 PDN4
VOUT1 N/C
VREF1
I1IN1
N/C
MCLK PCLK
VOUT1 I2IN1 VREF1
VREF2
I1IN1
CS1
CS2 CS3
CS4
7
PIN DESCRIPTIONS
Pin Name Type Description A-law or -law Select. The A-law/-law select pin is used to inform the QSLAC-NP device which compression/expansion standard to use. A logic Low signal (0 V) on the A-law/-law pin selects the -law standard, and a logic High (+5 V) selects the A-law standard. The A-law/-law input can be connected to VCCD directly, eliminating the need for a external pull-up resistor. Therefore, the device can be programmed for A-law by connecting the A/ input to V CCD and can be programmed for -law by connecting the device pin to DGND. (Am79Q4457 Device Only) Control Clock. The Control Clock input shifts data into and out of the Serial Interface of the QSLAC-NP device. The maximum clock rate is 4.096 MHz. (Serial control on the Am79Q4457 device only.) (Am79Q4457 Device Only) Control Data. Control Data is written into the selected Channel Control Register (see CSN) via the CI pin. The data is shifted in the Most Significant Bit (MSB) first. The data rate is determined by CCLK. (Serial control on the Am79Q4457 device only.) (Am79Q4457 Device Only) Control Data. Control Data is read in serial form from the Enabled Channel Register (see CSN) via the CO pin. Data is shifted out with the MSB first. The data rate is determined by the Control Clock (CCLK). (Serial control available on the Am79Q4457 device only.) (Am79Q4457 Device Only) Chip Select. The Chip Select (CSN) input (active Low) enables Channel N of the device so that control data can be written to or read from the channel. CS1 enables Channel 1, CS2 enables Channel 2, CS3 enables Channel 3, and CS4 enables Channel 4. (Serial control on the Am79Q4457 device only.) PCM. The PCM data for Channels 1, 2, 3, and 4 is serially received on the DRA port during the time slot determined by the Receive Frame Sync Signal (FSRN). Data is always received with the MSB first. A byte of data for each channel is received every 125 s at the PCLK rate. PCM. The transmit data from Channels 1, 2, 3, and 4 is sent serially out the DXA port during time slots determined by the Transmit Frame Sync (FSXN ) signal for that channel. Data is always transmitted with the MSB first. The output is available every 125 s and the data is shifted out in 8-bit bursts at the PCLK rate. DXA is high impedance between time slots. Receive Frame Sync. The Receive Frame Sync pulse for Channel N is an 8 kHz signal that identifies the receive time slot for Channel N on a system's receive PCM frame. The QSLACNP device references channel time slots with respect to this input, which must be synchronized to PCLK. There are both Long-Frame Sync and Short-Frame Sync modes available on the QSLAC-NP device. Transmit Frame Sync. The Transmit Frame Sync pulse for Channel N is an 8 kHz signal that identifies the transmit time slot for Channel N during the system's transmit PCM frame. The QSLAC-NP device references individual channel time slots with respect to this input, which must be synchronized to PCLK. There are both Long Frame Sync and Short Frame Sync modes available on the QSLAC-NP device. (I2IN on Am79Q4457 Device Only) Analog Inputs. The analog voice band voltage signal is applied to the IIN input of the QSLAC-NP device through a resistor. The IIN input is a virtual AC ground input (summing node). IIN is biased at the voltage on the VREF1 pin. The audio signal is sampled, digitally processed and encoded, and then made available at the TTL-compatible PCM output (DXA). There are two inputs per channel in the 44-pin QSLAC-NP device. I1IN1 is input 1 of Channel 1 and I2IN1 is input 2 of Channel 1; I1IN2 and I2IN2 are inputs 1 and 2 of Channel 2; I1IN3 and I2IN3 are inputs 1 and 2 of Channel 3; and I1IN4 and I2IN4 are inputs 1 and 2 of Channel 4. See Figure 9 for more details. (IREF2 and IREF3 on Am79Q4457 Device Only). Reference Current. The IREF outputs are biased at the internal reference voltage, which is the same as the voltage on the VREF1 pin. A resistor placed from IREFn (n = 1, 2, or 3) to ground sets one of three reference currents used by the Analog-to-Digital (Ato-D) converter to encode the signal current present on IyINn (n = channel number [1 to 4] and y = input number [1 or 2]) into digital form. By setting different levels for I REFx, three different transmit gains can be achieved. The reference current used by a channel A-to-D is determined by the Transmit Gain Select (TGS) bits in the channel control register. The absolute transmit gain is determined by the reference current selected and the input resistance connected to IIN. See Figure 9 and Table 2 for more details.
A/
Input
CCLK
Input
CI
Input
CO
Output
CS1, CS2, CS3, CS4
Input
DRA
Input
DXA
Output
FSR1, FSR2, FSR3, FSR4
Input
FSX1, FSX2, FSX3, FSX4
Input
I1IN1, I2IN1, I1IN2, I2IN2, I1IN3, I2IN3, I1IN4, I2IN4
Current
IREF1, IREF2, IREF3
Output
8
Am79Q4457/5457 Data Sheet
Pin Name
Type
Description Master Clock. The Master Clock frequency can be 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz for use by the digital signal processor. Using the Transmit Frame Sync (FSX) Inputs, the QSLAC-NP device determines the MCLK frequency and makes the necessary internal adjustments automatically. The master clock frequency must be an exact integer multiple of the frame sync frequency. PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock frequency is 4.096 MHz, and the minimum clock frequency is 256 kHz, due to a single PCM highway. PCLK frequencies between 1.03 MHz and 1.53 MHz are not allowed. The digital signal processor clock can be derived from PCLK by connecting MCLK and PCLK together. See frequency restrictions under MCLK. (Am79Q5457 Device Only) Power Down. The power-down inputs provide direct control over the channel circuitry. A logic High on PDN n (n = 1 to 4) powers Channel n down while a logic Low powers the channel up. PDN1 controls Channel 1, PDN2 controls Channel 2, PDN3 controls Channel 3, and PDN4 controls Channel 4. The PDN pins are used in the initialization of the internal circuitry. Refer to the Power-Up Sequence section on 24 for initialization using the PDN pins. Time Slot Control. The Time Slot Control output is an open drain output (requiring a pull-up resistor to VCCD) and is normally inactive (high impedance). TSCA is active (Low) when PCM data is transmitted on the DXA pin for any of the four channels. Analog Outputs. The received digital data at DRA is processed and converted to an analog signal at the VOUT pin. VOUT1 is the output from Channel 1; VOUT2 is the output for Channel 2; VOUT3 is the output from Channel 3; and VOUT4 is the output for Channel 4. The VOUT voltages are referenced to V REF1. Voltage Reference. The V REF1 output is provided in order for an external 0.1-F capacitor (or larger) to be connected from VREF1 to ground, filtering noise present on the internal voltage reference. VREF1 is buffered before it is used by internal circuitry. The voltage on V REF1 is nominally 2.1 V, and the output resistance is 115 kW. The leakage current in the capacitor must be less than 20 nA. A larger filter capacitor will provide better filtering, but will increase the settling time. (Am79Q4457 Device Only). Voltage Reference. VREF2 and VREF3 are buffered and are available as alternative reference voltages for the channel Digital-to-Analog (D-to-A) converters. The D-to-A converters decode the received PCM data into analog voltage levels. VREF1, VREF2, or VREF3 can be selected by the Receive Gain Select (RGS) bits as the reference for the D-to-A converter in order to select the receive gain of the channel.
MCLK
Input
PCLK
Input
PDN1, PDN2, PDN3, PDN4
Input
TSCA
Output
VOUT1, VOUT2, VOUT3, VOUT4
Voltage
VREF1
Output
VREF2, VREF3
Input
Power Supply for the Am79Q4457/5457 Devices:
AGND DGND VCCA VCCD Analog Ground Digital Ground +5.0 V Analog Power Supply +5.0 V Digital Power Supply
Two separate power supply inputs are provided to allow for noise isolation and good power supply decoupling techniques; however, the two pins have a low impedance connection inside the part. For best performance, all of the +5.0 power supply pins should be connected together at the connector of the printed circuit board, and all of the grounds should be connected together at the connector of the printed circuit board.
SLAC Products
9
FUNCTIONAL DESCRIPTION
The QSLAC-NP device performs the Codec/Filter and two-to-four-wire conversion function (requires external balance impedance) required of the subscriber line interface circuitry in telecommunications equipment. These functions involve converting an audio signal into digital PCM samples and converting digital PCM samples back into an audio signal. During conversion, digital filters are used to band limit the voice signals. All of the digital filtering is performed in digital signal processors operating from an internal clock, which is derived from MCLK. The fixed filters set the transmit and receive gain and frequency response. The transmit and receive gain can be altered on a perchannel basis and the per-channel balance impedance can be selected between two external impedances by the Am79Q4457 QSLAC-NP device. Control of these functions is provided by an integrated serial shift register and latch per channel. These additional functions are available on the Am79Q4457 device only. Data transmitted or received on the PCM highway is an 8-bit, A-law or -law companded code. The QSLAC-NP device is compatible with both codes. Code selection is provided via a device pin (A/). The 8-bit codes appear 1 byte per time slot. The PCM data is read and written to the PCM highway in time slots determined by the individual Frame Sync signals (FSRN and FSXN) at rates from 256 kHz to 4.096 MHz. Both Long- and ShortFrame Sync modes are available in the QSLAC-NP device. Two configurations of the QSLAC-NP device are offered as pictured previously. The Am79Q4457 dev ic e w i t h s e r i a l c o n t r o l o f g a i n a n d b a la n c e impedance is available in the 44-pin PLCC package and 44-pin TQFP package. The Am79Q5457 device without serial control is available in a 32-pin PLCC package and 44-pin TQFP package.
Serial Control Yes No Yes No Package 44 PLCC 32 PLCC 44 TQFP 44 TQFP Part Number Am79Q4457 Am79Q5457 JC JC
Am79Q4457 VC Am79Q5457 VC
10
Am79Q4457/5457 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . -60C < TA < +125C Ambient Operating Temp . . . . . . . -40C < TA < +85C Ambient Relative Humidity . . . . . . . . . . . . 5% to 95% (non condensing) VCCA with respect to VCCD . . . . . . . . . . . . . . . . 50 mV VCCA with respect to AGND. . . . . . . . . -0.4 V to +7.0 V VCCD with respect to DGND . . . . . . . . -0.4 V to +7.0 V AGND with respect to DGND . . . . . . . . . . . . . . 0.4 V IIN Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Other pins with respect to DGND . . . . . .-0.4 V to VCCD +0.4 V Latch-up immunity (any pin). . . . . . . . . . . . . . 30 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES
VCCA, Analog Supply . . . . . . . . . . . . . . . . VCCD 10 mV VCCA, Analog Supply . . . . . . . . . . . . . +5.0 V 0.25 V VCCD, Digital Supply . . . . . . . . . . . . . +5.0 V 0.25 V DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mV Ambient Temperature . . . . . . . . . . . .0C < TA < +70C Ambient Relative Humidity . . . . . . . . . . . .15% to 95%
Operating Ranges define those limits between which functionality of the device is guaranteed by 100% production testing. Specifications in this data sheet are guaranteed by testing from 0C to +70C. Performance from -40C to +85C is guaranteed by characterization and periodic sampling of production units.
SLAC Products
11
ELECTRICAL CHARACTERISTICS over operating ranges (unless otherwise noted)
Typical values are for TA = 25C and nominal supply voltages. Minimum and maximum specifications are over the temperature and supply voltage ranges shown in Operating Ranges.
Symbol VIL VIH IIL VOL Parameter Descriptions Input Low voltage Input High voltage Input leakage current Output Low voltage TSCA (IOL =14 mA) All other digital outputs (IOL = 2 mA) Output High voltage All digital outputs (IOH = 400 A) Output leakage current (H I = Z State) Analog input current range, RREF = 13 k Offset current allowed on IIN Offset voltage on IIN relative to VREF1 VOUT output impedance VREF1 output impedance (F < 3400 Hz) VOUT output current (F<3400 Hz) (Note 1) VOUT voltage range VOUT offset voltage (Relative to VREF1) Power dissipation All channels active 1 channel active All channels inactive (Note 2) -40 180 60 1 15 15 40 80 -4 1.584 40 240 90 6 -1.6 -16 1 2.4 -10 40 1.6 16 4 150 4 10 2.0 -10 10 0.4 0.4 Min Typ Max 0.8 Unit V V A V V V A A A mV k mA V mV mW mW mW pF pF dB
VOH IOL IIR IIOS VIOS ZOUT ZREF1 IOUT VOR VOOS PD
CI CO PSRR
Input capacitance (Digital) Output capacitance (Digital) Power supply rejection ratio (1.02 kHz, 100 mVrms, either path, GX = GR = 0 dB)
Notes: 1. When the QSLAC-NP device is in the Inactive mode, the analog output (VOUT) will present a VREF1 DC output level through a ~400-k resistor. 2. Power dissipation in the Inactive mode is measured with all digital inputs at VIH = VCC and VIL = DGND, and with no load connected to VOUT1, VOUT2, VOUT3, or VOUT4.
12
Am79Q4457/5457 Data Sheet
Transmission Characteristics
Table 1. 0 dBm0 Voltage Definitions
Signal at Digital Interface A-law digital mW or equivalent (0 dBm0) -law digital mW or equivalent (0 dBm0) Transmit 0.6776/Gt 0.6778/Gt Receive 0.6776 x Gr 0.6778 x Gr Unit Vrms Vrms Note 1 1
Description Gain accuracy, either path
Test Conditions 0 dBm0, 1014 Hz 0C to 85C Am79Q5457, or Am79Q4457, Gt = Gt1, Gr = Gr1 -40C (All), or Am79Q4457, Gt = Gt2 or Gt = Gt3, or Gr = Gr2 or Gr = Gr3
Min -0.25
Typ
Max +0.25
Unit dB
Note
-0.35
+0.35
dB
Attenuation distortion Single frequency distortion Idle channel noise Analog out Analog out Analog out Digital out Digital out digital input = 0 analog VIN = 0 0 dBm0
300 Hz to 3 kHz unweighted A-law -law A-law -law
-0.125
+0.125 -46 -55 -78 12 -68 16 -76 -76 -78 -78 500 540 0.5 2 5
dB dB dBm0 dBm0p dBrnc0 dBm0p dBrnc0 dBm0 dBm0 dBm0 dBm0 s dB dB dB
2 3 4 4 4 4 4
Crosstalk between channels TX or RX to TX TX or RX to RX End-to-end group delay Analog-to-analog overload compression loss relative to 0 dBm0 loss
1014 Hz Average 1014 Hz Average PCLK 1.53 MHz 3 dBm0, 1004 Hz input, C-weight 6 dBm0, 1004 Hz input, C-weight 9 dBm0, 1004 Hz input, C-weight
5 5 6, 7
Notes: 1. Gt and Gr are defined in the Transmit Gain Select and Receive Gain Select tables on 28 and 29. Gr must be in the range: 0.4 Gr 1. RREF must be in the range: 13K R REF 26K, where R REF is RREF1, R REF2A + RREF2B, or R REF3A + RREF3B. 2. Also see the following Attenuation Distortion figure. 3. Measured with a 0 dBm0 input signal, 300 Hz to 3400 Hz; output measured at any other frequency 300 Hz to 3400 Hz. 4. No single frequency component in the range above 3800 Hz may exceed a level of -55 dBm0. 5. The weighted average of the crosstalk is defined by the following equation, where C(f) is the crosstalk in dB as a function of frequency, fN = 3300 Hz, f1 = 300 Hz, and the frequency points (fj, j = 2..N) are closely spaced:
--------------------------------------------------------- * log 2
10 + 10 Average = 20 * log
1
1----- * C ( f j ) 20
1----- * C ( fj - 1 ) 20
fj -------- f
j-1
j ------------------------------------------------------------------------------------------------- f N log ---f
6. See following Group Delay Distortion figure also. 7. The End-to-End Group Delay is the sum of the transmit and receive group delays where both are measured using the same time slot.
SLAC Products
13
Attenuation Distortion
If a capacitive coupling network is used in series with either the transmit input or the receive output of the part, that network must have a corner frequency of less than 20 Hz to meet the template in Figure 1. If the corner frequency is above 20 Hz, the loss in the coupling network must be taken into account.
QSLAC-NP Device Specification
2
Transmit curve 1.6 dB Attenuation (dB) 1 Receive curve 1 dB 0.75 dB
0.125 0 - 0.125 Transmit only
200
300 Frequency (Hz)
3000
3400
20013A-006
Figure 1. Attenuation Distortion
14
Am79Q4457/5457 Data Sheet
Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in Figure 2. The minimum value of the group delay is taken as the reference. The signal level should be 0 dBm0.
420
QSLAC-NP Device Specification (Either Path)
Delay (s) 175
125
90
0
500 600
1000 Frequency (Hz)
2600
2800
3000
20013A-007
Figure 2. Group Delay Distortion
SLAC Products
15
Variation of Gain with Input Level
The gain deviation relative to the gain at -10 dBm0 is within the limits shown in Figure 3 for either transmission path when the input is a sine wave signal of frequency 1014 Hz.
1.5
QSLAC-NP Device Specification
0.55 0.25 Gain dB 0 -55 -50 -0.25 -0.55 -40 -10 0 +3 Input Level dBm0
-1.5
19256A-008
Figure 3a. A-law Gain Tracking with Tone Input (Both Paths)
1.4
QSLAC-NP Device Specification
0.45 0.25 Gain dB 0 -55 -50 -0.25 -0.45 -37 -10 0 +3 Input Level dBm0
-1.4
19256A-009
Figure 3b. -law Gain Tracking with Tone Input (Both Paths)
16
Am79Q4457/5457 Data Sheet
Total Distortion, Including Quantizing Distortion
The signal-to-total distortion will exceed the limits shown in Figure 4 for either transmission path when the input is a sine wave signal of frequency 1014 Hz.
QSLAC-NP Device Specification
35.5 30 25
35.5
Signal-to-Total Distortion (dB)
-45 -40 -30 Input Level (dBm0)
+3
20013A-010
Figure 4a. A-law Total Distortion with Tone Input (Both Paths)
QSLAC-NP Device Specification
35.5 31 27
35.5
Signal-to-Total Distortion (dB)
-45 -40 -30 Input Level (dBm0)
+3
20013A-011
Figure 4b. -law Total Distortion with Tone Input (Both Paths)
SLAC Products
17
Discrimination against Out-of-Band Input Signals
When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be frequency components below 4 kHz at the digital output caused by the out-of-band signal. These components are at least the specified dB level below the level of a signal at the same output originating from a 1014-Hz sine wave signal with a level of A dBm0 also applied to the analog input. The minimum specifications are shown in Figure 5.
Frequency of Out-of-Band Signal 16.6 Hz < f < 45 Hz 45 Hz < f < 65 Hz 65 Hz < f < 100 Hz 3400 Hz < f < 4600 Hz 4600 Hz < f < 100 kHz
Amplitude of Out-of-Band Signal -25 dBm0 < A 0 dBm0 -25 dBm0 < A 0 dBm0 -25 dBm0 < A 0 dBm0 -25 dBm0 < A 0 dBm0 -25 dBm0 < A 0 dBm0
Level below A 18 dB 25 dB 10 dB see Figure 5 32 dB
0 QSLAC-NP Device Specification -10
-20 Level (dB) -30 -32 dB, -25 dBm0 < input < 0 dBm0 -40 -28 dBm
-50
3.4
4.0
4.6 Frequency (kHz)
20013A-012
Note: The attenuation of the waveform below amplitude A between 3400 Hz and 4600 Hz is given by the formula:
( 4000 - f ) Attenuation (db) = 14 - 14 sin -------------------------1200
Figure 5. Discrimination against Out-of-Band Signals
18
Am79Q4457/5457 Data Sheet
Discrimination against 12 kHz and 16 kHz Metering Signals
If the QSLAC-NP device is used in a metering application where 12 kHz or 16 kHz tone bursts are injected onto the telephone line toward the subscriber, a portion of those tones may also appear at the I IN terminal. These out-of-band signals may cause frequency components to appear below 4 kHz at the digital output. For a 12 kHz or 16 kHz tone, the frequency components below 4 kHz will be reduced from the input by at least 70 dB. The sum of the peak metering and signal currents must be within the analog input current range.
out-of-band signals at the analog output is less than the limits shown in the following table.
Frequency 4.6 kHz to 40 kHz 40 kHz to 240 kHz 240 kHz to 1 MHz
Level -32 dBm0 -46 dBm0 -36 dBm0
Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied to the digital input, the level of the spurious
With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to the digital input, the level of the signals at the analog output are below the limits in Figure 6. The amplitude of the spurious out-of-band signals between 3400 Hz and 4600 Hz is given by the formula: ( f - 4000 ) A = - 14 - 14 sin --------------------------- dBm0 1200
0 QSLAC-NP Device Specification -10
-20 Level (dBm0) -30 -28 dB -32 dB
-40
-50
3.4
4.0
4.6 Frequency (kHz)
19256A-013
Figure 6. Spurious Out-of-Band Signals
SLAC Products
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SWITCHING CHARACTERISTICS over operating ranges (unless otherwise noted)
Min and Max values are valid for all digital outputs with a 150 pF load.
Control Interface
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol tCCY tCCH tCCL tCCR tCCF tICSS tICSH tICSL tICSO tIDS tIDH tOLH tOCSS tOCSH tOCSL tOCSO tODD tODH tODOF tODC Parameter Control Clock Period Control Clock High Pulse Width Control Clock Low Pulse Width Rise Time of Clock Fall Time of Clock Chip Select Setup Time, Input Mode Chip Select Hold Time, Input Mode Chip Select Pulse Width, Input Mode Chip Select Off Time, Input Mode Input Data Setup Time Input Data Hold Time Output Latch Valid (Internal) Chip Select Setup Time, Output Mode Chip Select Hold Time, Output Mode Chip Select Pulse Width, Output Mode Chip Select Off Time, Output Mode Output Data Turn On Delay Output Data Hold Time Output Data Turn Off Delay Output Data Valid 0 0 50 50 1 50 70 0 8t CCY 2 30 30 100 t CCY -10 t CCH -20 70 0 8t CCY Min 244 97 97 25 25 t CCY -10 t CCH -20 Typ Max Units ns ns ns ns ns ns ns ns s ns ns ns ns ns ns s ns ns ns ns
PCM Interface
PCLK not to exceed 4.096 MHz. Pull-up resistor of 360 is attached to TSCA.
No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol tPCY tPCH tPCL tPCF tPCR tFSS tFSH tFSJ tTSD tTSO tDXD tDXH tDXZ tDRS tDRH tTSD tDXD Parameter PCM Clock Period (Note 1) PCM Clock High Pulse Width PCM Clock Low Pulse Width Fall Time of Clock Rise Time of Clock FS Setup Time FS Hold Time FS or PCLK Jitter Time Delay to TSCA Valid (Short Frame Sync Mode) Delay to TSCA Off (Note 2) PCM Data Output Delay (Short Frame Sync Mode) PCM Data Output Hold Time PCM Data Output Delay to High-Z (Note 3) PCM Data Input Setup Time PCM Data Input Hold Time Delay to TSCA Valid (Long Frame Sync Mode) PCM Data Output Delay (Long Frame Sync Mode) 55 50 -68 5 50 5 5 50 25 5 5 5 40 40 +68 80 220 t PCL +70 70 70 220 t PCL +70 ns ns ns ns ns ns ns Min 244 97 97 25 25 t PCY -50 Typ Max Units ns ns ns ns ns ns ns ns ns ns
20
Am79Q4457/5457 Data Sheet
Master Clock
No. 38 39 40 41 42 Symbol AMCY tMCR tMCF tMCH tMCL Parameter Master Clock Accuracy Rise Time of Clock Fall Time of Clock MCLK High Pulse Width MCLK Low Pulse Width 97 97 Min -100 Typ Max +100 15 15 Units ppM ns ns ns ns
Notes: 1. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock frequency is 4.096 MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 256 kHz. 2. tTSO is defined as the time at which the output achieves the open circuit condition. 3. There is a special conflict detection circuitry that will prevent high-power dissipation from occurring when the DX pins of two QSLAC-NP devices are tied together and one QSLAC-NP device starts to transmit before the other has gone into a high-impedance state.
SWITCHING WAVEFORMS Input and Output Waveforms for AC Tests
2.4
2.0 0.8
Test Points
2.0 0.8
19256A-015
0.45
Master Clock Timing
38
41
VIH VIL
42 40 39
20031A-005
SLAC Products
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Control Interface (Input Mode)
1
2
5
CCLK
VIH VIL
VIH VIL
3 7 9 4 6
CSN
8
10
11
CI
Data Valid
Data Valid
Data Valid
12
Latch Outputs (Internal)
Data Valid
Data Valid
20013A-017
Control Interface (Output Mode)
VIH CCLK
13
VIL
14
16
CSN
15
20
17
18 19
CO
Three-State VOH VOL
Data Valid
Data Valid
Data Valid
Three-State
20013A-018
22
Am79Q4457/5457 Data Sheet
PCM Highway Timing (Short Frame Sync Mode)
Same point in previous frame
28
Time Slot Zero Clock Slot Zero
21 25 24
VIH PCLK VIL
23 26 27 22
FSX/FSR
29 30
TSCA
31 33 32
VOH DXA
First Bit VOL
34 35
VIH DRA First Bit Second Bit VIL
20031A-006
SLAC Products
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PCM Highway Timing (Long Frame Sync Mode)
28 25 PCLK 21 24
1
26 26
2
23
3
22 27
4
5
8
9
FSX/FSR 30
36 TSCA
37 37 DXA 32
33
First Bit
2
3
34
4
35
5
8
DRA
First Bit
2
3
4
5
8
20031A-007
OPERATING THE QSLAC-NP DEVICES
The following describes the operation of the four independent channels of the QSLAC-NP device. The description is valid for Channel 1, 2, 3, or 4; consequently, the channel subscripts have been dropped. For example, VOUT refers to either VOUT1, VOUT2, VOUT3, or VOUT4. Also, the additional features provided by the Am79Q4457 device (over the Am79Q5457 device) are described. Power-Up Sequence The signal pins have protection diodes to V CC and ground; consequently, if the signal leads are connected before VCC or ground, the transient signal current must be limited in order to prevent latch-up of the part. Following initial power application, it is necessary to place all channels in an inactive state. This ensures a hardware reset is initiated upon activation of any channel. For these reasons, the following power-up sequence is recommended: 1. VCC and ground 2. Signal connections 3. In the case of device Am79Q5457, take pins PDN1, PDN2, PDN3, and PDN4 to a logic high state, (device Am79Q4457 will default to all channels powered down). Following any subsequent occurrence of all channels inactivated, upon activation of any channel, a hardware reset will be initiated. Master Clock The master clock, MCLK, is used to derive internal clocks and timing signals. The master clock must be essentially jitter free and it must be an integer multiple of the frame sync frequency. The allowed frequencies for MCLK are 1.536 MHz, 1.544 MHz, 2.048 MHz, and 4.096 MHz. Internal circuitry determines the MCLK frequency based on the FSX inputs and adjusts the internal timing circuitry automatically.
24
Am79Q4457/5457 Data Sheet
CONTROL OF THE Am79Q4457/5457 QSLAC-NP DEVICES
The QSLAC-NP device is controlled either directly via device pins (PDN and A/ for the Am79Q5457 device) or through the serial control interface (Am79Q4457 device).
Serial Control Register (Am79Q4457 Device Only)
The Am79Q4457 device provides an A-law/-law select pin in the same manner as the Am79Q5457 device. The Am79Q4457 QSLAC-NP device provides several additional features over the Am79Q5457 device. The Am79Q4457 device provides the ability to program three different gain levels on both the transmit and receive side of each channel. One of two balance impedances (connected externally) can be selected on a per-channel basis with the Am79Q4457 device. The individual channels of the Am79Q4457 device can be powered down. Control of the power-down function is through the per-channel serial control register. Each channel of the Am79Q4457 QSLAC-NP device contains a serial shift register and latch in order to easily control the additional functionality of the device. The registers are connected as shown in Figure 7. The channel control registers are enabled for reading or writing by their corresponding Chip Select (CSn) signal. Data on the Control Input (CI) is shifted into the enabled register by the Control Clock (CCLK). Each channel register contains a Balance Network Select (BNS1) bit, two Receive Gain Select (RGS1/2) bits, two Transmit Gain Select (TGS1/2) bits and a Power-Down (PDN) bit. As indicated in Figure 7, the PDN bit is the most significant bit in the register and is shifted in first. The balance network select bit is the least significant bit and is shifted in last. The Balance Network is selected with the BNS1 bit, where: 0 --Selects the balance network connected to I1IN of the channel. 1 --Selects the balance network connected to I2IN of the channel. Transmit and Receive gains are selected according to the TGS1/2 and RGS1/2 bits as shown in the gain select tables, Table 2 and Table 3. The register layout for each channel is as follows:
Parallel Control (Am79Q5457 Device)
The Am79Q5457 QSLAC-NP device is controlled directly via device pins. There are two different control input pins on the Am79Q5457 device, an A-law/-law select (A/) pin and four power-down (PDN) pins, one per channel. Logic levels on these pins determine the operating state of the individual channels, active (powerup) or idle (power-down), and A-law or -law operation. Each channel of the QSLAC-NP device can operate in either the Powered-Up (Active) or Powered-Down (Standby) mode. In the Active mode, individual channels of the QSLACTM device are able to transmit and receive PCM and analog information. The Active mode is required when a telephone call is in progress. The Standby mode requires the least amount of power per channel and should be used whenever the line circuit is on hook and a telephone call is not in progress. Power Down Input (PDN n): 0 -- Powers the channel up 1 -- Powers the channel down A-Law/-Law Select Input (A/): 0 -- Selects -law operation 1 -- Selects A-law operation
PDN Note: PDN is loaded first.
RSVD
RSVD
TGS2
RGS2
TGS1
RGS1
BNS1
SLAC Products
25
CI CO CS1 CCLK CO CS1 CCLK Qh PDN1 Qg RSVD Qf RSVD Shift Register and Latch Channel 1 Qe TGS21 Qd Qc Qb CI Qa
RGS21 TGS11 RGS11 BNS11
CS2
CO CS2 CCLK Qh PDN2 Qg RSVD Qf
Shift Register and Latch Channel 2 Qe Qd Qc Qb
CI Qa
RSVD TGS22
RGS22 TGS12 RGS12 BNS12
CS3
CO CS3 CCLK Qh PDN3 Qg Qf
Shift Register and Latch Channel 3 Qe Qd Qc Qb
CI
Qa
RSVD RSVD
TGS23 RGS23
TGS13 RGS13 BNS13
CS4
CO CS4 CCLK Qh Am79Q4457 PDN4 Qg Qf
Shift Register and Latch Channel 4 Qe Qd Qc Qb
CI
Qa
RSVD RSVD
TGS24 RGS24
TGS14 RGS14 BNS14
20031A-008
Figure 7. Am79Q4457 QSLAC-NP Device Serial Control Interface
I1IN *I2IN
BNS1
ADC REF Select IREF1 *IREF2 *IREF3 VREF1 *VREF2 *VREF3 REF Select
Decimator TGS1* TGS2*
LPF & HPF
Compressor
PCM Interface
DXA
A/
RGS1* RGS2* Interpolator LPF Expander PCM Interface DRA
VOUT
DAC
20031A-009
*Am79Q4457 device only
Figure 8. QSLAC-NP Device Block Diagram
26
Am79Q4457/5457 Data Sheet
Power Down (PDNn): 0 -- Powers the channel up 1 -- Powers the channel down Reset State All four channel control registers are reset by the application of power. This resets the QSLAC-NP device to the following state: TGS, RGS, BNS = 0 and PDN = 1 for all four channels.
Receive Signal Processing Digital data received from the PCM highway is expanded from A-law or -law, filtered, converted to analog, and passed to the VOUT pin. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The Low-Pass Filter band limits the signal. The interpolator increases the sampling rate prior to D/A conversion. Receive PCM Interface The receive PCM interface receives 1 byte (8 bits) every 125 s from the PCM highway. The data is received under control of the receive logic and synchronized by the receive frame synchronization signal (FSR N). The receive frame sync (FSXN) pulse identifies the receive time slot of the PCM frame for Channel N. The QSLAC-NP devices (Am79Q4457/5457) are compatible with both a long- and a short-frame synchroniz a t i o n s i g n a l . S e e t h e P C M i n t e r fa c e t i m in g specifications (20 to 24) for more details. The receive PCM data is expanded by the A-law/-law expansion logic, and passed on to the signal processor. Speech Coding The A/D and D/A conversions follow either the A-law or the -law standard as defined in ITU-T Recommendation G.711. A-law or -law operation is programmed using the A-law/-law program (A/) pin. Alternate bit inversion is performed as part of the A-law coding. Short-Frame Sync Mode If each of the transmit (FSXN) frame sync pulses overlap either one or two negative-going transitions of PCLK, the part operates in what is called Short-Frame Sync mode. In this mode, the part operates like a DSLAC, ASLAC, or QSLAC device programmed for time slot 0, clock slot 0, and XE=1. If a frame sync overlaps two transitions, the first of these transitions defines the beginning of the time slot. The first positive PCLK transition after the beginning of a transmit time slot enables the DXA output with the sign bit as the first output. It also drives the TSCA output Low. The succeeding seven positive clock transitions shift out the remainder of the data, and the eighth negative transition tri-states DXA and turns off TSCA. During the latter part of each output period, the transmit data is held by a weak driver in order to minimize bus contention if one time slot starts before the preceding one ends. The first negative PCLK transition after the beginning of a receive time slot latches in the first data bit (sign bit) from the DRA input. The succeeding seven negative clock transitions shift in the remainder of the data.
Signal Processing
Overview of Digital Filters Several elements in the signal processing section of the Am79Q4457 device provide user options. These options allow the user to optimize the performance of the QSLAC-NP device for the application. Figure 8 shows the QSLAC-NP device signal processing section and indicates the user-programmable blocks, the reference current selector, the reference voltage selector, the balance network selector, and the A-law/-law selector. The High-Pass Filter (HPF) and the LowPass Filter (LPF) sections of the signal processor are implemented in the digital domain. The advantages of digital filters are high reliability, no drift with time or temperature, unit-to-unit repeatability, and superior transmission performance. Transmit Signal Processing In the transmit path, the analog input signal (IIN) is A/D converted, filtered, compressed, and made available to the PCM highway in A-law or -law form. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The decimator reduces the high input sampling rate to 16 kHz for input to the Low-Pass and High-Pass Filters. The High-Pass Filter rejects low frequencies such as 50 Hz or 60 Hz and the Low-Pass Filter limits the voice band to 3400 Hz. Transmit PCM Interface The transmit PCM interface receives 1 byte (8 bits) every 125 s from the A-law/-law compressor. The data is transmitted onto the PCM highway under control of the transmit logic, synchronized by the Transmit Frame Synchronization signal (FSXN). The frame synchronization signal (FSX N) identifies the transmit time slot of the PCM frame for Channel N. The QSLAC-NP devices (Am79Q4457/5457) are compatible with both a long- and a short-frame synchronization signal. See the PCM interface timing specifications (20 to 24) for more details. While the PCM data is output on the DXA port, the TSCA buffer control signal is Low.
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Long-Frame Sync Mode If each of the transmit (FSXN) frame sync pulses overlap three or more negative-going transitions of PCLK, the part operates in what is called Long-Frame Sync mode. The time slot begins at the first point where both frame sync and PCLK are High. The beginning of a transmit time slot enables the DXA output with the sign bit as the first output. It also drives the TSCA output Low. The succeeding seven positive clock transitions shift out the remainder of the data. The eighth negative transition of PCLK or the end of FSX, whichever comes later, tri-states DXA and turns off TSCA. If FSX extends beyond the eighth PCLK edge, the eighth bit is held at DXA. During the latter part of each output period, the transmit data is held by a weak driver in order to minimize bus contention if one time slot starts before the preceding one ends. The first negative PCLK transition after the beginning of a receive time slot latches in the first data bit (sign bit) from the DRA input. The succeeding seven negative clock transitions shift in the remainder of the data.
SETTING GAIN LEVELS Gain Settings for the Am79Q4457 Device
The possible transmit and receive gain levels are set once for the four channels via three reference currents and three reference voltages (see Figure 9a). The three IREF outputs are biased at the internal reference voltage so that a resistor placed from the output to ground sets up a reference current in the device. These reference currents are buffered and provided as inputs to the 3-to-1 analog multiplexers, one per channel. One of three reference currents can be selected for use by the transmit A/D converter. Each reference current set up by the user corresponds to one transmit gain setting. The transmit gain is a function of the input resistor RTX and the reference resistor R REF as shown in Figure 9a and Table 2. In much the same way, three reference voltages are set up, one internally and two externally, as shown in Figure 9a. These voltages are internally buffered and provided to the 3-to-1 analog multiplexers, one per channel. One of three reference voltages can be selected and provided to the receive D/A converter for use in decoding the data. Each reference voltage level corresponds to a receive gain setting. The receive gain is a function of the internally generated reference voltage V REF1 and the scaled version V REF2 or V REF3, as shown in Figure 9a and Table 3. One of two balance networks per channel is selected via the serial control register. As shown in Figure 9a, this is achieved by providing two inputs to the transmit A/D converter and using a 2-to-1 analog multiplexer to select the desired input.
APPLICATIONS
The QSLAC-NP device family consists of two devices, the Am79Q5457 device and the Am79Q4457 device. The Am79Q5457 device is a four-channel Codec/Filter device with eight frame synchronization inputs, two per channel. Both the Am79Q4457 and Am79Q5457 devices are A-law or -law c om patible. The Am79Q4457 device provides all the functions of the Am79Q5457 device and the additional functions of selecting transmit and receive gain levels and balance networks on a per-channel basis. If the application requires a fixed transmit and receive gain level and one balance network, the Am79Q5457 device is ideal. If the application requires more than one gain setting or balance network, the Am79Q4457 device is ideal. If full programmability of gain, frequency response, balance impedance, input impedance, and time slot assignment are required, then the Am79Q02/021/031 Quad SLAC (QSLAC) device is ideal. The QSLAC-NP device performs the Codec/Filter function for four telephone lines. It interfaces to the telephone lines through four Legerity SLIC devices as shown in Figure 10 and Figure 11. The QSLAC-NP device may require an external buffer to drive transformer SLICs. Connection to a PCM back plane is implemented by means of a simple buffer IC. See Figure 10 and Figure 11. Several QSLAC-NP devices can be tied together in one bus interfacing the back plane through a single buffer. An intelligent bus interface chip is not required because each QSLAC-NP device provides its own buffer control (TSCA).
Table 2. Transmit Gain Select (Am79Q4457 Device Only) Transmit Gain Select 1 (TGS1) and Transmit Gain Select 2 (TGS2)
TGS2 0 TGS1 0 A-to-D Gain
3*R REF1 Gt = Gt1 = --------------------------Rb TX 3 * (R +R ) REF2A REF2B Gt = Gt2 = ------------------------------------------------------------------Rb TX 3 * ( R REF3A + R REF3B ) Gt = Gt3 = ------------------------------------------------------------------Rb TX
0
1
1
0
1
1
Do Not Use
See Figure 9. "b" represents the value of BNS1.
28
Am79Q4457/5457 Data Sheet
Gain Settings for the Am79Q5457 Device
Table 3. Receive Gain Select (Am79Q4457 Device Only) Receive Gain Select 1 (RGS1) and Receive Gain Select 2 (RGS2)
RGS2 0 RGS1 0 D-to-A Voltage Reference
Gr = Gr1 = 1
0 1
The transmit and receive gains for each of the four channels are set for the Am79Q5457 device similarly to those of the Am79Q4457 device. The Am79Q5457 device has only one IREF output and one VREF input as shown in Figure 9b, and only one gain setting is available. The transmit gain is a function of the reference current set up by the R REF1 resistor and by the R TX1 input resistor, and is set by the following equation: 3 * R REF1 Gt = ---------------------R1 TX1 The receive gain Gr through the QSLAC-NP device is equal to 1 and is not adjustable. However, this gain typically is set by choice of component values in the SLIC portion of the circuit.
1.4 * R REF2A Gr = Gr2 = -----------------------------------------R REF2A + R REF2B 1.4 * R REF3A Gr = Gr3 = -----------------------------------------R REF3A + R REF3B
Do Not Use
1
0
1 Note: 0.4 Gr 1
1
Am79Q4457JC to SLIC VTX R1TX1 R2TX1 C1TX1 l1IN1 l2IN1
C2TX1
A/D 1
IREF
2
3
4
BNS1
I1
IO 3 to 1 Multiplexer I2 I3 IREF1 IREF2 IREF3
TGS1 TGS2 IREF1 VREF to IREF IREF2 IREF3 RREF1 RREF2A RREF3A CFIL RREF2B RREF3B
Bal Net 1 * Bal Net 1
Bal Net 2 * Bal Net 2 V1 3 to 1 Multiplexer Vo VREF VOUT1
VREF1 V2 V3 RGS1 RGS2 2 3
VREF1 VREF2 VREF3
to SLIC RSN
RRX1
CRX1
D/A 1
4
20031A-010
*Optional Bal Net Connection
Figure 9a. Am79Q4457JC Device (Channel 1 Shown)
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Am79Q5457 to SLIC VTX R1TX1 C1TX1 I1 IN1
A/D 1
IREF
2
3
4
* Bal Net Bal Net
VREF to IREF
IREF1
RREF1
VREF1
CFIL
to SLIC RSN
VREF RRX1 CRX1 VOUT1
D/A
*Optional Bal Net Connection
20031A-012
Figure 9b. Am79Q5457 Device (Channel 1 Shown)
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Am79Q4457/5457 Data Sheet
R1TX1 VTX
C1TX1 C2TX1 I1IN1 I2IN1 IREF1 IREF2 Am79Q4457JC QSLAC-NP IREF3 VREF1 VREF2 VREF3 C2TX2 I1IN2 I2IN2 A/ VCCD RPULL DXA TSCA VOUT2 CRX2 DRA PCLK C2TX3 I1IN3 I2IN3 FSRn FSXn MCLK
P C M
RREF1 RREF2A RREF3A CFIL RREF2B RREF3B
SLIC1 ZT1
R2TX1
Bal Net 1
Bal Net 2
Bal Net 1
*
Bal Net 2
*
RRX1 RSN C RX1 R1TX2 VTX C1TX2 VOUT1
VCCD
SLIC2 ZT2
R2TX2
*
Bal Net 1 Bal Net 2 Bal Net 1 Bal Net 2
*
RRX2 RSN R1TX3 VTX C1TX3
B A C K P L A N E
SLIC3 ZT3
R2TX3
Bal Net 1
Bal Net 2
Bal Net 1
*
Bal Net 2
*
RRX3 RSN C RX3 R1TX4 VTX C1TX4 C2TX4 R2TX4 ZT4 RRX4 RSN To SLICs Analog GND Analog VCC CRX4 AGND VCCA DGND VCCD To other QSLAC-NP Devices VOUT4 I1IN4 I2IN4 VOUT3 CCLK CI CO CS1 CS2 CS3 CS4
C O N T R O L
SLIC4
Bal Net 1
Bal Net 2
Bal Net 1
*
Bal Net 2
*
13 k R REF1 26 k 13 k R REF2A + RREF2B 26 k 13 k R REF3A + RREF3B 26 k RPULL = 360 5% R1TX1, R1TX2, R1TX3, R1TX4 - See Transmit Gain Select 1, Table 2 R2TX1, R2TX2, R2TX3, R2TX4 - See Transmit Gain Select 2, Table 2 ZT1-4 = SLIC Programming Impedance - See SLIC Data Sheet
Digital Digital GND VCC
20031A-011
RRX1, RRX2, R RX3, RRX4 - See SLIC Data Sheet CFIL = 0.1 F 20%, X7R C1TX1, C1TX2, C1TX3, C1TX4 = 0.1 F 20%, X7R, typ. C2TX1, C2TX2, C2TX3, C2TX4 = 0.1 F 20%, X7R, typ. CRX1, CRX2, C RX3, CRX4 = 0.1 F 20%, X7R, typ. *Optional Balance Network connection.
Figure 10. Am79Q4457JC Device
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R1TX1 VTX
C1TX1 I1IN1 IREF1 RREF1
*
SLIC1 ZT1 Bal Net Bal Net Am79Q5457 QSLAC-NP CFIL
RSN R RX1 R1TX2 VTX C1TX2 C RX1
VOUT1
VREF1
I1IN2
VCCD A/ VCCD RPULL DXA TSCA
P C M
*
SLIC2 ZT2 Bal Net Bal Net
RSN RRX2 R1TX3 VTX C1TX3 CRX2
VOUT2
B
DRA PCLK
A C K P L A N E
I1IN3
FSRn FSXn MCLK
*
SLIC3 ZT3 Bal Net Bal Net
RSN RRX3 R1TX4 VTX C1TX4 C RX3
VOUT3
CCLK
C O N
I1IN4
PDN1 PDN2 PDN3 PDN4
T R O L
*
SLIC4 ZT4 Bal Net Bal Net
RSN RRX4 Analog GND Analog VCC To SLICs CRX4
VOUT4
AGND VCCA
DGND
VCCD To other QSLAC-NP Devices
Digital Digital GND VCC 13 k R REF1 26 k RPULL = 360 5% R1TX1, R1TX2, R1TX3, R1TX4 - See Transmit Gain Select 1, Table 2 RRX1, RRX2, RRX3, RRX4 - See SLIC Data Sheet ZT1-4 = SLIC Programming Impedance - See SLIC Data Sheet
20031A-011
CFIL = 0.1 F 20%, X7R, typ. C1TX1, C1TX2, C1TX3, C1TX4 = 0.1 F 20%, X7R, typ. CRX1, CRX2, C RX3, CRX4 = 0.1 F 20%, X7R, typ. *Optional Balance Network connection.
Figure 11. AM79Q5457JC Device
32
Am79Q4457/5457 Data Sheet
Calculation of Balance Network
Th e balan ce fu nctio n is implemen ted with the QSLAC-NP device by connecting an external balance network (ZBAL) between the VOUT and IIN terminals. Assuming the uncancelled receive path signal, which appears in the SLIC's transmit path, is out of phase with the originating receive path (the QSLAC-NP device's VOUT) signal, this external network will provide a path for the needed cancellation. The IIN terminal is a current summing node and is a virtual ac ground, simplifying the implementation of this balance function. In many cases, this balance network can be a single resistor, and in other cases, depending on the balance impedance and the transfer characteristics of the SLIC, it may be necessary to add a capacitor. Complete definition of the balance network is dependent on the SLIC and the balance impedance and, as such, cannot be completely defined within this document. However, a general method of calculation can be described as follows: Figure 12 shows a simplified equivalent circuit of a SLIC, along with the balance impedance and interconnecting networks to the QSLAC device. A SLIC circuit can be represented by four gain parameters (G-parameters), where each of these blocks represents a complex transfer function: G24 is the gain from the tip/ring two-wire port toward the four-wire port; G42 is the unterminated gain from the four-wire port toward the two-
wire port; ZSL is the two-wire SLIC impedance; and G44 is the gain that appears from the four-wire input toward the four-wire output with the two-wire por t shorted. Considering only the SLIC, plus the externally connected balance impedance, ZTERM, any signal that is presented to the SLIC's four-wire input will have a representation at the V TX four-wire output defined by the SLIC's G-parameters and the ZBAL termination. G44L (G44 loaded) can then be defined as the four-wire to four-wire gain through the SLIC when loaded by Z TERM. The RTX resistor establishes the transmit path gain by translating the SLIC's VTX output voltage so that it appears as a current into the QSLAC-NP device's IIN current input and, as such, provides the scaling necessary to define the transmit gain. If the G44L gain is then known, the balance network can be calculated as follows: R TX 1 Z BAL = ------------G44L G44L is a complex value, which implies that ZBAL must also be complex. However, in many cases, satisfactory balance over the voice band can be achieved by using only one resistor. This configuration assumes that R TX * C TX and R RX * C RX have time constants greater than 10 ms. If that is not true, the balance network should be moved to the QSLAC-NP device side of the coupling capacitors and should also have a capacitor placed in series with the network.
SLIC G24 VTX RTX CTX
QSLAC-NP device IIN
ZBAL G44 TIP/RING ZSL ZTERM G42 CRX RRX *
Optional ZBAL Placement VOUT
Note: *G-parameter model includes the R RX resistor inside SLIC.
Figure 12. Balance Network
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CONSIDERATIONS FOR CONNECTION TO SLICS
There are several factors to consider with the connection method used between the QSLAC-NP device and the SLIC. The RTX resistor controls the transmit path gain by establishing the current into the QSLAC-NP device's IIN pin. The RRX resistor controls the receive path gain in conjunction with the other SLIC circuit elements, by establishing the current into the SLIC's RSN pin. The balance network provides a path for passing a representative portion of the receive path signal back into the transmit path for setting the transhybrid balance. Additionally, the capacitors used to provide DC isolation between the SLIC and the QSLAC device also have an effect on system performance. Figure 13 shows the connection scheme as described earlier in this document. An alternative connection scheme is shown in Figure 14. The only difference in these connection methods is the placement of the balance network, but in each case, there are specific factors to be considered.
Placement of the Balance Network
The only difference in the two circuit connection methods shown in Figure 13 and Figure 14 is the placement of the ZBAL network. Both methods have benefits and both have different issues to consider for the overall design performance. Depending on the SLIC and the termination impedance for which balance is specified, the circuit of Figure 13 may reduce the complexity needed of the ZBAL network so that only a single resistor is required. This would be especially true of short loop applications where the actual termination in service is a relatively constant resistance. Since in this configuration the CTX and C RX capacitors are both external to the echo loop being canceled by ZBAL, the frequency dependent echo responses due to their effects need not be considered. In Figure 14, however, the capacitors are in series with the receive and transmit paths. Since the resistor values are unequal, the frequency rolloff characteristics will likely be unequal without corresponding changes of the C RX and CTX values. This frequency dependent characteristic now implies that the ZBAL network also contains the necessary complex components to maintain proper phase response.
Effects of CRX and CTX Capacitors
While the purpose of the CRX and CTX capacitors is to provide DC isolation, they have a finite impedance that is a function of frequency. Nominal values of the RRX and RTX resistors typically are large compared to the capacitors' impedances at most voice band frequencies; but at lower frequencies, the capacitor impedances may have an effect. For example, a 0.1 uF capacitor at 1000 Hz has an impedance of 1592 , but at 300 Hz, that impedance increases to 5305 . While this is still a small change compared to the resistor values, it is not this change alone that may need to be considered. For example, in Figure 14, the I IN input pin of the QSLAC-NP device has two sources feeding it: One is the ZBAL balance network, and the other is the series path of RTX and CTX that are fed from the SLIC's VTX output. The IIN pin is a virtual ground, so currents from the two source paths do not effect one another. However, in Figure 13, the ZBAL network is connected between the C TX and R TX components. So long as the capacitor's impedance is low, it has little effect on signals from either ZBAL or from RTX, and both of those signal's currents continue to flow into the IIN virtual ground. As the capacitor's impedance begins to become significant with lower frequencies, a portion of the transmit path current from RTX will begin to flow into ZBAL toward the low impedance output of the QSLAC-NP device's VOUT pin. The net effect is a low frequency attenuation to the transmit path signal. A similar situation also exists in the receive path.
SLIC Connection Consideration Summary
Two different interconnection schemes are described in Figure 13 and Figure 14. The configuration shown in Figure 13 may simplify the ZBAL network, or possibly even remove the need for it to contain capacitive elements, provided that the balance termination impedance and SLIC characteristics are compatible. It may be necessary in this configuration to use larger C RX or CTX capacitor values if frequency response at very low frequencies becomes a concern. The configuration shown in Figure 14 may allow smaller transmit and receive path coupling capacitors, but may require a slightly more complex ZBAL network. Variations of the configurations from either of these figures are also possible. In any case, the designer must consider all of the effects of SLIC characteristics, balance termination impedance values, coupling capacitor values, and balance network values.
34
Am79Q4457/5457 Data Sheet
SLIC RTX VTX CTX
QSLAC-NP device
IIN
ZT
ZBAL
RSN RRX CRX
VOUT
Figure 13. Balance Network Connection
SLIC RTX VTX CTX
QSLAC-NP device
IIN
ZT
ZBAL
RSN RRX CRX
VOUT
Figure 14. Alternate Balance Network Connection
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PHYSICAL DIMENSIONS PL032
Dwg rev AH; 10/99
36
Am79Q4457/5457 Data Sheet
PL044
Dwg rev. AN; 8/99
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PQT044
Dwg rev AS; 08/99
38
Am79Q4457/5457 Data Sheet
REVISION SUMMARY Revision B to Revision C
* * The physical dimensions (PL032, PL044 and PQT044) were added to the Physical Dimension section. Updated the Pin Description table to correct inconsistencies.
Revision C to Revision D
* All the physical dimensions were updated.
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Notes:
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Notes:
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