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FEATURES 3.0 GHz Fractional-N/1.2 GHz Integer-N 2.7 V to 3.3 V Power Supply Separate V P Allows Extended Tuning Voltage to 5 V Programmable Dual Modulus Prescaler RF: 4/5, 8/9 IF: 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents 3-Wire Serial Interface Digital Lock Detect Power-Down Mode Programmable Modulus on Fractional-N Synthesizer Trade-Off Noise versus Spurious Performance APPLICATIONS Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications Test Equipment CATV Equipment
Dual Fractional-N/Integer-N Frequency Synthesizer ADF4252
GENERAL DESCRIPTION
The ADF4252 is a dual fractional-N/integer-N frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Both the RF and IF synthesizers consist of a low noise digital PFD (phase frequency detector), a precision charge pump, and a programmable reference divider. The RF synthesizer has a - -based fractional interpolator that allows programmable fractional-N division. The IF synthesizer has programmable integer-N counters. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2 VDD3 DVDD VP1 VP2 RSET
ADF4252
REFERENCE 4-BIT R COUNTER
REFIN
2 DOUBLER
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CPRF
REFOUT LOCK DETECT RFINA RFINB
MUXOUT
OUTPUT MUX
FRACTIONAL N RF DIVIDER CLK DATA LE 24-BIT DATA REGISTER INTEGER N IF DIVIDER
IFINB IFINA
2 DOUBLER
15-BIT R COUNTER
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CPIF
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
AGND1
AGND2
DGND
CPGND1
CPGND2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
V 3 3 R referred ,T T ADF4252-SPECIFICATIONS1 (V 1==2.7 k2 =, VdBm = DV = to V50 10%,=DV
DD DD DD DD SET A
DD
MIN
< VP1, VP2 < 5.5 V, GND = 0 V, to TMAX, unless otherwise noted.)
Parameter RF CHARACTERISTICS RF Input Frequency (RFINA, RFINB)2 RF Input Sensitivity RF Input Frequency (RFINA, RFINB)2 RF Phase Detector Frequency Allowable Prescaler Output Frequency IF CHARACTERISTICS IF Input Frequency (IFINA, IFINB)2 IF Input Sensitivity IF Phase Detector Frequency Allowable Prescaler Output Frequency REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Current REFIN Input Capacitance CHARGE PUMP RF ICP Sink/Source IF ICP Sink/Source High Value Low Value High Value Low Value
B Version 0.25/3.0 -10/0 0.1/3.0 30 375 50/1200 -10/0 55 150 250 0.5/VDD1 100 10 4.375 625 5 625 1 2 1.5/1.6 2 2 2 1.35 0.6 1 10 VDD - 0.4 0.4 2.7/3.3 VDD1 VDD1/5.5 13 10 4 1 -141 -90 -95 -103
Unit GHz min/max dBm min/max GHz min/max MHz max MHz max MHz min/max dBm min/max MHz max MHz max MHz max V p-p min/max A max pF max mA typ A typ mA typ A typ nA typ % typ k typ % typ % typ % typ V min V max A max pF max V min V max V min/V max V min/V max mA typ mA typ mA typ A typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ
Test Conditions/Comments
Input Level = -8/0 dBm min/max Guaranteed by Design
Guaranteed by Design
For f < 10 MHz, use dc-coupled square wave (0 to VDD). AC-coupled. When dc-coupled, use 0 to VDD max (CMOS compatible).
See Table V See Table IX
ICP Three-State Leakage Current RF Sink and Source Current Matching RSET Range IF Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD1, VDD2, VDD3 DVDD VP1, VP2 IDD3 Power-Down Mode RF NOISE AND SPURIOUS CHARACTERISTICS Noise Floor In-Band Phase Noise Performance4 Lowest Spur Mode Low Noise and Spur Mode Lowest Noise Mode Spurious Signals
0.5 V < VCP < VP - 0.5 See Table V 0.5 V < VCP < VP - 0.5 VCP = VP /2
IOH = 0.2 mA IOL = 0.2 mA
RF + IF RF Only IF Only
16 mA max 13 mA max 5.5 mA max
@ 20 MHz PFD Frequency @ VCO Output RFOUT = 1.8 GHz, PFD = 20 MHz RFOUT = 1.8 GHz, PFD = 20 MHz RFOUT = 1.8 GHz, PFD = 20 MHz See Typical Performance Characteristics
NOTES 1 Operating Temperature Range (B Version): -40C to +85C. 2 Use a square wave for frequencies less than f MIN. 3 RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, V DD = 3 V, VP1 = 5 V, and VP2 = 3 V. 4 The in-band phase noise is measured with the EVAL-ADF4252EB2 evaluation board and the HP5500E phase noise test system. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). fOUT = 1.74 GHz, fREF = 20 MHz, N = 87, Mod = 100, Channel Spacing = 200 kHz, V DD = 3.3 V, and VP = 5 V. Specifications subject to change without notice.
-2-
REV. B
ADF4252 TIMING CHARACTERISTICS* unless otherwise noted.)
Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 10 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min
(VDD1 = VDD2 = VDD3 = DVDD = 3 V
10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V,
Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width
*Guaranteed by design, but not production tested.
t4
CLOCK
t5
t2
DATA DB23 (MSB) DB22
t3
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
LE
t1 t7
t6
LE
Figure 1. Timing Diagram
REV. B
-3-
ADF4252
ABSOLUTE MAXIMUM RATINGS 1, 2 ORDERING GUIDE Mode Temperature Range Package Option*
VDD1, VDD2, VDD3, DVDD to GND3 . . . . . . . . -0.3 V to +4 V REFIN, RFINA, RFINB to GND . . . . . . -0.3 V to VDD + 0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.8 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . . -3.3 V to +3.5 V Digital I/O Voltage to GND . . . . . . . . -0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C CSP JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 122C/W Soldering Reflow Temperature Vapor Phase (60 sec max) . . . . . . . . . . . . . . . . . . . . . 240C IR Reflow (20 sec max) . . . . . . . . . . . . . . . . . . . . . . . 240C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of <2 k, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = CPGND1, AGND1, DGND, AGND2, and CPGND2.
(TA = 25C, unless otherwise noted.)
ADF4252BCP ADF4252BCP-REEL ADF4252BCP-REEL7 EVAL-ADF4252EB1 EVAL-ADF4252EB2
*CP = Chip Scale Package
-40C to +85C -40C to +85C -40C to +85C
CP-24 CP-24 CP-24
PIN CONFIGURATION
VP1 VDD1 VDD3 VDD2 VP2 CPIF
CPRF 1 CPGND1 2 RFINA 3 RFINB 4 AGND1 5 MUXOUT 6
24 23 22 21 20 19
18 17 16 15 14 13
PIN 1 INDICATOR
ADF4252
TOP VIEW (Not to Scale)
CPGND2 DVDD IFINA IFINB AGND2 RSET
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4252 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-4-
REFIN 7 REFOUT 8 DGND 9 CLK 10 DATA 11 LE 12
REV. B
ADF4252
PIN FUNCTION DESCRIPTIONS
Mnemonic CPRF CPGND1 RFINA RFINB AGND1 MUXOUT REFIN REFOUT DGND CLK DATA LE RSET
Function RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO. RF Charge Pump Ground. Input to the RF Prescaler. This small signal input is normally taken from the VCO. Complementary Input to the RF Prescaler. Analog Ground for the RF Synthesizer. This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference frequency to be accessed externally. Reference Input. This is a CMOS input with a nominal threshold of VDD /2 and an equivalent input resistance of 100 k. This input can be driven from a TTL or CMOS crystal oscillator. Reference Output. Digital Ground for the Fractional Interpolator. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the seven latches, the latch being selected using the control bits. Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship between ICP and RSET is
1.6875 RSET Therefore, with RSET = 2.7 k, ICPmin = 0.625 mA. ICPmin =
AGND2 IFINB IFINA DVDD CPGND2 CPIF V P2 VDD2 VDD3 VDD1 V P1 Ground for the IF Synthesizer. Complementary Input to the IF Prescaler. Input to the IF Prescaler. This small signal input is normally taken from the IF VCO. Positive Power Supply for the Fractional Interpolator Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. DVDD must have the same voltage as VDD1, VDD2, and VDD3. IF Charge Pump Ground. IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO. IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. This voltage should be greater than or equal to VDD2. Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. VDD2 has a value 3 V 10%. VDD2 must have the same voltage as VDD1, VDD3, and DVDD. Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. VDD3 has a value 3 V 10%. VDD3 must have the same voltage as VDD1, VDD2, and DVDD. Positive Power Supply for the RF Analog Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. VDD1 has a value 3 V 10%. VDD1 must have the same voltage as VDD2, VDD3, and DVDD. RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. This voltage should be greater than or equal to VDD1.
REV. B
-5-
ADF4252
VDD1 VDD2 VDD3 DVDD VP1 VP2 RSET
ADF4252
REFERENCE 4-BIT R COUNTER
REFIN
2 DOUBLER
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CPRF
REFOUT VDD HIGH Z OUTPUT MUX DGND VDD RDIV NDIV THIRD ORDER FRACTIONAL INTERPOLATOR N COUNTER RFINA RFINB LOCK DETECT
MUXOUT
CLK DATA LE
24-BIT DATA REGISTER
FRACTION REG
MODULUS REG
INTEGER REG
6-BIT IF A COUNTER IF PRESCALER 12-BIT IF B COUNTER IFINB IFINA
2 DOUBLER
15-BIT R COUNTER
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CPIF
AGND1
AGND2
DGND
CPGND1
CPGND2
Figure 2. Detailed Functional Block Diagram
-6-
REV. B
Typical Performance Characteristics-ADF4252
TPC plots 1 to 12 attained using EVAL-ADF4252EB1; measurements from HP8562E spectrum analyzer.
0 -10 -20 -30
OUTPUT POWER (dB)
0 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz REFERENCE LEVEL = - 4.2dBm -10 -20
OUTPUT POWER (dB)
-30 -40 -50 -60 -70 -80 -90
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz
REFERENCE LEVEL = - 4.2dBm
-40 -50 -60 -70 -80 -90 - 99.19dBc/Hz
-50dBc@ 100kHz
-100 -2kHz -1kHz 1.7518GHz FREQUENCY 1kHz 2kHz
-100 -400kHz -200kHz 1.7518GHz FREQUENCY 200kHz 400kHz
TPC 1. Phase Noise Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution
TPC 4. Spurious Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution
0 -10 -20
OUTPUT POWER (dB)
0 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz REFERENCE LEVEL = - 4.2dBm -10 -20
OUTPUT POWER (dB)
-30 -40 -50 -60 -70 -80 -90
-30 -40 -50 -60 -70 -80 -90 -100
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz
REFERENCE LEVEL = - 4.2dBm
-51dBc@ 100kHz
-90.36dBc/Hz
-100 -2kHz -1kHz 1.7518GHz FREQUENCY 1kHz 2kHz
-400kHz
-200kHz
1.7518GHz FREQUENCY
200kHz
400kHz
TPC 2. Phase Noise Plot, Low Noise and Spur Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution
TPC 5. Spurious Plot, Low Noise and Spur Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution
0 -10 -20 -30
OUTPUT POWER (dB)
0 VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz REFERENCE LEVEL = - 4.2dBm -10 -20
OUTPUT POWER (dB)
-30 -40 -50 -60 -70 -80 -90 -100
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 10MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz
REFERENCE LEVEL = - 4.2dBm
-40 -50 -60 -85.86dBc/Hz -70 -80 -90 -100 -2kHz -1kHz 1.7518GHz FREQUENCY 1kHz 2kHz
-72dBc@ 100kHz
-400kHz
-200kHz
1.7518GHz FREQUENCY
200kHz
400kHz
TPC 3. Phase Noise Plot, Lowest Spur Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution REV. B
TPC 6. Spurious Plot, Lowest Spur Mode, 1.7518 GHz RFOUT, 10 MHz PFD Frequency, 200 kHz Channel Step Resolution
-7-
ADF4252
0 -10 -20
OUTPUT POWER (dB)
OUTPUT POWER (dB)
-30 -40 -50 -60 -70 -80 -90 -100
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz
0 REFERENCE LEVEL = - 4.2dBm -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz
REFERENCE LEVEL = - 4.2dBm
-53dBc@ 100kHz
-102dBc/Hz
-2kHz
-1kHz
1.7518GHz FREQUENCY
1kHz
2kHz
-400kHz
-200kHz
1.7518GHz FREQUENCY
200kHz
400kHz
TPC 7. Phase Noise Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution
TPC 10. Spurious Plot, Lowest Noise Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution
0 -10 -20
OUTPUT POWER (dB)
-30 -40 -50 -60 -70 -80 -90 -100
OUTPUT POWER (dB)
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz
0 REFERENCE LEVEL = - 4.2dBm -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz
REFERENCE LEVEL = - 4.2dBm
-63.2dBc@ 100kHz
-93.86dBc/Hz
-2kHz
-1kHz
1.7518GHz FREQUENCY
1kHz
2kHz
-400kHz
-200kHz
1.7518GHz FREQUENCY
200kHz
400kHz
TPC 8. Phase Noise Plot, Low Noise and Spur Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution
TPC 11. Spurious Plot, Low Noise and Spur Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution
0 -10 -20
OUTPUT POWER (dB)
-30 -40 -50 -60 -70 -80 -90
OUTPUT POWER (dB)
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 10Hz
0 REFERENCE LEVEL = - 4.2dBm -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
VDD = 3V, VP = 5V ICP = 1.875mA PFD FREQUENCY = 20MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz FRACTION = 59/100 RBW = 1kHz
REFERENCE LEVEL = - 4.2dBm
-89.52dBc/Hz
-72.33dBc@ 100kHz
-100 -2kHz -1kHz 1.7518GHz FREQUENCY 1kHz 2kHz
-400kHz
-200kHz
1.7518GHz FREQUENCY
200kHz
400kHz
TPC 9. Phase Noise Plot, Lowest Spur Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution
TPC 12. Spurious Plot, Lowest Spur Mode, 1.7518 GHz RFOUT, 20 MHz PFD Frequency, 200 kHz Channel Step Resolution
-8-
REV. B
ADF4252
-70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 1.430 1.435 1.440 1.445 1.450 1.455 1.460 LOWEST NOISE MODE LOW NOISE AND SPUR MODE LOWEST SPUR MODE
-20 -30 -40
SPURIOUS LEVEL (dBc)
PHASE NOISE (dBc/Hz)
-50 -60 -70 -80 -90 -100 -110 LOWEST SPUR MODE -120 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) LOWEST NOISE MODE
1.455
1.460
FREQUENCY (GHz)
TPC 13. In-Band Phase Noise vs. Frequency*
TPC 16. 400 kHz Spur vs. Frequency*
-10 -20 -30
-20 -30 -40
SPURIOUS LEVEL (dBc)
-40 LOWEST NOISE MODE -50 -60 -70 -80 -90 -100 LOWEST SPUR MODE -110 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 1.460
SPURIOUS LEVEL (dBc)
-50 -60 -70 -80 -90 -100 -110 LOWEST SPUR MODE -120 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) LOWEST NOISE MODE
1.455
1.460
TPC 14. 100 kHz Spur vs. Frequency*
TPC 17. 600 kHz Spur vs. Frequency*
-20 -30 -40 SPURIOUS LEVEL (dBc) -50 -60 -70 -80 -90 -100 -110 LOWEST SPUR MODE 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 1.460 LOWEST NOISE MODE
-20 -30 -40
SPURIOUS LEVEL (dBc)
-50 -60 -70 -80 -90 -100 -110 LOWEST SPUR MODE -120 1.430 1.435 1.440 1.445 1.450 FREQUENCY (GHz) 1.455 1.460 LOWEST NOISE MODE
-120 1.430
TPC 15. 200 kHz Spur vs. Frequency*
TPC 18. 3 MHz Spur vs. Frequency*
*Across all fractional channel steps from f = 0/130 to f = 129/130. RFOUT = 1.45 GHz, Int Reg = 55, Ref = 26 MHz, and LBW = 40 kHz. Plots attained using EVAL-ADF4252EB2 evaluation board.
REV. B
-9-
ADF4252
0
-120 VDD = 3V VP = 3V -130
-5
AMPLITUDE (dBm)
-10 PRESCALER = 4/5 -15
PHASE NOISE (dB/Hz)
-140
-150
-20 PRESCALER = 8/9 -25
-160
-30 -35
-170
0
1
2
3 4 FREQUENCY (GHz)
5
6
-180 10k
100k 1M PHASE DETECTOR FREQUENCY (Hz)
10M
TPC 19. RF Input Sensitivity
TPC 22. Phase Noise (Referred to CP Output) vs. PFD Frequency, IF Side
0 5 10
VDD = 3V VP2 = 3V
6
4
IF INPUT POWER (dBm)
2
15
ICP (mA)
VDD = 3V VP1 = 5.5V 0
20 25 30
-2
-4
35 40 -0.4
-6
0.1 0.6 1.1 IF INPUT FREQUENCY (GHz) 1.6
0
0.5
1.0
1.5
2.0
2.5 3.0 VCP (V)
3.5
4.0
4.5
5.0
5.5
TPC 20. IF Input Sensitivity
TPC 23. RF Charge Pump Output Characteristics
-120 VDD = 3V VP = 5V -130
PHASE NOISE (dB/Hz)
6
4
-140
2
-150
ICP (mA)
VDD = 3V VP2 = 3V
0
-160
-2
-170
-4
-180 10k
100k 1M PHASE DETECTOR FREQUENCY (Hz)
-6
10M
0
0.5
1.0
1.5 VCP (V)
2.0
2.5
3.0
TPC 21. Phase Noise (Referred to CP Output) vs. PFD Frequency, RF Side
TPC 24. IF Charge Pump Output Characteristics
-10-
REV. B
ADF4252
CIRCUIT DESCRIPTION Reference Input Section
The reference input stage is shown in Figure 3. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL
REFIN = the reference input frequency, D = RF REFIN doubler bit, R = the preset divide ratio of the binary 4-bit programmable reference counter (1 to 15), INT = the preset divide ratio of the binary 8-bit counter (31 to 255), MOD = the preset modulus ratio of binary 12-bit programmable FRAC counter (2 to 4095), and FRAC = the preset fractional ratio of the binary 12-bit programmable FRAC counter (0 to MOD).
RF N DIVIDER N = INT + FRAC/MOD
NC SW2 REFIN NC SW1 SW3 NO
100k
FROM RF INPUT STAGE
N-COUNTER
TO PFD
BUFFER
TO R COUNTER REFOUT
THIRD ORDER FRACTIONAL INTERPOLATOR
XOEB
INT REG MOD REG FRAC VALUE
NC = NORMALLY CLOSED NO = NORMALLY OPEN
Figure 3. Reference Input Stage
RF and IF Input Stage
The RF input stage is shown in Figure 4. The IF input stage is the same. It is followed by a two-stage limiting amplifier to generate the CML clock levels needed for the N counter.
RF R Counter
BIAS GENERATOR 2k 1.6V VDD1 2k
Figure 5. N Counter
The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the RF PFD. Division ratios from 1 to 15 are allowed.
IF R Counter
RFINA
The 15-bit IF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the IF PFD. Division ratios from 1 to 32767 are allowed.
IF Prescaler (P/P + 1)
RFINB
AGND
Figure 4. RF Input Stage
RF INT Divider
The dual modulus IF prescaler (P/P + 1), along with the IF A and B counters, enables the large division ratio, N, to be realized (N = PB + A). Operating at CML levels, it takes the clock from the IF input stage and divides it down to a manageable frequency for the CMOS IF A and B counters.
IF A and B Counters
The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 255 are allowed.
INT, FRAC, MOD, and R Relationship
The IF A and B CMOS counters combine with the dual modulus IF prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are guaranteed to work when the prescaler output is 150 MHz or less.
Pulse Swallow Function
The INT, FRAC, and MOD values, in conjunction with the RF R counter, make it possible to generate output frequencies that are spaced by fractions of the RF phase frequency detector (PFD). The equation for the RF VCO frequency (RFOUT) is
FRAC RFOUT = FPFD x INT + MOD
(1)
The IF A and B counters, in conjunction with the dual modulus IF prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. See Device Programming after Initial Power-Up section for examples. The equation for the IF VCO (IFOUT) frequency is
where RFOUT is the output frequency of external voltage controlled oscillator (VCO).
FPFD = REFIN
IFOUT = (P x B ) + A x FPFD
[
]
(3)
(1 + D) x
R
(2)
where IFOUT = the output frequency of the external voltage controlled oscillator (VCO), P = the preset modulus of IF dual modulus prescaler, B = the preset divide ratio of the binary 12-bit counter (3 to 4095), and A = the preset divide ratio of the binary 6-bit swallow counter (0 to 63). FPFD is obtained using Equation 2.
REV. B
-11-
ADF4252
Phase Frequency Detector (PFD) and Charge Pump Lock Detect
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 6 is a simplified schematic. The antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs.
U1 HI D1 Q1 +IN CLR1 CHARGE PUMP DELAY ELEMENT CP UP
MUXOUT can be programmed for two types of lock detect: digital and analog. Digital is active high. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. When lock has been detected, this output will be high with narrow low going pulses.
Input Shift Register
Data is clocked in on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the input register to one of seven latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C2, C1, and C0) in the shift register. These are the three LSBs: DB2, DB1, and DB0, as shown in Figure 1. The truth table for these bits is shown in Table I. Table II summarizes how the registers are programmed.
Table I. Control Bit Truth Table
U3
C2
CLR2 D2 DOWN Q2
C1 0 0 1 1 0 0 1
C0 0 1 0 1 0 1 0
Data Latch RF N Divider Reg RF R Divider Reg RF Control Reg Master Reg IF N Divider Reg IF R Divider Reg IF Control Reg
HI -IN
U2
Figure 6. PFD Simplified Schematic
MUXOUT and Lock Detect
0 0 0 0 1 1 1
The output multiplexer on the ADF4252 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M4, M3, M2, and M1 in the master register. Table I shows the full truth table. Figure 7 shows the MUXOUT section in block diagram format.
LOGIC LOW IF ANALOG LOCK DETECT IF R DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT IF/RF ANALOG LOCK DETECT IF DIGITAL LOCK DETECT LOGIC HIGH RF R DIVIDER OUTPUT RF N DIVIDER OUTPUT THREE STATE OUTPUT RF DIGITAL LOCK DETECT RF/IF DIGITAL LOCK DETECT LOGIC HIGH LOGIC LOW DGND MUX CONTROL MUXOUT DVDD
Figure 7. MUXOUT Circuit
-12-
REV. B
ADF4252
Table II. Register Summary
RF N DIVIDER REG
RESERVED
8-BIT RF INTEGER VALUE (INT)
12-BIT RF FRACTIONAL VALUE (FRAC)
CONTROL BITS
DB23
DB22
DB21 N7
DB20
N6
DB19
N5
DB18
N4
DB17
N3
DB16
N2
DB15
N1
DB14
F12
DB13
F11
DB12
F10
DB11
F9
DB10 F8
DB9
F7
DB8
F6
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
C3 (0)
DB1
C2 (0)
DB0
C1 (0)
P1
N8
RF R DIVIDER REG
PRESCALER
RF REFIN DOUBLER
4-BIT RF R COUNTER
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
CONTROL BITS
DB20 P3
DB19 P2
DB18 R4
DB17 R3
DB16 R2
DB15 R1
DB14 M12
DB13 M11
DB12 M10
DB11 M9
DB10 M8
DB9 M7
DB8 M6
DB7 M5
DB6 M4
DB5 M3
DB4 M2
DB3 M1
DB2 C3 (0)
DB1 C2 (0)
DB0 C1 (1)
RF CONTROL REG
NOISE AND SPUR SETTING 3 NOISE AND SPUR SETTING 2 RESERVED NOISE AND SPUR SETTING 1 RF PD POLARITY
RESERVED
RF CP CURRENT SETTING
RF COUNTER RESET
RF POWERDOWN
RF CP THREESTATE
CONTROL BITS
DB15 N3
DB14 T3
DB13 T2
DB12 T1
DB11 N2
DB10 CP2
DB9 CP1
DB8 0
DB7 P8
DB6 N1
DB5 P6
DB4 P5
DB3 P4
DB2 C3 (0)
DB1 C2 (1)
DB0 C1 (0)
MASTER REG
CP THREESTATE COUNTER RESET XO DISABLE POWERDOWN
MUXOUT
CONTROL BITS
DB10 M4
DB9 M3
DB8 M2
DB7 M1
DB6 P12
DB5 P11
DB4 P10
DB3 P9
DB2 C3 (0)
DB1 C2 (1)
DB0 C1 (1)
IF N DIVIDER REG
IF CP GAIN
IF PRESCALER
12-BIT IF B COUNTER
6-BIT IF A COUNTER
CONTROL BITS
DB23 P15
DB22 P14
DB21 P13
DB20 B12
DB19 B11
DB18 B10
DB17 B9
DB16 B8
DB15 B7
DB14 B6
DB13 B5
DB12 B4
DB11 B3
DB10 B2
DB9 B1
DB8 A6
DB7 A5
DB6 A4
DB5 A3
DB4 A2
DB3 A1
DB2 C3 (1)
DB1 C2 (0)
DB0 C1 (0)
IF R DIVIDER REG
IF REFIN DOUBLER
15-BIT IF R COUNTER
CONTROL BITS
DB18 P16
DB17 R15
DB16 R14
DB15 R13
DB14 R12
DB13 R11
DB12 R10
DB11 R9
DB10 R8
DB9 R7
DB8 R6
DB7 R5
DB6 R4
DB5 R3
DB4 R2
DB3 R1
DB2 C3 (1)
DB1 C2 (0)
DB0 C1 (1)
IF CONTROL REG
IF POWERDOWN RF PHASE RESYNC IF PD POLARITY IF COUNTER RESET IF CP THREESTATE
RF PHASE RESYNC
RESERVED
IF CP CURRENT SETTING
IF LDP
CONTROL BITS
DB15 PR3
DB14 PR2
DB13 T8
DB12 T7
DB11 PR1
DB10 CP3
DB9 CP2
DB8 CP1
DB7 P21
DB6 P20
DB5 P19
DB4 P18
DB3 P17
DB2 C3 (1)
DB1 C2 (1)
DB0 C1 (0)
REV. B
-13-
ADF4252
Table III. RF N Divider Register Map
RESERVED
8-BIT RF INTEGER VALUE (INT)
12-BIT RF FRACTIONAL VALUE (FRAC)
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P1 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7
DB8 F6
DB7 F5
DB6 F4
DB5 F3
DB4 F2
DB3 F1
DB2
DB1
DB0
C3 (0) C2 (0) C1 (0)
P1 0
RESERVED RESERVED
F12 0 0 0 0 . . . 1 1 1 1
F11 0 0 0 0 . . . 1 1 1 1
F10 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
F3 0 0 0 0 . . . 1 1 1 1
F2 0 0 1 1 . . . 0 0 1 1
F1 0 1 0 1 . . . 0 1 0 1
FRACTIONAL VALUE (FRAC) 0 1 2 3 . . . 4092 4093 4094 4095
N8 0 0 0 0 . . . 1 1 1
N7 0 0 0 0 . . . 1 1 1
N6 0 1 1 1 . . . 1 1 1
N5 1 0 0 0 . . . 1 1 1
N4 1 0 0 0 . . . 1 1 1
N3 1 0 0 0 . . . 1 1 1
N2 1 0 0 1 . . . 0 1 1
N1 1 0 1 0 . . . 1 0 1
RF INTEGER VALUE (INT)* 31 32 33 34 . . . 253 254 255
*WHEN P = 8/9, NMIN = 91
-14-
REV. B
ADF4252
Table IV. RF R Divider Register Map
RF REFIN DOUBLER PRESCALER
4-BIT RF R COUNTER
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
CONTROL BITS
DB20 P3
DB19 P2
DB18 R4
DB17 R3
DB16 R2
DB15 R1
DB14 M12
DB13 M11
DB12 M10
DB11 M9
DB10 M8
DB9 M7
DB8 M6
DB7 M5
DB6 M4
DB5 M3
DB4 M2
DB3 M1
DB2 C3 (0)
DB1 C2 (0)
DB0 C1 (1)
P2
RF REFIN DOUBLER DISABLED ENABLED
0 1
M12 0 0 0 . . . 1 1 1 1
M11 0 0 0 . . . 1 1 1 1
M10 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
M3 0 0 1 . . . 1 1 1 1
M2 1 1 0 . . . 0 0 1 1
M1 0 1 0 . . . 0 1 0 1
INTERPOLATOR MODULUS VALUE (MOD) DIVIDE RATIO 2 3 4 . . . 4092 4093 4094 4095
P3 0 1
RF PRESCALER 4/5 8/9
R4 0 0 0 . . . 1 1 1
R3 0 0 0 . . . 1 1 1
R2 0 1 1 . . . 0 1 1
R1 1 0 1 . . . 1 0 1
RF R COUNTER DIVIDE RATIO 1 2 3 . . . 13 14 15
REV. B
-15-
ADF4252
Table V. RF Control Register Map
RESERVED RF POWERDOWN NOISE AND SPUR SETTING 3 NOISE AND SPUR SETTING 2 NOISE AND SPUR SETTING 1 RF PD POLARITY RF COUNTER RESET
RESERVED
RF CP CURRENT SETTING
RF CP THREESTATE
CONTROL BITS
DB15 N3
DB14 T3
DB13 T2
DB12 T1
DB11 N2
DB10 CP2
DB9 CP1
DB8 0
DB7 P8
DB6 N1
DB5 P6
DB4 P5
DB3 P4
DB2 C3 (0)
DB1 C2 (1)
DB0 C1 (0)
THESE BITS SHOULD EACH BE SET TO 0 FOR NORMAL OPERATION
P4 0 1 N3 SETTING 0 0 1 N2 0 0 1 N1 0 1 1 NOISE AND SPUR LOWEST SPUR LOW NOISE AND SPUR LOWEST NOISE P5 0 1
RF COUNTER RESET DISABLED ENABLED
RF CP THREE-STATE DISABLED THREE-STATE
ICP (mA) CP2 0 0 1 1 CP1 0 1 0 1 1.5k 1.125 3.375 5.625 7.7875 2.7k 0.625 1.875 3.125 4.375 5.6k 0.301 0.904 1.506 2.109
P6 0 1
RF POWER-DOWN DISABLED ENABLED
P8 0 1
RF PD POLARITY NEGATIVE POSITIVE
-16-
REV. B
ADF4252
Table VI. Master Register Map
CP THREESTATE COUNTER RESET XO DISABLE POWERDOWN
MUXOUT
CONTROL BITS
DB10 M4
DB9 M3
DB8 M2
DB7 M1
DB6 P12
DB5 P11
DB4 P10
DB3 P9
DB2 C3 (0)
DB1 C2 (1)
DB0 C1 (1)
M4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
M3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
M2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
M1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW IF ANALOG LOCK DETECT IF R DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT IF DIGITAL LOCK DETECT LOGIC HIGH RF R DIVIDER OUTPUT RF N DIVIDER OUTPUT THREE-STATE OUTPUT LOGIC LOW RF DIGITAL LOCK DETECT RF/IF DIGITAL LOCK DETECT LOGIC HIGH LOGIC LOW
P9 0 1
COUNTER RESET DISABLED ENABLED
P10 0 1 P11 0 1
CP THREE-STATE DISABLED THREE-STATE
POWER-DOWN DISABLED ENABLED
P12 0 1
XO DISABLE XO ENABLED (REFOUT = REFIN ) XO DISABLED (REFOUT = LOGIC LOW) (REFOUT = LOGIC HIGH WHEN IN POWER-DOWN)
REV. B
-17-
ADF4252
Table VII. IF N Divider Register Map
IF CP GAIN
IF PRESCALER*
12-BIT IF B COUNTER*
6-BIT IF A COUNTER*
CONTROL BITS
DB23 P15
DB22 P14
DB21 P13
DB20 B12
DB19 B11
DB18 B10
DB17 B9
DB16 B8
DB15 B7
DB14 B6
DB13 B5
DB12 B4
DB11 B3
DB10 B2
DB9 B1
DB8 A6
DB7 A5
DB6 A4
DB5 A3
DB4 A2
DB3 A1
DB2 C3 (1)
DB1
DB0
C2 (0) C1 (0)
P14 0 0 1 1
P13 0 1 0 1
PRESCALER VALUE 8/9 16/17 32/33 64/65
P15 0 1
IF CP GAIN DISABLED ENABLED
A6 0 0 0 0 . . . 1 1 1 1
A5 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
A2 0 0 1 1 . . . 0 0 1 1
A1 0 1 0 1 . . . 0 1 0 1
A COUNTER DIVIDE RATIO 0 1 2 3 . . . 60 61 62 63
B12 0 0 . . . 1 1 1 1
B11 0 0 . . . 1 1 1 1
B10 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 1 . . . 1 1 1 1
B2 1 0 . . . 0 0 1 1
B1 1 0 . . . 0 1 0 1
B COUNTER DIVIDE RATIO 3 4 . . . 4092 4093 4094 4095
*N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER THAN OR EQUAL TO A FOR CONTIGUOUS VALUES OF N, NMIN IS (P2 - P) .
-18-
REV. B
ADF4252
Table VIII. IF R Divider Register Map
IF REFIN DOUBLER
15-BIT IF R COUNTER
CONTROL BITS
DB18 P16
DB17 R15
DB16 R14
DB15 R13
DB14 R12
DB13 R11
DB12 R10
DB11 R9
DB10 R8
DB9 R7
DB8 R6
DB7 R5
DB6 R4
DB5 R3
DB4 R2
DB3 R1
DB2 C3 (1)
DB1 C2 (0)
DB0 C1 (1)
R15 0 0 0 0 . . . 32764 32765 32766 32767 P16 0 1 IF REFIN DOUBLER DISABLED ENABLED
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
R12 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383
REV. B
-19-
ADF4252
Table IX. IF Control Register Map
RF PHASE RESYNC IF POWERDOWN IF PD POLARITY IF COUNTER RESET IF CP THREESTATE IF LDP
RF PHASE RESYNC
RESERVED
IF CP CURRENT SETTING
CONTROL BITS
DB15 PR3
DB14 PR2
DB13 T8
DB12 T7
DB11 PR1
DB10 CP3
DB9 CP2
DB8 CP1
DB7 P21
DB6 P20
DB5 P19
DB4 P18
DB3 P17
DB2 C3 (1)
DB1 C2 (1)
DB0 C1 (0)
THESE BITS SHOULD BE SET TO 0 FOR NORMAL OPERATION
P17 0 1
IF COUNTER RESET DISABLED ENABLED
PR3 0 1
PR2 0 1
PR1 0 1
RF PHASE RESYNC DISABLED ENABLED
P18 0 1
IF CP THREE-STATE DISABLED THREE-STATE
ICP (mA) IF CP3 0 0 0 0 1 1 1 1 IF CP2 0 0 1 1 0 0 1 1 IF CP1 0 1 0 1 0 1 0 1 1.5k 1.125 2.25 3.375 4.5 5.625 6.75 7.7875 9 2.7k 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 5.6k 0.301 0.602 0.904 1.205 1.506 1.808 2.109 2.411 P21 0 1
P19 0 1
IF POWER-DOWN DISABLED ENABLED
P20 0 1
IF LDP 3 5
IF PD POLARITY NEGATIVE POSITIVE
-20-
REV. B
ADF4252
RF N DIVIDER REGISTER (Address R0) RF CONTROL REGISTER (Address R2)
With R0[2, 1, 0] set to [0, 0, 0], the on-chip RF N divider register will be programmed. Table III shows the input data format for programming this register.
8-Bit RF INT Value
With R2[2, 1, 0] set to [0, 1, 0], the on-chip RF control register will be programmed. Table V shows the input data format for programming this register. Upon initialization, DB15-DB11 should all be set to 0.
Noise and Spur Setting
These eight bits control what is loaded as the INT value. This is used to determine the overall feedback division factor. It is used in Equation 1.
12-Bit RF FRAC Value
These 12 bits control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is used in Equation 1. The FRAC value must be less than or equal to the value loaded into the MOD register.
RF R DIVIDER REGISTER (Address R1)
With R1[2, 1, 0] set to [0, 0, 1], the on-chip RF R divider register will be programmed. Table IV shows the input data format for programming this register.
RF Prescaler (P/P + 1)
The RF dual-modulus prescaler (P/P +1), along with the INT, FRAC, and MOD counters, determine the overall division ratio from the RFIN to the PFD input. Operating at CML levels, it takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS counters. It is based on a synchronous 4/5 core (see Table IV).
RF REFIN Doubler
Setting this bit to 0 feeds the REFIN signal directly to the 4-bit RF R counter, disabling the doubler. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 4-bit RF R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional-N synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. When the doubler is enabled and lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to REFIN duty cycle in the lowest noise mode and in low noise and spur mode. The phase noise is insensitive to REFIN duty cycle when the doubler is disabled.
4-Bit RF R Counter
The noise and spur setting (R2[15, 11, 06]) is a feature that allows the user to optimize his or her design either for improved spurious performance or for improved phase noise performance. When set to [0, 0, 0], the lowest spurs setting is chosen. Here, dither is enabled. This randomizes the fractional quantization noise so that it looks more like white noise than spurious noise. This means that the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide1, for fastlocking applications. A wide-loop filter does not attenuate the spurs to a level that a narrow-loop2 bandwidth would. When this bit is set to [0, 0, 1], the low noise and spur setting is enabled. Here, dither is disabled. This optimizes the synthesizer to operate with improved noise performance. However, the spurious performance is degraded in this mode compared to lowest spurs setting. To improve noise performance even further, another option is available that reduces the phase noise. This is the lowest noise setting [1, 1, 1]. As well as disabling the dither, it also ensures the charge pump is operating in an optimum region for noise performance. This setting is extremely useful where a narrow-loop filter bandwidth is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The Typical Performance Characteristics (TPCs) give the user an idea of the trade-off in a typical WCDMA setup for the different noise and spur settings.
RF Counter Reset
DB3 is the RF counter reset bit for the ADF4252. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0.
RF Charge Pump Three-State
This bit puts the charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation.
RF Power-Down
The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 15 are allowed.
12-Bit Interpolator Modulus
DB5 on the ADF4252 provides the programmable power-down mode. Setting this bit to a 1 will perform a power-down on both the RF and IF sections. Setting this bit to 0 will return the RF and IF sections to normal operation. While in software power-down, the part will retain all information in its registers. Only when supplies are removed will the register contents be lost. When a power-down is activated, the following events occur: 1. All active RF dc current paths are removed. 2. The RF synthesizer counters are forced to their load state conditions. 3. The RF charge pump is forced into three-state mode. 4. The RF digital lock detect circuitry is reset. 5. The RFIN input is debiased. 6. The input register remains active and capable of loading and latching data.
This programmable register sets the fractional modulus. This is the ratio of the PFD frequency to the channel step resolution on the RF output.
NOTES 1 Wide-loop bandwidth is seen as a loop bandwidth greater than 1/10th of the RFOUT channel step resolution (F RES). 2 Narrow-loop bandwidth is seen as a loop bandwidth less than 1/10th of the RFOUT channel step resolution (F RES).
REV. B
-21-
ADF4252
RF Phase Detector Polarity Lock Detect
DB7 in the ADF4252 sets the RF phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0.
RF Charge Pump Current Setting
DB9 and DB10 set the RF charge pump current setting. This should be set to whatever charge pump current the loop filter has been designed with (see Table V).
RF Test Modes
These bits should be set to 0, 0, 0 for normal operation.
MASTER REGISTER (Address R3)
The digital lock detect output goes high if there are 40 successive PFD cycles with an input error of less than 15 ns. It stays high until a new channel is programmed or until the error at the PFD input exceeds 30 ns for one or more cycles. If the loop bandwidth is narrow compared to the PFD frequency, the error at the PFD inputs may drop below 15 ns for 40 cycles around a cycle slip; thus the digital lock detect may go falsely high for a short period until the error again exceeds 30 ns. In this case the digital lock detect is reliable only as a "loss of lock" indicator.
IF N DIVIDER REGISTER (Address R4)
With R3[2, 1, 0] set to 0, 1, 1, the on-chip master register will be programmed. Table VI shows the input data format for programming the master register.
RF and IF Counter Reset
With R4[2, 1, 0] set to [1, 0, 0], the on-chip IF N divider register will be programmed. Table VII shows the input data format for programming this register.
IF CP Gain
DB3 is the counter reset bit for the ADF4252. When this is 1, both the RF and IF R, INT, and MOD counters are held in reset. For normal operation, this bit should be 0. Upon power-up, the DB3 bit needs to be disabled, the INT counter resumes counting in "close" alignment with the R counter. (The maximum error is one prescaler cycle).
Charge Pump Three-State
When set to 1, this bit changes the IF charge pump current setting to its maximum value. When the bit is set to 0, the charge pump current reverts back to its previous state.
IF Prescaler
This bit puts both the RF and IF charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation.
Power-Down
The dual-modulus prescaler (P/P + 1), along with the IF A and B counters, determine the overall division ratio, N, to be realized (N = PB + A) from the IFIN to the IF PFD input. Operating at CML levels, it takes the clock from the IF input stage and divides it down to a manageable frequency for the CMOS counters. It is based on a synchronous 4/5 core. See Equation 2 and Table VII.
IF B and A Counter
R3[3] on the ADF4252 provides the programmable power-down mode. Setting this bit to a 1 will perform a power-down on both the RF and IF sections. Setting this bit to 0 will return the RF and IF sections to normal operation. While in software powerdown, the part will retain all information in its registers. Only when supplies are removed will the register contents be lost. When a power-down is activated, the following events occur: 1. All active dc current paths are removed. 2. The RF and IF counters are forced to their load state conditions. 3. The RF and IF charge pumps are forced into three-state mode. 4. The digital lock detect circuitry is reset. 5. The RFIN input and IFIN input are debiased. 6. The oscillator input buffer circuitry is disabled. 7. The input register remains active and capable of loading and latching data.
XO Disable
The IF A and B counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency (REFIN) divided by R. The equation for the IFOUT VCO frequency is given in Equation 2.
IF R DIVIDER REGISTER (Address R5)
With R5[2, 1, 0] set to [1, 0, 1], the on-chip IF R divider register will be programmed. Table VIII shows the input data format for programming this register.
IF REFIN Doubler
Setting this bit to 0 feeds the REFIN signal directly to the 15-bit IF R counter. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 15-bit IF R counter.
15-Bit IF R Counter
Setting this bit to 1 disables the REFOUT circuitry. This will be set to 1 when using an external TCXO, VCXO, or other reference sources. This will be set to 0 when using the REFIN and REFOUT pins to form an oscillator circuit.
MUXOUT Control
The 15-bit IF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the IF phase frequency detector (PFD). Division ratios from 1 to 32767 are allowed.
IF CONTROL REGISTER (Address R6)
The on-chip multiplexer is controlled by R3[10-7] on the ADF4252. Table VI shows the truth table. If the user updates the RF control register or the IF control register, the MUXOUT contents will be lost. To retrieve the MUXOUT signal, the user must write to the master register.
With R6[2, 1, 0] set to [1, 1, 0], the on-chip IF control register will be programmed. Table IX shows the input data format for programming this register. Upon initialization, DB15-DB11 should all be set to 0.
-22-
REV. B
ADF4252
IF Counter Reset
DB3 is the IF counter reset bit for the ADF4252. When this is 1, the IF synthesizer counters are held in reset. For normal operation, this bit should be 0.
IF Charge Pump Three-State
This bit puts the IF charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation.
IF Power-Down
delaying the resync activation until the locking transient is close to its final frequency. In the IF R divider register, Bits R5[17-3] are used to set a time interval from when the new channel is programmed to the time the resync is activated. Although the time interval resolution available from the 15-bit IF R register is one REFIN clock cycle, IF R should be programmed to be a value that is an integer multiple of the programmed MOD value to set a time interval that is at least as long as the RF PLL loop's lock time. For example, if REFIN = 26 MHz, MOD = 130 to give 200 kHz output steps (FRES), and the RF loop has a settling time of 150 s, then IF_R should be programmed to 3900, as 26 MHz x 150 s = 3900 Note that if it is required to use the IF synthesizer with phase resync enabled on the RF synth, the IF synth must operate with a PFD frequency of 26 MHz/3900. In an application where the IF synth is not required, the user should ensure that Registers R4 and R6 are not programmed so that the rest of the IF circuitry remains in power-down.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
DB5 on the ADF4252 provides the programmable power-down mode. Setting this bit to a 1 will perform a power-down on the IF section. Setting this bit to 0 will return the section to normal operation. While in software power-down, the part will retain all information in its registers. Only when supplies are removed will the register contents be lost. When a power-down is activated, the following events occur: 1. All active IF dc current paths are removed. 2. The IF synthesizer counters are forced to their load state conditions. 3. The IF charge pump is forced into three-state mode. 4. The IF digital lock detect circuitry is reset. 5. The IFIN input is debiased. 6. The input register remains active and capable of loading and latching data.
IF Phase Detector Polarity
After initially applying power to the supply pins, there are three ways to operate the device.
RF and IF Synthesizers Operational
All registers must be written to when powering up both the RF and IF synthesizer.
RF Synthesizer Operational, IF Power-Down
DB7 in the ADF4252 sets the IF phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0.
IF Charge Pump Current Setting
It is necessary to write only to Registers R3, R2, R1, and R0 when powering up the RF synthesizer only. The IF side will remain in power-down until Registers R6, R5, R4, and R3 are written to.
IF Synthesizer Operational, RF Power-Down
DB8, DB9, and DB10 set the IF charge pump current setting. This should be set to whatever charge pump current the loop filter has been designed with (see Table VII).
IF Test Modes
It is necessary to write to only Registers R6, R5, R4, and R3 when powering up the IF synthesizer only. The RF side will remain in power-down until registers R3, R2, R1, and R0 are written to.
RF Synthesizer: An Example
These bits should be set to [0, 0] for normal operation.
RF Phase Resync
The RF synthesizer should be programmed as follows:
FRAC RFOUT = INT + x FPFD MOD
Setting the phase resync bits [15, 14, 11] to [1, 1, 1] enables the phase resync feature. With a fractional modulus of M, a fractional-N PLL can settle with any one of (2 )/M valid phase offsets with respect to the reference input. This is different to integer-N (where the RF output always settles to the same static phase offset with respect to the input reference, which is zero ideally) but does not matter in most applications where all that is required is consistent frequency lock. For applications where a consistent phase relationship between the output and reference is required (i.e., digital beamforming), the ADF4252 fractional-N synthesizer can be used with the phase resync feature enabled. This ensures that if the user programs the PLL to jump from Frequency (and Phase) A to Frequency (and Phase) B and back again to Frequency A, the PLL will return to the original phase (Phase A). When enabled, it will activate every time the user programs Register R0 or R1 to set a new output frequency. However if a cycle slip occurs in the settling transient after the phase re-resync operation, the phase resync will be lost. This can be avoided by
(4)
where RFOUT = the RF frequency output, INT = the integer division factor, FRAC = the fractionality, and MOD = the modulus.
1 + D FPFD = REFIN x R
where REF IN = the reference frequency input, D = the RF REFIN doubler bit, and R = the RF reference division factor.
(5)
For example, in a GSM 1800 system where 1.8 GHz RF frequency output (RFOUT) is required, a 13 MHz reference frequency input (REF IN) is available and a 200 kHz channel resolution (FRES) is required on the RF output.
MOD = MOD =
REFIN
FRES 13 MHz
200 kHz
= 65
REV. B
-23-
ADF4252
So, from Equation 5:
1+ 0 = 13 MHz 1 FRAC 1.8 GHz = 13 MHz x INT + 65 FPFD = 13 MHz x
For example, in an application that requires 1.75 GHz RF and 200 kHz channel step resolution, the system has a 13 MHz reference signal. One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65. This results in the required 200 kHz resolution. Another possible setup is using the reference doubler to create 26 MHz from the 13 MHz input signal. This 26 MHz is then fed into the PFD. The modulus is now programmed to divide by 130, which also results in 200 kHz resolution. This offers superior phase noise performance over the previous setup. The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM1800 standards, the programmable modulus is a huge benefit. PDC requires 25 kHz channel step resolution, whereas GSM1800 requires 200 kHz channel step resolution. A 13 MHz reference signal could be fed directly to the PFD. The modulus would then be programmed to 520 when in PDC mode (13 MHz /520 = 25 kHz). The modulus would be reprogrammed to 65 for GSM1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remains constant (13 MHz). This allows the user to design one loop filter that can be used in both setups without any stability issues. It is the ratio of the RF frequency to the PFD frequency that affects the loop design. Keeping this relationship constant, and instead changing the modulus factor, results in a stable filter.
Spurious Optimization and Fastlock
where INT = 138 and FRAC = 30.
IF Synthesizer: An Example
The IF synthesizer should be programmed as follows:
IFOUT = (P x B ) + A x FPFD
[
]
(6)
where IFOUT = the output frequency of external voltage controlled oscillator (VCO), P = the IF prescaler, B = the B counter value, and A = the A counter value. Equation 5 applies in this example as well. For example, in a GSM1800 system, where 540 MHz IF frequency output (IFOUT) is required, a 13 MHz reference frequency input (REFIN) is available and a 200 kHz channel resolution (FRES) is required on the IF output. The prescaler is set to 16/17. IF REFIN doubler is disabled. By Equation 5, 200 kHz = 13 MHz x if R = 65. By Equation 6,
540 MHz = 200 kHz x (16 x B ) + A
1+ 0 R
[
]
if B = 168 and A = 12.
Modulus
The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (FRES) required at the RF output. For example, a GSM system with 13 MHz REFIN would set the modulus to 65. This means that the RF output resolution (FRES) is the 200 kHz (13 MHz/65) necessary for GSM.
Reference Doubler and Reference Divider
There is a reference doubler on-chip, which allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency will usually result in an improvement in noise performance of 3 dB. It is important to note that the PFD cannot be operated above 30 MHz due to a limitation in the speed of the - circuit of the N divider.
12-Bit Programmable Modulus
As mentioned in the Noise and Spur Setting section, the part can be optimized for spurious performance. However, in fastlocking applications, the loop bandwidth needs to be wide. Therefore, the filter does not provide much attenuation of the spurious. The programmable charge pump can be used to avoid this issue. The filter is designed for a narrow-loop bandwidth so that steady-state spurious specifications are met. This is designed using the lowest charge pump current setting. To implement fastlock during a frequency jump, the charge pump current is set to the maximum setting for the duration of the jump. This has the effect of widening the loop bandwidth, which improves lock time. When the PLL has locked to the new frequency, the charge pump is again programmed to the lowest charge pump current setting. This will narrow the loop bandwidth to its original cutoff frequency to allow for better attenuation of the spurious than the wide-loop bandwidth.
Spurious Signals--Predicting Where They Will Appear
Unlike most other fractional-N PLLs, the ADF4252 allows the user to program the modulus over a 12-bit range. This means that the user can set up the part in many different configurations for a specific application, when combined with the reference doubler and the 4-bit R counter.
Just as in integer-N PLLs, spurs will appear at PFD frequency offsets on either side of the carrier (and multiples of the PFD frequency). In a fractional-N PLL, spurs will also appear at frequencies equal to the RFOUT channel step resolution (FRES). The ADF4252 uses a high order fractional interpolator engine, which results in spurs also appearing at frequencies equal to half of the channel step resolution. For example, examine the GSM1800 setup with a 26 MHz PFD and 200 kHz resolution. Spurs will appear at 26 MHz from the RF carrier (at an extremely low level due to filtering). Also, there will be spurs at 200 kHz from the RF carrier. Due to the fractional interpolator architecture used in the ADF4252, spurs will also appear at
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REV. B
ADF4252
100 kHz from the RF carrier. Harmonics of all spurs mentioned will also appear. With the lowest spur setting enabled, the spurs will be attenuated into the noise floor.
Prescaler
byte has been written, the LE input should be brought high to complete the transfer. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be 166 kHz.
The prescaler limits the INT value. With P = 4/5, Nmin = 31. With P = 8/9, Nmin = 91. The prescaler can also influence the phase noise performance. If INT < 91, a prescaler of 4/5 should be used. For applications where INT > 91, P = 8/9 should be used for optimum noise performance.
Filter Design--ADIsimPLL
SCLK DT TFS
SCLK SDATA LE CE
A filter design and analysis program is available to help users implement their PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL software. The software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed.
INTERFACING
I/O FLAGS
MUXOUT (LOCK DETECT)
ADSP-21xx
The ADF4252 has a simple SPI compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Control Bit Truth Table. The maximum allowable serial clock rate is 20 MHz, which means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 s. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds.
ADF4252
Figure 9. ADSP-21xx to ADF4252 Interface
ADSP-2181 Interface
SCLOCK MOSI
SCLK SDATA LE
Figure 9 shows the interface between the ADF4252 and the ADSP-21xx digital signal processor. Each latch of the ADF4252 needs (at most) a 24-bit word. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
I/O PORTS
CE MUXOUT (LOCK DETECT)
The leads on the chip scale package (CP-24) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This will ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This will ensure that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz copper to plug the via. The user should connect the printed circuit board to AGND.
ADuC812
ADF4252
Figure 8. ADuC812 to ADF4252 Interface
ADuC812 Interface
Figure 8 shows the interface between the ADF4252 and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The microconverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4252 needs (at most) a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third
REV. B
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ADF4252
VVCO R48 0 VP R44 0 VDD R1 20 VDD' C3 22 F IFOUT J6 C9 22 F C5 22 F R43 0 C7 22 F C11 22 F C29 22 F RFOUT J7 VP VVCO R49 0 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
C4 10pF
C10 10pF
C6 10pF
DVDD VDD1 VDD2 VDD3
C8 10pF
C12 10pF
C30 10pF
C15 100pF R12 18 R13 C16 18 100pF R14 18 R15 51
14 VCC 10 RF OUT VIN 2
R17 13k C20 82pF C19 2.2nF R16 7.5k C18 270pF
VP2 CPIF U1
VP1 CPRF C23 10nF C24 100nF R19 270
14 R20 470 C25 3.3nF VCC 2V IN RFOUT 10
C27 100pF R22 18 C26 R21 100pF 18 R23 18 R24 51 C28 100pF
VCO2 VCO190-540T
ADF4252BCP
CPGND1 IFINA RFINA RFINB
VCO1 VCO190-1730T
C17 100pF
REFIN T13 J5 5V
C13 1nF R11 51
C14 1nF
C43 100pF R27 2.7k LE MUXOUT AGND1 DGND AGND2 CPGND2 T14
C44 100pF
R27 10k
T16
R28 10k VDD R29 10k D4
R45 0 3V R46 0
R47 0 3 O/P 4 B+
GND Y3 C32 33pF
2
DATA CLK
C46 22 F
C45 10pF
Y2 10MHz C31 33pF
R4 1M
R26 1k
R39 0
REFOUT J8
4 R38 0
1 U6 2
VCC 3V R34 0 5V R35 0
Figure 10. Typical PLL Circuit Schematic
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REV. B
ADF4252
OUTLINE DIMENSIONS 24-Lead Lead Frame Chip Scale Package [LFCSP] (CP-24)
Dimensions shown in millimeters
4.0 BSC SQ 0.60 MAX 0.60 MAX
19 18 24 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95
7 6
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
BOTTOM VIEW
13 12
0.25 MIN 2.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
REV. B
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ADF4252 Revision History
Location 10/03--Data Sheet changed from REV. A to REV. B. Page
Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Change to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Inserted Lock Detect section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
C02946-0-10/03(B)
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REV. B

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