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LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
DESCRIPTION
The LF48410 is capable of generating histograms and Cumulative Distribution Functions of video images. It may also be used as a look up table, a bin accumulator, a delay memory (delay and subtract also possible), or a single port RAM. The on-chip 1024 x 24-bit memory array facilitates histograms of images up to 4K x 4K pixels with a 10-bit pixel resolution. Once the histogram of a video image is stored in the memory array, the Cumulative Distribution Function can be calculated by putting the device in Histogram Accumulate Mode. Transformation functions can be performed on pixel values when the device is in Look Up Table Mode. If the Cumulative Distribution Function is the desired transformation function, the LF48410 can calculate it and have it available for Look Up Table Mode. When the device is in Delay Memory Mode, it functions as a video row buffer. In this mode, the LF48410 can buffer video lines as long as 1029 pixels. The device can also function as an asynchronous single port RAM. During asynchronous modes, the device can be configured as a 1024 x 24, 1024 x 16, or 1024 x 8-bit RAM. A Flash Clear function is provided which sets all memory array locations and data path registers to "0".
FEATURES
u 40 MHz Data Input and Computation Rate u 1024 x 24-bit Memory Array u Histograms of Images up to 4K x 4K with 10-bit Pixel Resolution u Memory Array Flash Clear u User-Programmable Modes: Histogram, Histogram Accumulate, Look Up Table, Bin Accumulate, Delay Memory, Delay and Subtract, Single Port RAM u Replaces Harris HSP48410 u 84-pin PLCC, J-Lead
LF48410 BLOCK DIAGRAM
RAM ARRAY DATA IN 24 DIN23-0
3
DATA OUT ADDRESS WR ADDER INPUT CONTROL DIO I/F 24 DIO23-0
10 IOA9-0 10 PIN9-0 ADDRESS GENERATOR
CLK (TO ALL REGISTERS) WR RD UWS START FC
COUNTER
CONTROL
3 FCT2-0 LD FUNCTION DECODE MUX CONTROL SIGNALS
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LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
rising edge of LD. To ensure proper operation of the device, START must be HIGH while changing modes, and there must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. Inputs/Outputs DIO23-0 -- Data Input/Output In all synchronous modes, DIO23-0 is the 24-bit registered data output port. In all asynchronous modes, DIO23-0 is both the data input and data output port for the memory array. Controls START -- Device Enable START is used to enable and disable the synchronous modes of operation (except for the Delay Memory and Delay and Subtract Modes). The synchronous mode sections explain how START functions in each mode. START has no effect in asynchronous modes. Data is latched on the rising edge of CLK. START must be held HIGH when changing from one mode to another. To ensure proper operation of the device, there must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. RD -- Read/Output Enable In all synchronous modes, RD is used as an output enable for DIO23-0. When RD is LOW, DIO23-0 is enabled for output. When RD is HIGH, DIO23-0 is placed in a high-impedance state. In all asynchronous modes, RD is used as a read enable for the memory array (see asynchronous mode sections for details). WR -- Write Enable In all asynchronous modes, WR is used as a write enable for the memory array (see asynchronous mode sections for details). WR has no effect in the synchronous modes. UWS -- Upper Word Select UWS is only used in Asynchronous 16 Mode. If UWS is LOW and a memory write is performed, data on DIO15-0 is written to the lower 16 bits of the addressed 24-bit word. If UWS is LOW and a memory read is performed, the lower 16 bits of the addressed 24-bit word will be output on DIO15-0. If UWS is HIGH and a memory write is performed, data on DIO7-0 is written to the upper 8 bits of the addressed 24-bit word. If UWS is HIGH and a memory read is performed, the upper 8 bits of the addressed 24-bit word will be output on DIO7-0. FC -- Flash Clear When FC is LOW, all memory array locations and data path registers are set to "0". To ensure that Flash Clear functions properly, FC should not be set LOW until START is HIGH (synchronous modes) or WR is HIGH (asynchronous modes). LD -- Function Load Strobe Data present on FCT2-0 is latched into the LF48410 on the rising edge of LD. To ensure proper operation of the device, there must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.
SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK -- Master Clock When operating in a synchronous mode, the rising edge of CLK strobes all enabled registers. CLK has no effect when operating in an asynchronous mode. Inputs PIN9-0 -- Pixel Data Input PIN9-0 provides address information to the memory array in Histogram, Bin Accumulate, and Look Up Table Modes. Data is latched on the rising edge of CLK. DIN23-0 -- Data Input In Bin Accumulate Mode, DIN23-0 provides data to the internal summer to be added to data already in the memory array. In Look Up Table Mode, DIN23-0 is used to load the memory array with the desired values. In Delay Memory Mode, the data to be delayed is input to the memory array using DIN23-0, and in Delay and Subtract Mode it also provides data to be subtracted from the delayed data. In all four modes, DIN23-0 is latched on the rising edge of CLK. IOA9-0 -- Asynchronous Address Input IOA9-0 provides address information to the memory array in Asynchronous 16 and 24 Modes. FCT2-0 -- Function Input FCT2-0 is used to put the LF48410 into one of its eight modes of operation (Table 1). Data is latched on the
TABLE 1.
FCT2-0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
LF48410 MODES
MODE Histogram Histogram Accumulate Delay and Subtract Look Up Table Bin Accumulate Delay Memory Asynchronous 24 Asynchronous 16
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LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
FIGURE 1. HISTOGRAM MODE
HISTOGRAM MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 1. The memory array keeps track of how many times a particular pixel value is used in a video image. The pixel value is input on PIN9-0 and is latched on the rising edge of CLK. Data at the address defined by PIN9-0 is read out of the memory array and incremented by one. The data is then written back to the memory array, in the same location it was read from, and is also output on DIO23-0 (if RD is LOW). As long as START is LOW, the device will be enabled for Histogram Mode. When START is HIGH, the device will still read pixel values, but the addres-sed data will not be incremented. The unchanged data is output on DIO23-0 and is not written back to the memory array (writing is disabled). START is delayed internally three clock cycles to match the latency of the address generator. HISTOGRAM ACCUMULATE MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 2. This mode is used to calculate the Cumulative Distribution Function of a video image. Before this can be done, the histogram of the image must already be in the memory array. The internal counter is used to generate address data for the memory array. Data at the address defined by the counter is read out of the memory array and added to the sum of the data from all previous address locations. This new value is written back to the memory array, in the same location where the last read occurred, and is also output on DIO23-0 (if RD is LOW). After all memory locations with histogram data are accumulated, the memory array will contain the Cumulative Distribution Function. After this mode is selected, the internal counter and all data path registers are reset to zero when
RAM ARRAY DATA IN DATA OUT ADDRESS WR DIO I/F 10 PIN9-0 ADDRESS GENERATOR "0" "1" RD 24 DIO23-0
START
CONTROL
CLK
TO ALL REGISTERS
FIGURE 2.
HISTOGRAM ACCUMULATE MODE
RAM ARRAY DATA IN DATA OUT ADDRESS WR DIO I/F ADDRESS GENERATOR "0" RD CLK (TO ALL REGISTERS) COUNTER 24 DIO23-0
START
CONTROL
START is set LOW. Every rising edge of CLK causes the counter to increment its output by one until the counter reaches a value of 1023. At this point, the counter will hold the value of 1023 and writing to the memory array will be disabled. As long as START is LOW, the device will be enabled for Histogram Accumulate Mode. When START is HIGH, the counter will still increment its address values, but the addressed data will not be added to anything. The unchanged data is output on DIO23-0 and is not written back to the memory array (writing is disabled). START is delayed internally three clock cycles to match the latency of the address generator.
LOOK UP TABLE MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 3. This mode is used to perform fixed transformation functions on pixel values. The transformation function can be loaded into the memory array in Look Up Table Write Mode, Asynchronous 16/24 Mode, or Histogram Accumulate Mode. In Look Up Table Write Mode, data is loaded into the memory array using DIN23-0, CLK, and START. The internal counter is used to generate address data for the memory array. When START goes LOW, the counter is reset to zero. As long as START is LOW, data on DIN23-0 is latched on the rising edge of CLK and loaded
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LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
DIO23-0 (if RD is LOW). If Look Up Table Write Mode was used to load the memory array, it is important to wait until the third clock cycle after START goes HIGH to input data on PIN9-0 to insure that all data is written into the memory array before any reading is done. BIN ACCUMULATE MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 4. PIN9-0 provides address data for the memory array and is latched on the rising edge of CLK. Data at the address defined by PIN9-0 is read out of the memory array and added to the data on DIN23-0. This new value is written back to the memory array, in the same location where the last read occured, and is also output on DIO23-0 (if RD is LOW). As long as START is LOW, the device will be enabled for Bin Accumulate Mode. When START is HIGH, the device will still read address values on PIN9-0, but the addressed data will not be added to anything. The unchanged data will be output on DIO23-0 and is not written back to the memory array (writing is disabled). START and DIN23-0 are delayed internally three clock cycles to match the latency of the address generator. DELAY MEMORY MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 5. This mode allows the device to function as a row buffer. The internal counter is used to generate address data for the memory array. When START goes LOW, the counter is reset to zero. Delay length (row length) is determined by reseting the counter every N-4 clock cycles, where N is the number of delays. For
FIGURE 3.
LOOK UP TABLE MODE
RAM ARRAY
24 DIN23-0 DATA IN DATA OUT ADDRESS WR DIO I/F 10 PIN9-0 ADDRESS GENERATOR "0" RD CLK (TO ALL REGISTERS) COUNTER 24 DIO23-0
3
START
CONTROL
NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS.
FIGURE 4.
BIN ACCUMULATE MODE
RAM ARRAY DATA IN DATA OUT ADDRESS 24 DIN23-0
3
WR DIO I/F 24 DIO23-0
10 PIN9-0
ADDRESS GENERATOR
"0"
RD
START
CONTROL
CLK
TO ALL REGISTERS
NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS.
into the memory array at the address defined by the counter. The value already in the memory array at that address is output on DIO23-0 (if RD is LOW). Every rising edge of CLK causes the counter to increment its output by one until the counter reaches a value of 1023. At this point, the counter will hold the value of 1023 and writing to the memory array will be disabled. DIN23-0 is delayed internally three clock cycles to match the latency of the address generator. In Asynchronous 16/24 Mode, data is loaded into the memory array as detailed in the asynchronous mode
sections. If the Cumulative Distribution Function is the desired transformation function, the memory array will contain this data as soon as the Histogram Accumulate function has been completed. Once the memory array contains the desired data, the device needs to be put in Look Up Table Read Mode by setting START HIGH. In Look Up Table Read Mode, pixel values are input on PIN9-0 and are latched on the rising edge of CLK. Data at the address defined by PIN9-0 is read out of the memory array and output on
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LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
FIGURE 5. DELAY MEMORY MODE
example, to set the number of delays to 10, START would have to be set LOW every 6 cycles. The maximum delay length is 1029 and the minimum delay length is 6. Data on DIN23-0 is latched on the rising edge of CLK and loaded into the memory array at the address defined by the counter. Data is output on DIO23-0 (if RD is LOW). If the counter reaches the value of 1023, the counter will hold this value and writing to the memory array will be disabled. DELAY AND SUBTRACT MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 6. The internal counter is used to generate address data for the memory array. When START goes LOW, the counter is reset to zero. Delay length (row length) is determined by reseting the counter every N-4 clock cycles, where N is the number of delays. The maximum delay length is 1029 and the minimum delay length is 6. Data on DIN23-0 is latched on the rising edge of CLK and loaded into the memory array at the address defined by the counter. Data is output on DIO23-0 (if RD is LOW). Before data read from the memory array is output to DIO23-0, input data is subtracted from it according to the following formula: OUTC = D(C-N+1) - D(C-3). OUTC is the data sent to the output port (DIO23-0) on clock cycle C. D(C-N+1) is the data latched into the device on clock cycle C-N+1, and D(C3) is the data latched into the device on clock cycle C-3. N is the number of delays. For example, to determine what will be output on DIO23-0 on clock cycle 12 when the device is set for 10 delays, set C=12 and N=10 to obtain: OUT12 = D3 - D9. If the counter reaches the value of 1023, the counter will hold this value and writing to the memory array will be disabled.
RAM ARRAY 24 DIN23-0 DATA IN DATA OUT ADDRESS WR DIO I/F CLK (TO ALL REGISTERS) COUNTER "0" RD 24 DIO23-0
3
START
CONTROL
NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS.
FIGURE 6.
DELAY AND SUBTRACT MODE
RAM ARRAY 24 DIN23-0 DATA IN DATA OUT ADDRESS WR DIO I/F CLK (TO ALL REGISTERS) COUNTER -DIN23-0 RD 24 DIO23-0 3
START
CONTROL
NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS.
ASYNCHRONOUS 16 MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 7. This mode allows the device to function as an asynchronous single port RAM. Each 24-bit memory location is split into two parts, the lower 16 bits and the upper 8 bits. IOA9-0 addresses the 24-bit memory locations, and UWS addresses the lower 16 or upper 8 bits of those locations. If UWS is LOW, the lower 16 bits of the 24-bit memory location are addressed. If UWS is HIGH, the upper 8 bits are addressed. Address
data on IOA9-0 and UWS is latched into the device on the falling edge of RD or WR. If RD latches the address data, a memory read is performed. Data at the specified address is output on DIO15-0 (if UWS was latched LOW) or DIO7-0 (if UWS was latched HIGH). If UWS was latched LOW/HIGH, DIO16-23/DIO8-23 will output zeros during a memory read. If WR latches the address data, a memory write is performed. After the falling edge of WR latches the address, data on DIO15-0 (if UWS was latched LOW) or DIO7-0 (if UWS was latched HIGH) is written to the RAM on the rising edge of WR.
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LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
FIGURE 7. ASYNCHRONOUS 16/24 MODE
ASYNCHRONOUS 24 MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 7. In this mode, the device functions the same as when in Asynchronous 16 Mode except that the 24-bit memory locations are not split into two parts. All 24 bits are used during a read or write operation. When reading, data is output on DIO23-0. When writing, data is input on DIO23-0. UWS is not used in this mode.
RAM ARRAY DATA IN DATA OUT ADDRESS WR DIO I/F 24 DIO23-0
10 IOA9-0
ADDRESS GENERATOR
WR RD UWS
CONTROL
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LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V Input signal with respect to ground ............................................................................... -0.5 V to VCC + 0.5 V Signal applied to high impedance output ...................................................................... -0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0C to +70C -55C to +125C Supply Voltage 4.75 V VCC 5.25 V 4.50 V VCC 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance
(Note 3)
Test Condition VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 4.0 mA
Min 2.6
Typ
Max
Unit V
0.4 2.2 0.0 VCC 0.8 10 10 310 500 12 12
V V V A A mA A pF pF
Ground VIN VCC (Note 12) Ground VOUT VCC (Note 12)
(Notes 5, 6) (Note 7)
TA = 25C, f = 1 MHz TA = 25C, f = 1 MHz
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432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE
Symbol
DEVICES INCORPORATED
COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
1024 x 24-bit Video Histogrammer
LF48410- 25
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Min
tDIS
tENA
tD
tFL
tFH
tFS
tLS
tLL
tOH
tRD
tRH
tRL
tWDH
tWDS
tWH
tWL
tAH
tAS
tCY
tSH
tSS
tDH
tDS
tPH
tPS
tPWH
tPWL
tCYC
Parameter
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
Output Delay
FC Pulse Width
FCT2-0 Hold Time
FCT2-0 Setup Time
LD Setup to START
LD Pulse Width
RD High to DIO23-0 Valid
RD Low to DIO23-0 Valid
RD Pulse Width High
RD Pulse Width Low
DIO23-0 Hold Time
DIO23-0 Setup Time
WR Pulse Width High
WR Pulse Width Low
Address Hold Time
Address Setup Time
Read/Write Cycle Time
START Hold Time
START Setup Time
DIN23-0 Hold Time
DIN23-0 Setup Time
PIN9-0 Hold Time
PIN9-0 Setup Time
Clock Pulse Width High
Clock Pulse Width Low
Cycle Time
8
Min
15
12
15
12
15
13
30
17
43
15
30
10
35
13
12
13
65
2
2
2
2
2
2
30
Max
43
19
19
19
0
Video Imaging Products
Min
12
10
12
10
12
12
25
15
35
13
25
10
35
12
10
12
55
2
2
2
2
2
2
Max
35
18
18
15
0
08/08/2000-LDS.48410-L
10
10
15
25
15
15
35
5
7
2
2
5
5
8
5
2
2
2
5
5
7
2
5
LF48410
15*
Max
25
11
15 15
0
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE
Symbol
4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4
Min
DEVICES INCORPORATED
MILITARY OPERATING RANGE (-55C to +125C) Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
tDIS
tENA
tD
tFL
tFH
tFS
tLS
tLL
tOH
tRD
tRH
tRL
tWDH
tWDS
tWH
tWL
tAH
tAS
tCY
tSH
tSS
tDH
tDS
tPH
tPS
tPWH
tPWL
tCYC
Parameter
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
Output Delay
FC Pulse Width
FCT2-0 Hold Time
FCT2-0 Setup Time
LD Setup to START
LD Pulse Width
RD High to DIO23-0 High Z
RD Low to DIO23-0 Valid
RD Pulse Width High
RD Pulse Width Low
DIO23-0 Hold Time
DIO23-0 Setup Time
WR Pulse Width High
WR Pulse Width Low
Address Hold Time
Address Setup Time
Read/Write Cycle Time
START Hold Time
START Setup Time
DIN23-0 Hold Time
DIN23-0 Setup Time
PIN9-0 Hold Time
PIN9-0 Setup Time
Clock Pulse Width High
Clock Pulse Width Low
Cycle Time
9
20
15
20
15
20
16
39
20
55
20
39
15
35
15
16
16
80
1024 x 24-bit Video Histogrammer
2
2
2
2
2
0
2
39*
Max
55
27
24
24
Video Imaging Products
Min
15
12
15
12
16
15
30
17
43
16
30
12
35
12
15
15
65
LF48410- 30*
2
2
2
2
2
0
2
Max
43
27
19
19
08/08/2000-LDS.48410-L
Min
10
12
12
12
12
12
25
15
35
13
25
10
35
10
12
12
55
2
2
2
2
2
0
2
LF48410
25*
Max
35
18 18 15
LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
HISTOGRAM MODE
1 2 tSS 3 4 5 tPWH tPWL tCYC tSH
2 3 4 5 6 7
SWITCHING WAVEFORMS:
CLK tSS START tPS PIN9-0
1
6
7
tSH tPH
RD tDIS DIO23-0 tENA
HIGH IMPEDANCE 1 2 3*
tD
*RAM contents not changed.
SWITCHING WAVEFORMS:
HISTOGRAM ACCUMULATE MODE
1 CLK tSS START
2 tSS
3
4
5 tPWH tPWL tCYC
6
7
tSH
tSH RD tDIS DIO23-0 tENA
HIGH IMPEDANCE 1 2 3*
tD
*RAM contents not changed.
SWITCHING WAVEFORMS:
CLK tSS START tPS PIN9-0
1
BIN ACCUMULATE MODE
1 2 tSS 3 4 5 tPWH tPWL tCYC tSH
2 3 4 5 6 7
6
7
tSH tPH
tDS DIN23-0
1
tDH
2 3 4 5 6 7
RD tDIS DIO23-0 tENA
HIGH IMPEDANCE 1 2 3*
tD
*RAM contents not changed.
Video Imaging Products
10
08/08/2000-LDS.48410-L
LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
LOOK UP TABLE WRITE MODE
1 2 3 4 5 tPWH tPWL tCYC tDH
1 2 3 4 5 6 7
SWITCHING WAVEFORMS:
CLK tSS START* tDS DIN23-0
6
7
tD RD tDIS DIO23-0 tENA
HIGH IMPEDANCE 1 2 3 4
*START must be held LOW a minimum of tSH after the rising edge of CLK that loads the last value of DIN23-0.
SWITCHING WAVEFORMS: LOOK UP TABLE READ MODE
1 CLK tSS START* tDS PIN9-0
1
2
3
4 tPWH
5
6
7
tPWL tDH
2
tCYC
3
4
5
tD RD tDIS DIO23-0 tENA
HIGH IMPEDANCE 1
*START must be held HIGH a minimum of tSH after the rising edge of CLK that loads the last value of PIN9-0.
SWITCHING WAVEFORMS:
1 CLK tSS START tDS DIN23-0 1 tDH 2 tSH 2
DELAY MEMORY/DELAY AND SUBTRACT MODE
3 4 5 tPWH 6 7 tSH 8 9 tCYC tSH tSS 12 10 11 12 13 tSH 14
tPWL
tSS tSH 6 7
tSS
tSS 3 4 5
8
9
10
11
13
14
RD tDIS DIO23-0 tENA
HIGH IMPEDANCE
tD 1 2 3 4
Shown are the waveforms for a delay length of 10.
Video Imaging Products
11
08/08/2000-LDS.48410-L
LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
SWITCHING WAVEFORMS: ASYNCHRONOUS WRITE 16/24 MODE
tCY tWL WR tWH
RD tAS IOA9-0 UWS* tWDS DIO23-0 *applies only to 16-bit Asynchronous Mode. tWDH tAH
SWITCHING WAVEFORMS: ASYNCHRONOUS READ 16/24 MODE
WR tRL RD tAS IOA9-0 UWS* tRD DIO23-0
HIGH IMPEDANCE
tCY tRH
tAH
tDIS
HIGH IMPEDANCE
*applies only to 16-bit Asynchronous Mode.
SWITCHING WAVEFORMS: FUCNTION LOAD
tLL LD tFS FCT2-0 tLS START* *there must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. tFH
SWITCHING WAVEFORMS:
FLASH CLEAR
tFL FC
Video Imaging Products
12
08/08/2000-LDS.48410-L
LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
NOTES
9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and IOL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at -0.6 V and a. A 0.1 F ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of -0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 20 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the 200mV level from the measured steady-state output voltage with 10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
DUT
S1 IOL CL IOH VTH
FIGURE B. THRESHOLD LEVELS
tENA OE
Z 0
1.5 V 1.5 V 1.5 V
tDIS
3.5V Vth VOL*
0.2 V
0 1
Z Z
1.5 V
VOH*
0.2 V
Z
1
0V Vth VOL* Measured VOL with IOH = -10mA and IOL = 10mA VOH* Measured VOH with IOH = -10mA and IOL = 10mA
Video Imaging Products
13
08/08/2000-LDS.48410-L
LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
ORDERING INFORMATION
84-pin
PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 VCC CLK GND PIN9 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 FC RD START LD FCT2 FCT1 FCT0 WR GND UWS IOA9 IOA8 IOA7 IOA6 IOA5 IOA4 IOA3 IOA2 IOA1 IOA0 VCC
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 72 71 70 69 68 67 66
Top View
65 64 63 62 61 60 59 58 57 56
55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 DIN16 DIN17 GND DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIO23 DIO22 DIO21 DIO20
Speed
0C to +70C -- COMMERCIAL SCREENING
30 ns 25 ns LF48410JC30 LF48410JC25
-40C to +85C -- COMMERCIAL SCREENING
DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 GND DIO8 DIO9 DIO10 DIO11 DIO12 DIO13 DIO14 DIO15 DIO16 DIO17 DIO18 DIO19
Plastic J-Lead Chip Carrier (J3)
Video Imaging Products
14
08/08/2000-LDS.48410-L
121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
DEVICES INCORPORATED
Speed
-55C to +125C -- MIL-STD-883 COMPLIANT
-55C to +125C -- COMMERCIAL SCREENING
0C to +70C -- COMMERCIAL SCREENING
ORDERING INFORMATION
84-pin
G
H
D
C
K
E
B
A
F
L
J
START FC
FCT1 FCT2
GND WR FCT0
IOA5 UWS IOA9
IOA1 DIO0 DIO1 DIO4 DIO7 DIO8 DIO12 DIO15 DIO18 DIO20 DIO22
IOA2 IOA0
IOA4 IOA3
IOA7 IOA6 IOA8
PIN0 PIN2 PIN3 PIN5 PIN8 VCC PIN9 DIN2 DIN4 DIN5 DIN8
VCC DIO2 DIO3 DIO5 GND DIO13 DIO11 DIO14 DIO16 DIO17 DIO19
LD
1
RD
2
PIN1 PIN4 PIN7 DIN1 DIN0 DIN3 DIN6 DIN7 DIN10
3
Ceramic Pin Grid Array (G6)
Discontinued Package
4
(i.e., Component Side Pinout)
DIO6 DIO9 DIO10
PIN6 CLK GND
15
5
Through Package
Top View
6
1024 x 24-bit Video Histogrammer
7
8
DIN18 DIN20 DIN19
DIN14 DIN15 DIN16
GND DIN21 DIN17
9
DIO21 DIO23
DIN23 DIN22
DIN12 DIN13
DIN9 DIN11
10
Video Imaging Products
11
08/08/2000-LDS.48410-L
LF48410

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