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LM98714 - Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output
October 2006
LM98714 Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output
General Description
The LM98714 is a fully integrated, high performance 16-Bit, 45 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. Highspeed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for Contact Image Sensors and CMOS image sensors). The signal paths utilize 8 bit Programmable Gain Amplifiers (PGA), a +/-9-Bit offset correction DAC and independently controlled Digital Black Level correction loops for each input. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each of the three inputs. The signals are then routed to a 45MHz high performance analog-to-digital converter (ADC). The fully differential processing channel shows exceptional noise immunity, having a very low noise floor of -74dB. The 16-bit ADC has excellent dynamic performance making the LM98714 transparent in the image reproduction chain. n n n n Independent Gain/Offset Correction for Each Channel Digital Black Level Correction Loop for Each Channel Programmable Input Clamp Voltage Flexible CCD/CIS Sensor Timing Generator
Key Specifications
n n n n n n n n n n n n n n n n 1.2 or 2.4 Volt Modes (both with + or - polarity option) ADC Resolution 16-Bit ADC Sampling Rate 45 MSPS INL +/- 23 LSB (typ) Channel Sampling Rate 15/22.5/30 MSPS PGA Gain Steps 256 Steps PGA Gain Range 0.7 to 7.84x Analog DAC Resolution +/-9 Bits Analog DAC Range +/-300mV or +/-600mV Digital DAC Resolution +/-6 Bits Digital DAC Range -1024 LSB to + 1008 LSB SNR -74dB (@0dB PGA Gain) Power Dissipation 505mW (LVDS) 610mW (CMOS) Operating Temp 0 to 70C Supply Voltage 3.3V Nominal (3.0V to 3.6V range) Maximum Input Level
Applications
n n n n Multi-Function Peripherals Facsimile Equipment Flatbed or Handheld Color Scanners High-speed Document Scanner
Features
n LVDS/CMOS Outputs n LVDS/CMOS Pixel Rate Input Clock or ADC Input Clock n CDS or S/H Processing for CCD or CIS sensors
System Block Diagram
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(c) 2006 National Semiconductor Corporation
DS201053
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LM98714 Overall Chip Block Diagram
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FIGURE 1. Chip Block Diagram
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LM98714 Pin Out Diagram
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FIGURE 2. LM98714 Pin Out Diagram
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Typical Application Diagram
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FIGURE 3. Typical Application Diagram
LM98714
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name CLK3 CLK2 CLK1 SH RESET SH_R SDIO SCLK SEN AGND VA VREFB VREFT VA AGND VCLP VA AGND OSR AGND OSG AGND OSB AGND DGND VR DVB INCLK+ O I I I I IO O O I/O O O O O I I I/O I I Typ D D D D D D D D D P P A A P P A P P A P A P A P P P P D PD PU Res PU PD PU PD PU PD Description Configurable sensor control output. Configurable sensor control output. Configurable sensor control output. Sensor - Shift or transfer control signal for CCD and CIS sensors. Active-low master reset. NC when function not being used. External request for an SH pulse. Serial Interface Data Input Serial Interface shift register clock. Active-low chip enable for the Serial Interface. Analog ground return. Analog power supply. Bypass voltage source with 4.7F and pin with 0.1F to AGND. Bottom of ADC reference. Bypass with a 0.1F capacitor to ground. Top of ADC reference. Bypass with a 0.1F capacitor to ground. Analog power supply. Bypass voltage source with 4.7F and pin with 0.1F to AGND. Analog ground return. Input Clamp Voltage. Normally bypassed with a 0.1F, and a 4.7F capacitor to AGND. An external reference voltage may be applied to this pin. Analog power supply. Bypass voltage source with 4.7F and pin with 0.1F to AGND. Analog ground return. Analog input signal. Typically sensor Red output AC-coupled thru a capacitor. Analog ground return. Analog input signal. Typically sensor Green output AC-coupled thru a capacitor. Analog ground return. Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor. Analog ground return. Digital ground return. Power supply input for internal voltage reference generator. Bypass this supply pin with a 0.1F capacitor. Digital Core Voltage bypass. Not an input. Bypass with 0.1F capacitor to DGND. Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation. Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock. Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode. Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode. Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode. Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode. Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode. Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.
29 30 31 32 33 34 35
INCLKDOUT7/ TXCLK+ DOUT6/ TXCLKDOUT5/ TXOUT2+ DOUT4/ TXOUT2DOUT3/ TXOUT1+ DOUT2/ TXOUT1-
I O O O O O O
D D D D D D D
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LM98714
Pin Descriptions
Pin 36 37 38 39 Name DOUT1/ TXOUT0+ DOUT0/ TXOUT0DGND VD O I/O O
(Continued) Typ D D P P Res Description Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode. Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode. Digital ground return. Power supply for the digital circuits. Bypass this supply pin with 0.1F capacitor. A single 4.7F capacitor should be used between the supply and the VD, VR and VC pins. PD PD PD PD PU PD Output clock for registering output data when using CMOS outputs, or configurable sensor control output. Configurable sensor control output. Configurable sensor control output. Configurable sensor control output. Configurable sensor control output. Configurable sensor control output. Digital ground return. Power supply for the sensor control outputs. Bypass this supply pin with 0.1F capacitor. PD Configurable sensor control output.
40 41 42 43 44 45 46 47 48
CLKOUT/ CLK10 CLK9 CLK8 CLK7 CLK6 CLK5 DGND VC CLK4
O O O O O O
D D D D D D P P
O
D
(I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor.).
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Absolute Maximum Ratings
1)
(Notes 2,
Thermal Resistance (JA) Package Dissipation at TA = 25C (Note 4) ESD Rating (Note 5) Human Body Model Machine Model Storage Temperature
66C/W 1.89W
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA,VR,VD,VC) Voltage on Any Input Pin (Not to exceed 4.2V) Voltage on Any Output Pin (execpt DVB and not to exceed 4.2V) DVB Output Pin Voltage Input Current at any pin other than Supply Pins (Note 3) Package Input Current (except Supply Pins) (Note 3) Maximum Junction Temperature (TA) 4.2V -0.3V to (VA + 0.3V) -0.3V to (VA + 0.3V) 2.0V
2500V 250V -65C to +150C
Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6)
25 mA 50 mA
150C
Operating Ratings (Notes 1, 2)
Operating Temperature Range All Supply Voltage 0C TA +70C +3.0V to +3.6V
Electrical Characteristics
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25C. Symbol VIH VIL IIH Parameter Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current VIH = VD RESET SH_R, SCLK SEN IIL Logical "0" Input Current VIL = DGND RESET SH_R, SCLK SEN CMOS Digital Output DC Specifications (SH, CLK1 to CLK10, CMOS Data Outputs) VOH VOL IOS IOZ Logical "1" Output Voltage Logical "0" Output Voltage Output Short Circuit Current CMOS Output TRI-STATE Current Logical "1" Input Current Logical "0" Input Current Differential LVDS Clock High Threshold Voltage VILL Differential LVDS Clock Low Threshold Voltage IOUT = -0.5mA IOUT = 1.6mA VOUT = DGND VOUT= VD VOUT = DGND VOUT = VD VIH = VD VIL = DGND RL = 100W VCM (LVDS Input Common Mode Voltage)= 1.25V -100 mV 16 -20 20 -25 90 90 100 nA nA mV nA 2.95 0.25 V V mA 70 235 70 A nA A 235 70 130 nA A nA Conditions Min 2.0 0.8 Typ (Note 8) Max Units V V
CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb)
CMOS Digital Input/Output DC Specifications (SDIO) IIH IIL VIHL
LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins)
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LM98714
Electrical Characteristics
(Continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25C. Parameter CMOS Clock High Threshold Voltage VILC IIHL IILC CMOS Clock Low Threshold Voltage CMOS Clock Input High Current CMOS Clock Input Low Current -150 A 280 A 0.8 V Conditions INCLK- = DGND Min 2.0 Typ (Note 8) Max Units V
Symbol VIHC
LVDS Output DC Specifications VOD VOS IOS IA Differential Output Voltage LVDS Output Offset Voltage Output Short Circuit Current VA Analog Supply Current VOUT = 0V, RL = 100 VA Normal State VA Low Power State (Powerdown) IR VR Digital Supply Current VR Normal State (LVDS Outputs) CMOS Output Data Format LVDS Output Data Format with Data Outputs Disabled ID VD Digital Output Driver Supply Current LVDS Output Data Format CMOS Output Data Format (ATE Loading of CMOS Outputs > 50pF) IC VC CCD Timing Generator Output Driver Supply Current Typical sensor outputs: SH, CLK1=1A, CLK2=2A, CLK3=B, CLK4=C, CLK5=RS, CLK6=CP (ATE Loading of CMOS Outputs > 50pF) PWR Average Power Dissipation LVDS Output Data Format CMOS Output Data Format (ATE Loading of CMOS Outputs > 50pF) Input Sampling Circuit Specifications VIN Input Voltage Level CDS Gain=1x, PGA Gain=1x CDS Gain=2x, PGA Gain= 1x 2.3 1.22 Vp-p 350 380 505 610 650 700 mW mW 0.5 12 mA 12 15 47 47 0.05 40 55 mA mA mA mA 30 64 75 mA 60 12 RL = 100 180 1.17 328 1.23 7.9 97 23 125 32 450 1.3 mV V mA mA mA
Power Supply Specifications
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Electrical Characteristics
(Continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25C. Parameter Sample and Hold Mode Input Leakage Current Conditions Source Followers Off CDS Gain = 1x OSX = VA (OSX = AGND) Source Followers Off CDS Gain = 2x OSX = VA (OSX = AGND) Source Followers On CDS Gain = 2x OSX = VA (OSX = AGND) CSH Sample/Hold Mode Equivalent Input Capacitance (see Figure 11) IIN_CDS RCLPIN CDS Mode Input Leakage Current CLPIN Switch Resistance (OSX to VCLP Node in Figure 8) CDS Gain = 2x Source Followers Off OSX = VA (OSX = AGND) -300 4 7 (-25) 16 50 300 pF nA CDS Gain = 1x 2.5 pF -200 -10 -16 200 nA 75 (-105) 105 (-75) A Min 50 (-70) Typ (Note 8) Max 70 (-40) Units A
Symbol IIN_SH
VCLP Reference Circuit Specifications VCLP DAC Resolution VCLP DAC Step Size VVCLP VCLP DAC Voltage Min Output VCLP DAC Voltage Max Output Resistor Ladder Enabled ISC VCLP DAC Short Circuit Output Current Resolution Monotonicity Offset Adjustment Range Referred to AFE Input CDS Gain = 1x Minimum DAC Code = 0x000 Maximum DAC Code = 0x3FF CDS Gain = 2x Minimum DAC Code = 0x000 Maximum DAC Code = 0x3FF Offset Adjustment Range Referred to AFE Output DAC LSB Step Size DNL Differential Non-Linearity Minimum DAC Code = 0x000 Maximum DAC Code = 0x3FF CDS Gain = 1x Referred to AFE Output -0.95 -16000 16000 1.2 (32) 3.25 -307 mV 307 -18200 18200 LSB -614 mV 614 VCLP Config. Register = 0001 0000b VCLP Config. Register = 0001 1111b VCLP Config. Register = 0010 xxxxb VCLP Config. Register = 0001 xxxxb 10 Guaranteed by characterization Bits 30 mA 1.54 VA / 2 1.73 V 2.38 2.68 2.93 V 0.14 4 0.16 0.26 0.43 Bits V V
Black Level Offset DAC Specifications
mV (LSB) LSB
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LM98714
Electrical Characteristics
(Continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25C. Parameter Integral Non-Linearity Gain Resolution Monotonicity Maximum Gain Minimum Gain PGA Function Channel Matching CDS Gain = 1x CDS Gain = 1x CDS Gain = 1x CDS Gain = 1x 7.18 17.1 0.56 -5 Conditions Min -3.1 8 Guaranteed by characterization 7.9 17.9 0.7 -3 8.77 18.9 0.82 -1.72 V/V dB V/V dB Typ (Note 8) Max 2.65 Units LSB Bits
Symbol INL PGA Specifications
Gain (V/V) = (196/(280-PGA Code)) Gain (dB) = 20LOG10(196/(280-PGA Code)) Minimum PGA Gain Maximum PGA Gain 3 12.7 2.07 0.89 1.07 1.18 65535 0 7 Referred to AFE Output Min DAC Code =7b0000000 Mid DAC Code =7b1000000 Max DAC Code = 7b1111111 16 -1024 0 1008 LSB Bits LSB 1.29 V V V %
ADC Specifications VREFT VREFB VREFT VREFB Top of Reference Bottom of Reference Differential Reference Voltage Overrange Output Code Underrange Output Code Digital Offset "DAC" Specifications Resolution Digital Offset DAC LSB Step Size Offset Adjustment Range Referred to AFE Output
Full Channel Performance Specifications DNL INL SNR Differential Non-Linearity Integral Non-Linearity Total Output Noise Minimum PGA Gain -0.99 -73 0.8/-0.6 +/-23 -79 7.2 PGA Gain = 1x -74 13 Maximum PGA Gain -56 104 Channel to Channel Crosstalk Mode 3 Mode 2 47 16 30 2.55 78 LSB LSB dB LSB RMS dB LSB RMS dB LSB RMS LSB
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not recommended. Note 2: All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two.
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Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX - TA)/JA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through 0. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per note 3. However, input errors will be generated If the input goes above VA and below AGND.
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Note 8: Typical figures are at TA = 25C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed.
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LM98714 - Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead TSSOP NS Package Number MTD48
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant.
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