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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6227A/D
1M x 1 Bit Static Random Access Memory
The MCM6227A is a 1,048,576 bit static random-access memory organized as 1,048,576 words of 1 bit, fabricated using high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227A is equipped with a chip enable (E) pin. In less than a cycle time after E goes high, the part enters a low-power standby mode, remaining in that state until E goes low again. The MCM6227A is available in 400 mil, 28-lead surface-mount SOJ packages. * * * * * * Single 5 V 10% Power Supply Fast Access Times: 20, 25, 35, and 45 ns Equal Address and Chip Enable Access Times Input and Output are TTL Compatible Three-State Output Low Power Operation: 160/140/130/120 mA Maximum, Active AC
MCM6227A
WJ PACKAGE 400 MIL SOJ CASE 810-03
PIN ASSIGNMENT
A0 A1 A2 A3 A4 A5 NC A6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A19 A18 A17 A16 A15 A14 NC A13 A12 A11 A10 D E
BLOCK DIAGRAM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER MEMORY MATRIX 1024 ROWS x 1024 COLUMNS V CC VSS
A7 A8 A9 Q W VSS
PIN NAMES
A0 - A19 . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable D . . . . . . . . . . . . . . . . . . . . . . . . Data Input Q . . . . . . . . . . . . . . . . . . . . . Data Output NC . . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground
D
INPUT DATA CONTROL
COLUMN I/O COLUMN DECODER
Q
E A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 W
REV 4 5/95
(c) Motorola, Inc. 1994 MOTOROLA FAST SRAM
MCM6227A 1
MCM6227A TRUTH TABLE
E H L L W X H L Mode Not Selected Read Write I/O Pin High-Z Dout High-Z Cycle -- Read Write Current ISB1, ISB2 ICCA ICCA
H = High, L = Low, X = Don't Care
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to 7.0 - 0.5 to VCC + 0.5 20 1.1 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Storage Temperature Tstg - 55 to + 150 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns). ** VIH (max) = VCC = 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width 20 ns). Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Max 5.5 VCC + 0.3** 0.8 Unit V V V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6227A-20: tAVAV = 20 ns MCM6227A-25: tAVAV = 25 ns MCM6227A-35: tAVAV = 35 ns MCM6227A-45: tAVAV = 45 ns AC Standby Current (VCC = max, E = VIH, f = fmax) CMOS Standby Current (E VCC - 0.2 V, Vin VSS + 0.2 V or VCC - 0.2 V, VCC = max, f = 0 MHz) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) * Typical values are measured at 25C, VCC = 5 V. Symbol Ilkg(I) Ilkg(O) ICCA -- -- -- -- ISB1 ISB2 VOL VOH -- -- -- 2.4 120 110 100 90 7 4 -- -- 160 140 130 120 20 15 0.4 -- mA mA V V Min -- -- Typ* -- -- Max 1 1 Unit A A mA
MCM6227A 2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance Input and Output Capacitance All Inputs Except Clocks and D, Q E and W D, Q Symbol Cin Cin, Cout Typ 4 5 5 Max 6 8 8 Unit pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLE TIMING (See Notes 1 and 2)
6227A-20 Parameter Read Cycle Time Address Access Time Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Power Up Time Power Down Time Symbol tAVAV tAVQV tELQV tAXQX tELQX tEHQZ tELICCH tEHICCL Min 20 -- -- 5 5 0 0 -- Max -- 20 20 -- -- 9 -- 20 6227A-25 Min 25 -- -- 5 5 0 0 -- Max -- 25 25 -- -- 10 -- 25 6227A-35 Min 35 -- -- 5 5 0 0 -- Max -- 35 35 -- -- 12 -- 35 6227A-45 Min 45 -- -- 5 5 -- 0 -- Max -- 45 45 -- -- 18 -- 45 Unit ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 4 Notes 2,3
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E VIL).
AC TEST LOADS
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM6227A 3
READ CYCLE 1 (See Notes 1, 2, and 8)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 4)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX Q (DATA OUT) HIGH-Z tAVQV tELICCH DATA VALID tEHICCL tEHQZ
ICC SUPPLY CURRENT ISB
MCM6227A 4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
6227A-20 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold TIme Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 20 0 15 15 10 0 0 5 0 Max -- -- -- -- -- -- 9 -- -- 6227A-25 Min 25 0 17 17 10 0 0 5 0 Max -- -- -- -- -- -- 10 -- -- 6227A-35 Min 35 0 20 20 15 0 0 5 0 Max -- -- -- -- -- -- 15 -- -- 6227A-45 Min 45 0 25 25 20 0 0 5 0 Max -- -- -- -- -- -- 20 -- -- Unit ns ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled See Notes 1 and 2)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHDX tWHDX tWHAX
MOTOROLA FAST SRAM
MCM6227A 5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
6227A-20 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tWLEH tDVEH tEHDX tEHAX Min 20 0 15 15 15 10 0 0 Max -- -- -- -- -- -- -- -- 6227A-25 Min 25 0 17 17 17 10 0 0 Max -- -- -- -- -- -- -- -- 6227A-35 Min 35 0 20 20 20 15 0 0 Max -- -- -- -- -- -- -- -- 6227A-45 Min 45 0 25 25 25 20 0 0 Max -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns 4, 5 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high-impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high-impedance state.
WRITE CYCLE 2 (E Controlled See Notes 1 and 2)
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELWH tEHAX
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
6227A
WJ
XX
XX
Shipping Method (R2 = Tape and Reel, Blank = Rails) Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns, 45 = 45 ns) Package (WJ = 400 mil SOJ)
Full Part Numbers -- MCM6227AWJ20 MCM6227AWJ25 MCM6227AWJ35 MCM6227AWJ45
MCM6227AWJ20R2 MCM6227AWJ25R2 MCM6227AWJ35R2 MCM6227AWJ45R2
MCM6227A 6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
28 LEAD 400 MIL SOJ CASE 810-03
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. DIM A B C D E F G H K L M N P R S MILLIMETERS MIN MAX 18.29 18.54 10.04 10.28 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 -- 1.14 0.89 0.64 BSC 5 0 1.14 0.76 11.30 11.05 9.65 9.15 1.01 0.77 INCHES MIN MAX 0.720 0.730 0.395 0.405 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC -- 0.020 0.035 0.045 0.025 BSC 5 0 0.030 0.045 0.435 0.445 0.360 0.380 0.030 0.040
MOTOROLA FAST SRAM
MCM6227A 7
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MCM6227A 8
CODELINE TO BE PLACED HERE
*MCM6227A/D*
MCM6227A/D MOTOROLA FAST SRAM

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