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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
DESCRIPTION
The PLUS405-55 device is a bipolar, programmable state machine of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the 8 on-chip State Registers (QP0 - QP7). Two complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C0, C1). All state transition terms can include True, False and Don't Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all of the 64 transition terms can be connected to any or all of the State and Output Registers. All state (QP0 - QP7) and output (QF0 - QF7) registers are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level "1". This feature allows the state machine to be asynchronously initialized to known internal state and output conditions prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to "1". If desired, the initialization input pin (INIT) can be converted to an Output Enable (OE) function as an additional user-programmable feature. Availability of two user-programmable clocks allows the user to design two independently clocked state machine functions consisting of four state and four output bits each. Order codes are listed in the Ordering Information Table below.
FEATURES
* 66.7MHz minimum guaranteed clock rate * 55MHz minimum guaranteed operating * Functional superset of PLS105/105A * Field-programmable (Ti-W fusible link) * 16 input variables * 8 output functions * 64 transition terms * 8-bit State Register * 8-bit Output Register * 2 transition Complement Arrays * Multiple clocks * Programmable Asynchronous Initialization * Power-on preset of all registers to "1" * "On-chip" diagnostic test mode features for * 950mW power dissipation (typ.) * TTL compatible * J-K or S-R flip-flop functions * Automatic "Hold" states * 3-State outputs
APPLICATIONS
access to state and output registers or Output Enable frequency (1/(tIS1 + tCKO1)
PIN CONFIGURATIONS
N Package
CLK 1 I7 2 I6 3 I5/CLK 4 I4 5 I3 6 I2 7 I1 8 I0 9 F7 10 F6 11 F5 12 F4 13 GND 14 28 VCC 27 I8 26 I9 25 I10 24 I11 23 I12 22 I13 21 I14 20 I15 19 INIT/OE 18 F0 17 F1 16 F2 15 F3
N = Plastic DIP (600mil-wide)
A Package
I5/CLK I6 4 I4 5 I3 6 I2 7 I1 8 I0 9 F7 10 F6 11 12 13 14 15 16 17 18 3 I7 CLK VCC I8 1 28 27 2 I9 26 25 I10 24 I11 23 I12 22 I13 21 I14 20 I15 19 INIT/OE
* Interface protocols * Sequence detectors * Peripheral controllers * Timing generators * Sequential circuits * Elevator contollers * Security locking systems * Counters * Shift registers
F5 F4 GND F3 F2 F1 F0 A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION 28-Pin Plastic Dual In-Line (600mil-wide) 28-Pin Plastic Leaded Chip Carrier OPERATING FREQUENCY 55MHz (tIS + tCKO) 55MHz (tIS + tCKO) ORDER CODE PLUS405-55N PLUS405-55A DRAWING NUMBER 0413B 0401F
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
PIN DESCRIPTION
PIN NO. 1 SYMBOL CLK1 NAME AND FUNCTION Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both state and output registers. Pin 1 only clocks P0-3 and F0-3 if Pin 4 is also being used as a clock. Logic Inputs: The 12 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of "H" and "L". Logic Input/Clock: A user programmable function: POLARITY Active-High (H)
2, 3, 5-9, 26-27 20-22 4
I0 - I4, I7, I6 I8 - I9 I13 - I15 CLK2
Active-High/Low (H/L)
* Logic Input: A 13th external logic input to the AND array, as above. * Clock: A 2nd clock for the State Registers P4-7 and Output Registers F4-7, as above.
Note that input buffer I5 must be deleted from the AND array (i.e., all fuse locations "Don't Care") when using Pin 4 as a Clock. 23 I12 Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard TTL or CMOS levels. When I12 is held at +10V, device outputs F0-F7 reflect the contents of State Register bits P0-P7. The contents of each Output Register remains unaltered. Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when exercising standard TTL levels. When I11 is held at +10V, device outputs F0-F7 become direct inputs for State Register bits P0-P7; a Low-to-High transition on the appropriate clock line loads the values on pins F0-F7 into the State Register bits P0-P7. The contents of each Output Register remains unaltered. Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercising standard TTL levels. When I10 is held at +10V, device outputs F0-F7 become direct inputs for Output Register bits Q0-Q7; a Low-to-High transition on the appropriate clock line loads the values on pins F0-F7 into the Output Register bits Q0-Q7. The contents of each State Register remains unaltered. Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which normally reflect the contents of Output Register Bits Q0-Q7, when enabled. When I12 is held at +10V, F0-F7 = (P0-P7). When I11 is held at +10V, F0-F7 become inputs to State Register bits P0-P7. When I10 is held at +10V, F0-F7 become inputs to Output Register bits Q0-Q7. Initialization or Output Enable Input: A user programmable function:
Active-High/Low (H/L) Active-High (H)
Active-High/Low (H/L)
24
I11
Active-High/Low (H/L)
25
I10
Active-High/Low (H/L)
10-13 15-18
F0 - F7
Active-High (H)
19
INIT/OE
* Initialization: Provides an asynchronous preset to logic "1" or reset to logic "0" of all State and Output Register bits, determined individually for each register bit through user programming. INIT overrides Clock, and when held High, clocking is inhibited and F0-F7 and P0-P7 are in their initialization state. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after INIT goes Low. See timing definition for tNVCK and tVCK. * Output Enable: Provides an output enable function to buffers F0-F7 from the Output
Registers.
Active-High (H)
Active-Low (L)
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
TRUTH TABLE 1, 2, 3, 4, 5, 6, 7
OPTION VCC INIT H L L L L L L H +5V X X X X L L L L L L OE I10 * +10V +10V X X X X X +10V +10V X X X X X X X X X I11 * X X +10V +10V X X X X X +10V +10V X X X X X X X I12 * X X X X +10V X * X X X X +10V X X X X X X CK X J X X X X X X X X X X X X X X L L H H X K X X X X X X X X X X X X X X L H L H X QP H/L QP QP L H QP QP QP QP QP L H QP QP QP L H QP H
PLUS405-55
QF H/L L H QF QF QF QF QF L H QF QF QF QF QF L H QF H
F QF L H L H QP QF Hi-Z L H L H QP QF QF L H QF

X X X

X X

X
X
X
NOTES: 1. Positive Logic: S/R (or J/K) = T0 + T1 + T2 + . . . T63 Tn = (C0, C1) (I0, I1, I2, . . .) (P0, P1, . . . P7) 2. Either Initialization (Active-High) or Output Enable (Active-Low) are available, but not both. The desired function is a user-programmable option. 3. denotes transition from Low-to-High level. 4. * = H or L or +10V 5. X = Don't Care (<5.5V) 6. H/L implies that either a High or a Low can occur, depending upon user-programmed selection (each State and Output Register individually programmable). 7. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels on the output pins are forced by the user.
VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that: 1. INIT/OE is set to INIT. In order to use the INIT function, the user must select either the PRESET or the RESET option for each flip-flop. Note that regardless of the user-programmed initialization, or even if the INIT function is not used, all registers are preset to "1" by the power-up procedure. 2. All transition terms are inactive (0). 3. All S/R (or J/K) flip-flop inputs are disabled (0). 4. The device can be clocked via a Test Array preprogrammed with a standard test pattern. 5. Clock 2 is inactive.
LOGIC FUNCTION
Q3 1 Q2 0 Q1 1 Q0 0 SR PRESENT STATE A B C ... Sn + 1 NEXT STATE
STATE REGISTER 0 0 0 1
SET Q0: J0 = (Q2 Q1 Q0) A B C . . . K0 = 0 RESET Q1: J1 = 0 K1 = (Q3 Q2 Q1 Q0) A B C . . .

HOLD Q2: J2 = 0 K2 = 0 RESET Q3: J3 = (Q3 Q2 Q1 Q0) A B C . . . K3 = (Q3 Q2 Q1 Q0) A B C . . .

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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
FUNCTIONAL DIAGRAM
P63 I P0
15
I/CLK
X2
J (4) K P 4 4
Q
R
J (4) K P 4 4
Q
R
J (4)
Q 4
K P 4 4
F R
J (4) K P 4 4
Q
CK
R
4
F
INIT/OE
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
LOGIC DIAGRAM
DETAIL A I0 9 I1 8 I2 7 I3 6 I4 5 I5/CLK 4 I6 3 I7 2 I8 27 I9 26 I10 25 I11 24 I12 23 I13 22 I14 21 I15 20 19 INIT/OE
DETAIL B
DETAIL C 18 F0 17 F1 16 F2 15 F3 13 F4 12 F5 11 F6 10 F7 1 CLK NOTE: Denotes a programmable fuse location.
DETAIL D
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
DETAILS FOR REGISTERS FOR PLUS405
TO INIT LINE TO AND ARRAY
STATE REGISTERS J 19 INIT/OE Q P K CLK R Ps
Detail A
TO INIT LINE OUTPUT REGISTERS J Q P K CLK R Fn FROM PIN 4 (I5/CLK)
Detail B
FROM PIN 1 CLK
Detail C
Detail D
COMPLEMENT ARRAY DETAIL
P63 P62 P2 P1 P0 C0 C1
A
B
D
E C1
C0
TO OR ARRAY
The Complement Array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms. The concept is deceptively simple. If you subscribe to the theory that the expressions (/A * /B * /C) and (A + B + C) are equivalent, you will begin to see the value of this single term NOR array. The Complement Array is a single OR gate with inputs from the AND array. The output of the Complement Array is inverted and fed back to the AND array (NOR). The output of the array will be Low if any one or more of the
AND terms connected to it are active (High). If, however, all the connected terms are inactive (Low), which is a classic unknown state, the output of the Complement Array will be High. Consider the Product Terms A, B and D that represent defined states. They are also connected to the input of the Complement Array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to Product Term E, which could be used in turn to reset the state machine to a known state. Without the Complement Array, one would have to generate product terms for
all unknown or illegal states. With very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources. Note that the PLUS405 sequencers have 2 Complement Arrays which allow the user to design 2 independent Complement functions. This is particularly useful if 2 independent state machines have been implemented on one device. Note that use of the Complement Array adds an additional delay path through the device. Please refer to the AC Electrical Characteristics for details.
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input currents Output currents Operating temperature range Storage temperature range RATINGS +7 +5.5 +5.5 -30 to +30 +100 0 to +75 -65 to +150 UNIT VDC VDC VDC mA mA
PLUS405-55
THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150C 75C 75C
C C
NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
DC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75V VCC 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT
Input voltage2 VIH VIL VIC Output VOH VOL High Low Clamp3 voltage2 High Low VCC = MIN, IOH = -2mA VCC = MIN, IOL = 9.6mA 2.4 0.35 0.45 V V VCC = MAX VCC = MIN VCC = MIN, IIN = -12mA -0.8 2.0 0.8 -1.2 V V V
Input current IIH IIL High Low VCC = MAX, VIN = VCC VCC = MAX, VIN = 0.45V <1 -20 30 -250 A A A A mA mA
Output current IO(OFF) Hi-Z state VCC = MAX, VOUT = 2.7V VCC = MAX, VOUT = 0.45V IOS ICC Capacitance CIN COUT Input Output VCC = 5.0V, VIN = 2.0V VCC = 5.0V, VOUT = 2.0V 8 10 pF pF Short circuit
3, 4
1 -1 -15 190
40 -40 -70 225
VOUT = 0V VCC = MAX
VCC supply current5
NOTES: 1. All typical values are at VCC = 5V. Tamb = +25C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Duration of short-circuit should not exceed one second. 5. ICC is measured with the INIT/OE input grounded, all other inputs at 4.5V and the outputs open.
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
AC ELECTRICAL CHARACTERISTICS
R1 = 470, R2 = 1k, CL = 30pF, 0C Tamb +75C, 4.75V VCC 5.25V LIMITS SYMBOL Pulse width tCKH1 tCKL1 tCKP1 tCKH2 tCKL2 tCKP2 tINITH Setup time tIS1 tIS2 tVS tVCK tNVCK Hold time tIH Input CK+ Input 0 -5 ns Input Input (through Complement Array) Power-on preset Clock resume (after Initialization) Clock lockout (before Initialization) Input Input VCC+ INIT- CK- CK+ CK+ CK- CK- INIT- 10 18 0 0 12 9 15 -10 -5 5 ns ns ns ns ns Clock High; CLK1 (Pin 1) Clock Low; CLK1 (Pin 1) CLK1 Period Clock High; CLK2 (Pin 4) Clock Low; CLK2 (Pin 4) CLK2 Period Initialization pulse CK+ CK- CK+ CK+ CK- CK + INIT- CK- CK+ CK+ CK- CK+ CK + INIT+ 7.5 7.5 15 7.5 7.5 15 14 6 6 12 6 6 12 12 ns ns ns ns ns ns ns PARAMETER FROM TO MIN TYP1 MAX UNIT
Propagation delay tCKO1 tCKO2 tOE
2
Clock1 (Pin 1) Clock2 (Pin 4) Output Enable Output Disable Initialization Power-on Preset
CK1+ CK2+ OE- OE+ INIT+ VCC +
Output Output Output - Output + Output + Output +
6.5 7.0 6.5 6.5 12 0
8 8 8 8 18 10
ns ns ns ns ns ns
tOD2 tINIT tPPR
Notes on following page
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
AC ELECTRICAL CHARACTERISTICS (Continued)
R1 = 470, R2 = 1k, CL = 30pF, 0C Tamb +75C, 4.75V VCC 5.25V LIMITS SYMBOL Frequency of operation CLK1; (without Complement Array) fMAX1 1 t IS1 ) t CKO1 CLK2; (without Complement Array) fMAX2 1 t IS1 ) t CKO2 CLK1; (with Complement Array) fMAX3 1 t IS2 ) t CKO1 CLK2; (with Complement Array) fMAX4 1 t IS2 ) t CKO2 Internal feedback without Complement Array (CLK1 or CLK2) fMAX5 1 t CKL ) t CKH Internal feedback with Complement Array (CLK1 or CLK2) fMAX6 1 t IS2 fCLK Minimum guaranteed Clock frequency Input Output 55.6 62.5 MHz Input Output 55.6 64.5 MHz PARAMETER FROM TO MIN TYP1 MAX UNIT
Input through Complement Array Input through Complement Array
Output
38.5
46.5
MHz
Output
38.5
45.5
MHz
Register Output Register Output through Complement Array CK +
Register Input
66.7
83.3
MHz
Register Input CK +
55.6
66.7
MHz
66.7
83.3
MHz
NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. All propagation delays and setup times are measured and specified under worst case conditions.
TEST LOAD CIRCUIT
VCC +5V S1
VOLTAGE WAVEFORMS
+3.0V 90% 10%
C1
C2 I0 F0
R1
0V tR tF
2.5ns +3.0V CL
2.5ns 90%
INPUTS
I15
DUT F7
R2
10% OUTPUTS 0V 2.5ns 2.5ns
CK
INIT/OE GND
NOTE: C1 and C2 are to bypass VCC to GND.
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
TIMING DIAGRAMS
+3V I0 - I15 1.5V 1.5V 0V tIH CLK tIS 1.5V tCKH tCKP F0 - F7 1.5V tCKO fMAX OE 1.5V tOD 1.5V VOL +3V 1.5V 0V tOE tIS +3V 1.5V tCKL 1.5V 0V
VOH
Sequential Mode
+3V I0 - I15 1.5V 0V +3V CLK tIS F0 - F7 1.5V 1.5V 1.5V 1.5V 0V tCKO 1.5V tCKH 1.5V tCKL VOH 1.5V VOL
INIT
1.5V tINITH
Asynchronous Initialization
4.5V VCC
tPPR
F0 - F7
1.5V
[Fn] = 1
CLK
1.5V tCKH tVS
I0 - I15
1.5V tIS tIH
Power-On Preset
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CCCCCC CCCCCC CCCCCC CCCCCC
tVCK tNVCK 1.5V tCKO 1.5V 1.5V fMAX
tINIT
tCKO +3V
1.5V 0V
+5V
CCCCC CCCCC CCCCC CCCCC
0V
VOH [Fn] + 1 VOL +3V 0V
+3V 1.5V 0V
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
TIMING DIAGRAMS (Continued)
I0 - I11, I13 - I15 +3V 1.5V 0V +10V 8.0V I12 1.5V 1.5V 0V tIH CLK tIS Q0 - Q7 INTERNAL STATE REG. (PS) 1.5V tCKH (NS) 1.5V 0V +3V 8.0V +3V
tSRE
F0 - F7
(Fn)
1.5V tCKO
(Fn+1)
1.5V
OE
Diagnostic Mode - State Register Outputs
+10V 8.0V I11 8.0V +3V 0V +3V 0V +3V 0V VOH VOL
F0 - F7 (INPUTS)
CLK
()
QP STATE REG.
I10
F0 - F7 (INPUTS)
CLK
()
QF STATE REG.
October 22, 1993
EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EEEEE EEEEEEEEE EEEEE EEEEEEEEE EEEEE EEEEEEEEE EEEEE EEEEEEEEE
tRJS
1.5V
(FORCED DIN)
tIS
Diagnostic Mode - State Register Input Jam
8.0V
EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EEEEE EEEEEEEEE EEEEE EEEEEEEEE EEEEE EEEEEEEEE EEEEE EEEEEEEEE
tRJS
1.5V
(FORCED DIN)
tIS
Diagnostic Mode - Output Register Input Jam
190
EEE EEE EEE EEE
tSRD (NS) 1.5V tRH 1.5V tCKH tCKO 1.5V tRH 1.5V tCKH tCKO
EEEE EEEE EEEE EEEE
VOH VOL VOH 1.5V (Fn+1) VOL
0V
tRJH
1.5V
(DIN)
+10V 8.0V +3V 0V +3V 0V +3V 0V VOH VOL
tRJH
1.5V
(DIN)
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
TIMING DEFINITIONS
SYMBOL tCKH1, 2 tCKP1, 2 tIS1 PARAMETER Width of input clock pulse. Minimum guaranteed clock period. Required delay between beginning of valid input and positive transition of Clock. Delay between positive transition of Clock and when Outputs become valid (with INIT/OE Low). Delay between VCC (after power-on) and when Outputs become preset at "1". Required delay between beginning of valid Input and positive transition of Clock, when using optional Complement Array (two passes necessary through the AND Array). Required delay between positive transition of clock, and return of input I10, I11 or I12 from Diagnostic Mode (10V). Minimum guaranteed operating frequency; input to output (CLK1 and CLK2). Minimum guaranteed operating frequency; input through Complement Array, to output (CLK1 and CLK2). Minimum guaranteed internal operating frequency; with internal feedback from state register to state register. tNVCK SYMBOL fMAX6 PARAMETER Minimum guaranteed internal operating frequency with Complement Array, with internal feedback from state register through Complement Array, to state register. Minimum guaranteed clock frequency (register toggle frequency). Interval between clock pulses. Required delay between positive transition of Clock and end of valid Input data. Delay between beginning of Output Enable Low and when Outputs become valid. Delay between input I12 transition to Diagnostic Mode and when the Outputs reflect the contents of the State Register. Required delay between inputs I11, I10 or I12 transition to Diagnostic Mode (10V), and when the output pins become available as inputs. Required delay between the negative transition of the clock and the negative transition of the Asynchronous Initialization to guarantee that the clock edge is not detected as a valid negative transition. tINIT SYMBOL tINITH PARAMETER Width of initialization input pulse. Required delay between VCC (after power-on) and negative transition of Clock preceding first reliable clock pulse. Delay between beginning of Output Enable High and when Outputs are in the OFF-state. Delay between positive transition of Initialization and when Outputs become valid. Delay between input I12 transition to Logic mode and when the Outputs reflect the contents of the Output Register. Required delay between positive transition of Clock and end of valid Input data when jamming data into State or Output Registers in diagnostic mode. Required delay between negative transition of Asynchronous Initialization and negative transition of Clock preceding first reliable clock pulse.
tVS
fCLK
tCKO1, 2
tOD
tCKL1, 2 tIH
tPPR
tIS2
tOE
tSRD
tSRE
tRJH
tRH
tRJS
fMAX1, 2
tVCK
fMAX3, 4
fMAX5
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
LOGIC PROGRAMMING
The PLUS405-55 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABELTM and CUPLTM design software packages also support the PLUS405-55 architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLUS405-55 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only. To implement the desired logic functions, each logic variable (I, B, P, S, T, etc.) from the logic equations is assigned a symbol. TRUE, COMPLEMENT, PRESET, RESET, OUTPUT ENABLE, INACTIVE, etc., symbols are defined below.
INITIALIZATION/OE OPTION - (INIT/OE)
INIT/OE INIT/OE
INIT E=1 (ALWAYS ENABLED) OPTION INITIALIZATION1 CODE H
INIT = 0 (INITIALIZATION DISABLED)
E
OPTION OE
CODE L
PROGRAMMING THE PLUS405: The PLUS405 has a power-up preset feature. This feature insures that the device will power-up in a known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state.
INITIALIZATION OPTION - (INIT)
P
R
P
R
P
R
P
R
INIT ACTION INDETERMINATE4 CODE O ACTION PRESET
INIT CODE H ACTION RESET
INIT CODE L ACTION INDETERMINATE4
INIT CODE -
"AND" ARRAY - (I), (P)
i, p I, P i, p I, P i, p i, p I, P i, p i, p I, P i, p i, p
Tn STATE INACTIVE1, 2 CODE O STATE I, P
Tn CODE H STATE I, P
Tn CODE L STATE DON'T CARE
Tn CODE -
Notes are on next page.
ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.
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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
"OR" ARRAY - J-K FUNCTION - (N), (F)
Tn N, F J Q N, F Tn J Q N, F Tn J Q N, F Tn J Q
N, F
K
N, F
K
N, F
K
N, F
K
ACTION TOGGLE1, 6
CODE O
ACTION SET
CODE H
ACTION RESET
CODE L
ACTION NO CHANGE
CODE -
"COMPLEMENT" ARRAY - (C)
c c c c
c Tn ACTION INACTIVE1, 3 CODE O ACTION GENERATE Tn
c Tn ACTION PROPAGATE
c Tn ACTION TRANSPARENT
c
CODE A
CODE
*
CODE -
CLOCK OPTION - (CLK1/CLK2)
CLK2 CLK2
PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information.
CLK1 OPTION CLK1 ONLY1 CODE L OPTION
CLK1 CODE H
CLK1 and CLK2 5
NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Tn will be unconditionally inhibited if any one of its I or P link pairs is left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn. 4. These states are not allowed when using INITIALIZATION option. 5. Input buffer I5 must be deleted from the AND array (i.e., all fuse locations "Don't Care") when using second clock option. 6. A single product term cannot drive more than 8 registers by itself when used in TOGGLE mode.
October 22, 1993
193
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
PLUS405 PROGRAM TABLE
AND
INACTIVE I, P I, P DON'T CARE 0 H L Im, Ps INACTIVE GENERATE PROPAGATE TRANSPARENT 0
OR
OPTIONS
0 H L Ns, Fr CLK1 ONLY CLK1 AND 2 L H CLK1/ CLK2 INIT OE H L INIT/OE
*
A Cn
INACTIVE OR TOGGLE SET RESET NO CHANGE
-
-
-
INITIALIZATION/OUTPUT ENABLE CLOCK 1/2 AND COMP. INPUT (Im) PRESENT STATE (Ps) ARRAY C1 C0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 P7 P6 P5 P4 P3 P2 P1 P0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 PIN NO. PIN LABELS 2 0 2 1 2 2 22 34 2 5 22 67 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 5 1 6 1 7 1 8 OR NEXT STATE (Ns) OUTPUT (Fr)
N7 N6 N5 N4 N3 N2 N1 N0 F7 F6 F5 F4 F3 F2 F1 F0
DATE REV CF (XXXX) CUSTOMER NAME PHILIPS DEVICE # PROGRAM TABLE CUSTOMER SYMBOLIZED PART #
NOTES: 1. The device is shipped with all links initially intact. Thus, a background of "0" for all Terms, and an "H" for the IN/E and H for the clock option, exists in the table, shown BLANK instead for clarity. 2. Unused Cn Im, and Ps bits are normally programmed Don't Care (--). 3. Unused Transition Terms can be left blank for future code modification, or programmed as (--) for maximum speed.
October 22, 1993
194
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic sequencer (16 x 64 x 8)
PLUS405-55
SNAP RESOURCE SUMMARY DESIGNATIONS
P63 I DIN405 NIN405 DIN405 P0
15
I/CLK
NIN405
AND NOR X2 JKFF405 CK405
J (4) K P 4 4
Q
R
J (4) K P 4
Q
R
CK405 4
J (4)
Q 4
K P 4 4
F R OUT405
J (4) K P 4 4
Q
CK
R
4
F
OUT405
INIT/OE
October 22, 1993
195

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