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5-BIT REGISTERED TRANSCEIVER SY100S891 FEATURES s s s s s s s s 25 cut-off bus outputs 50 receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs (BUS) 1500ps max. delay from CLK2 to Receiver Outputs (Q) Individual bus enable pins Internal 75K input pull-down resistors Voltage and temperature compensation for improved noise immunity s Industry standard 100K ECL levels s Extended supply voltage option: VEE = -4.2V to -5.5V s Available in 28-pin PLCC package DESCRIPTION The SY100S891 is a 5-bit registered transceiver containing five bus transceivers with both transmit and receive registers. The bus outputs (BUS0 - BUS4) are specified for driving a 25 ohm bus and the receive outputs (Q0 - Q4) are specified for driving a 50 ohm line. The bus outputs have a normal high level output voltage and a normal low level output voltage when the bus enable (BUSEN0 - BUSEN4) is high. However, the output is switched to a cut-off level when a bus-enable is low. This cut-off level is sufficiently low that a relatively high impedance is presented to the bus in order to minimize reflections. There is one bus-enable for each bus driver; a clock (CLK1) which is common to all five bus driver registers; and a separate clock (CLK2) which is common to all five receive registers. Data at the D inputs is clocked to the Bus register by a positive transition of CLK1 and data on the bus is clocked into the Receiver register by a positive transition of CLK2. A high on the Master Reset clears all registers. PIN CONFIGURATION PIN NAMES Pin Function Bus Enable Inputs Data Inputs Bus Driver Clock Input Receive Register Clock Master Reset Bus Receive Outputs Bus Outputs BUSEN3 D4 BUSEN4 BUSEN0-4 BUS 4 VCCA Q4 D3 D0 - D4 CLK1 CLK2 18 17 25 24 23 22 21 20 19 MR CLK2 CLK1 VEE D2 BUSEN2 D1 26 27 28 1 2 3 4 5 6 7 8 9 10 11 Q3 BUS3 VCC Q2 BUS2 VCCA Q1 MR Q0 - Q4 BUS0-4 TOP VIEW PLCC J28-1 16 15 14 13 12 D0 BUSEN0 Q0 BUSEN1 BUS0 VCCA BUS1 Rev.: E Amendment: /0 1 Issue Date: August, 1998 Micrel SY100S891 BLOCK DIAGRAM D0 DQ RC DQ RC 25 CUTOFF 50 BUS0 Q0 BUSEN0 D1 DQ RC DQ RC 25 CUTOFF 50 BUS1 Q1 BUSEN1 D2 DQ RC DQ RC 25 CUTOFF 50 BUS2 Q2 BUSEN2 D3 DQ RC DQ RC 25 CUTOFF 50 BUS3 Q3 BUSEN3 D4 DQ RC DQ RC 25 CUTOFF 50 BUS4 Q4 BUSEN4 MR CLK1 CLK2 2 Micrel SY100S891 DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND Symbol VCUT VOH VOL VOHA VOLA VOH VOL VOHA VOLA VIH VIL IIL IIH IEE CIN COUT Parameter Cut-off Bus Output Voltage Output HIGH Voltage Bus Output LOW Voltage Bus Output HIGH Voltage Bus Output LOW Voltage Bus Output HIGH Voltage Receiver Output LOW Voltage Receiver Output HIGH Voltage Receiver Output LOW Voltage Receiver Input HIGH Voltage Input LOW Voltage Input LOW Current Input High Current Power Supply Current Input Pin Capacitance Output Pin Capacitance Min. -2200 -1025 -1810 -1035 -- -1025 -1810 -1035 -- -1165 -1810 0.5 -- -216 -- -- Typ. -2160 -955 -1705 -- -- -955 -1705 -- -- -- -- -- -- -- 4 5 Max. -2100 -880 -1620 -- -1610 -880 -1620 -- -1610 -880 -1475 -- 150 -- -- -- Unit mV mV mV mV mV mV mV mV mV mV mV A A mA pF pF VIN = VIH (Min.) or VIL (Max.) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min.) VIN = VIH (Max.) Inputs Open VIN = VIH (Max.) or VIL (Min.) Loading with 50 to -2.0V VIN = VIH (Min.) or VIL (Max.) Condition VIN = VIH (Max.) or VIL (Min.) VIN = VIH (Max.) or VIL (Min.) Loading with 25 to -2.20V Loading with 25 to -2.0V 3 Micrel SY100S891 AC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tS Parameter Propagation CLK1 to Bus Delay(1) Min. 600 500 500 600 500 Typ. 1000 800 800 1000 800 Max. 1500 1200 1200 1500 1200 TA = +25C Min. 600 500 500 600 500 Typ. 1000 800 800 1000 800 Max. 1500 1200 1200 1500 1200 TA = +85C Min. 600 500 500 600 500 Typ. 1000 800 800 1000 800 Max. 1500 1200 1200 1500 1200 Unit ps ps ps ps ps ps -- -- -- -- -- -- 400 400 1000 -- -- -- -- -- -- 400 400 1000 -- -- -- -- -- -- 400 400 1000 ps ps -- -- 500 300 500 300 -- -- -- -- -- -- -- 100 400 400 1000 900 1000 900 -- -- -- 500 300 500 300 -- -- -- -- -- -- -- 100 400 400 1000 900 1000 900 -- -- -- 500 300 500 300 -- -- -- -- -- -- -- 100 400 400 ps 1000 900 ps 1000 900 -- ps Condition Propagation Delay(2) CLK2 to Q Propagation Delay(1) BUSEN to Bus Propagation Delay(1) Master Reset to Bus Propagation Delay(2) Master Reset to Q Set-up Time Bus Wrt CLK2 D Wrt CLK1 Master Reset Release Time Hold Time Bus Wrt CLK2 D Wrt CLK1 Output Rise Time Bus(3) Q(4) Output Fall Time Bus(3) Q(4) Skew (Maximum difference between slowest and fastest path) tREL tH tr tf tskew NOTES: 1. Loaded with 25 to -2.0V 2. Loaded with 50 to -2.0V 3. 25 Load 4. 50 Load PRODUCT ORDERING CODE Ordering Code SY100S891JC SY100S891JCTR Package Type J28-1 J28-1 Operating Range Commercial Commercial 4 Micrel SY100S891 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 5 |
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