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19-3251; Rev 0; 4/04
200Mbps SFP Limiting Amplifier
General Description
The MAX3969 limiting amplifier with PECL data outputs is ideal for low-cost ATM, Fast Ethernet, FDDI and ESCON fiber optic receivers. The MAX3969 features 1mVP-P input sensitivity and an integrated power detector that senses the input signal power. It provides a received-signal-strength indicator (RSSI), which is an analog indication of the power level. Signal strength is also indicated by the complementary TTL loss-of-signal (LOS) outputs and the PECL signaldetect (SD) output, both of which indicate the power level relative to a programmable threshold. The threshold can be adjusted to detect signal amplitudes as low as 2.7mVP-P. An optional squelch function disables switching of the data outputs by holding them at a known state when the signal is below the programmed threshold. The MAX3969 is available in die form and a 4mm x 4mm, 20-pin thin QFN package. 1mVP-P Input Sensitivity Loss-of-Signal Detector with Programmable Threshold TTL LOS and PECL Signal Detect Analog Received-Signal-Strength Indicator Output Squelch Function Compatible with 4B/5B Data Coding
Features
MAX3969
Ordering Information
PART MAX3969ETP MAX3969E/D** TEMP RANGE PINPACKAGE Dice* PKG CODE T2044-2 --
Applications
SFP/SFF Transceivers Fast Ethernet/FDDI Transceivers 155Mbps LAN ATM Transceivers ESCON Receivers FTTx Transceivers
-40C to +85C 20 Thin QFN --
*Dice are designed to operate over a -40C to +100C junction temperature (TJ) range, but are tested and guaranteed only at TA = +25C. **Future product--contact factory for availability.
Typical Application Circuits
SFP OPTICAL RECEIVER WITH DIAGNOSTICS CAZ 0.027F DIAGNOSTIC MONITOR CZP RSSI VCC VCC FILT OUTCIN 0.01F SQUELCH LOS SD 0.1F OUTIN CFILTER 0.01F CZN FILTER VCC VCCO LOS 0.01F RLOS 4.7k TO 10k HOST BOARD VCC +2.97V TO +3.63V
IN-
MAX3969
MAX3657
GND
OUT+ CIN 0.01F
IN+ INV R1 100k VTH
OUT+ GND 150 R2 0.1F 150
Typical Application Circuits continued at end of data sheet. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
200Mbps SFP Limiting Amplifier MAX3969
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage Range (VCC, VCCO) ..........-0.5V to +7.0V Voltage at FILTER, RSSI, IN+, IN-, CZP, CZN, SQUELCH, INV, VTH..................................................-0.5V to (VCC + 0.5V) TTL Output Current (LOS, LOS) .........................................9mA PECL Output Current (OUT+, OUT-, SD) .........................50mA Differential Voltage Between CZP and CZN..........-1.5V to +1.5V Differential Voltage Between IN+ and IN- .............-1.5V to +1.5V Continuous Power Dissipation (TA = +85C) 20-Pin Thin QFN (derate 16.9mW/C above +85C) ....1099mW Operating Junction Temperature Range (die).....-40C to +150C Die Attach Temperature...................................................+400C Storage Temperature Range .............................-50C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, PECL outputs terminated with 50 to VCC - 2V, R1 = 100k, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1)
PARAMETER Supply Current LOS Hysteresis Squelch Input Current PECL Output-Voltage High PECL Output-Voltage Low LOS Assert Accuracy Minimum LOS Assert Input Maximum LOS Deassert Input Input Sensitivity Input Overload TTL Output High TTL Output Leakage TTL Output Low Data Output Transition Time Pulse-Width Distortion LOS, SD Assert/Deassert Time (Note 4) (Note 4) RLOS = 4.7k to 10k (Note 5) IOL = 800A 20% to 80%, Input > 4mVP-P (Note 4) Input > 4mVP-P (Notes 4, 6) CFILTER = 0.01F 0.35 1500 2.4 3.0 1 0.2 0.8 50 10 20 0.5 1.20 250 143 1 4 (Note 3) (Note 3) Input = 7mVP-P or 90mVP-P, 0C to +85C Input = 7mVP-P or 90mVP-P, -40C to +85C -1085 -1830 -3.0 -3.6 CONDITIONS PECL outputs open Input = 4.0mVP-P (Note 2) 3.0 MIN TYP 22 5 27 MAX 45 8.0 100 -880 -1550 +3.0 +3.6 2.7 UNITS mA dB A mV mV dB dB mVP-P mVP-P mVP-P mVP-P V A V ns ps s
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Dice are tested and guaranteed only at TA = +25C. LOS hysteresis = 20log(VLOS-DEASSERT / VLOS-ASSERT). Relative to supply voltage (VCCO). AC characteristics are guaranteed by design and characterization. Input < LOS threshold (LOS = HIGH), VLOS = 2.4V. Pulse-width distortion = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100Mbps 1-0 pattern.
2
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200Mbps SFP Limiting Amplifier MAX3969
Typical Operating Characteristics
(VCC = +3.3V, PECL outputs terminated with 50 to VCC - 2V, R1 = 100k, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (PECL OUTPUTS OPEN)
55 50 45 40 35 30 25 20 15 10 5 0 -40 -15 10 35 60 85 1ns/div 1ns/div AMBIENT TEMPERATURE (C)
MAX3969 toc01
OUTPUT EYE DIAGRAM (VIN = 2mVP-P, 155Mbps, 223 - 1 PRBS)
MAX3969 toc02
OUTPUT EYE DIAGRAM (VIN = 1500mVP-P, 155Mbps, 223 - 1 PRBS)
MAX3969 toc03
60
SUPPLY CURRENT (mA)
200mV/div
200mV/div
TRANSFER FUNCTION
MAX3969 toc04
BIT ERROR RATIO vs. DIFFERENTIAL INPUT VOLTAGE
MAX3969 toc05
RSSI VOLTAGE vs. DIFFERENTIAL INPUT VOLTAGE
2.80 2.60 2.40 VRSSI (V) 2.20 2.00 1.80 1.60 1.40 1.20 1.00 LOS HIGH LOS LOW 155Mbps 223 - 1 PRBS RSSI LOAD > 10k
MAX3969 toc06
1800 DIFFERENTIAL OUTPUT VOLTAGE (mVP-P) 1600 1400 1200 1000 800
10-03 10-04 10-05 BIT ERROR RATIO 10-06 10-07 10-08 10-09 10-10 10-11 155Mbps 223 - 1 PRBS
3.00
600 0.01 0.1 1 10 100 1000 10,000 DIFFERENTIAL INPUT VOLTAGE (mVP-P)
10-12 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DIFFERENTIAL INPUT VOLTAGE (mVP-P) 0.8
1
10
100
1000
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
RSSI VOLTAGE vs. TEMPERATURE (LOS LOW, RSSI LOAD > 10k)
MAX3969 toc07
POWER-DETECT THRESHOLD vs. R2 (R1 = 100k)
MAX3969 toc08
LOSS-OF-SIGNAL HYSTERESIS vs. TEMPERATURE
9 20log (VDEASSERT / VASSERT) (dB) 8 7 6 5 4 3 2 1 0 -40 -15 10 35 60 85 R2 = 10k R2 = 50k 155Mbps 223-1 PRBS
MAX3969 toc09
2.3 2.2 2.1 2.0 VRSSI (V) 1.9 1.8 1.7 1.6 1.5 1.4 -40 -20 0 20 40 60 80 INPUT = 10mVP-P INPUT = 5mVP-P INPUT = 50mVP-P INPUT = 100mVP-P
1000 DIFFERENTIAL INPUT VOLTAGE (mVP-P)
10
100
SD HIGH/ LOS LOW
10
SD LOW/ LOS HIGH
155Mbps 223 - 1 PRBS 1 10 20 30 40 50 60 70 80 90 100 110 120 R2 (k)
100
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
_______________________________________________________________________________________
3
200Mbps SFP Limiting Amplifier MAX3969
Typical Operating Characteristics (continued)
(VCC = +3.3V, PECL outputs terminated with 50 to VCC - 2V, R1 = 100k, TA = +25C, unless otherwise noted.)
POWER-DETECT TIMING WITH SQUELCH (INPUT = 12mVP-P, CFILTER = 0.01F, R2 = 15k, 155Mbps, 223 - 1 PRBS)
MAX3969 toc10
PULSE-WIDTH DISTORTION vs. DIFFERENTIAL INPUT VOLTAGE
90 PULSE-WIDTH DISTORTION (ps) 80 70 60 50 40 30 20 10 0 UNFILTERED INPUT DATA INPUT DATA THROUGH 117MHz FILTER 100Mbps 1-0 PATTERN
MAX3969 toc11
DATA OUTPUT TRANSITION TIME vs. TEMPERATURE
1.4 TRANSITION TIME (ns) 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -15 10 35 60 85
MAX3969 toc12
100
1.6
IN
OUT
LOS
SD
10s/div
1
10
100
1000
10,000
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
AMBIENT TEMPERATURE (C)
Pin Description
PIN 1 NAME INV FUNCTION Inverting Input of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a resistor from VTH to INV (R2), and from INV to ground (R1 = 100k), to program the desired threshold voltage. Filter Output of Logarithmic Full-Wave Detectors (FWDs). The FWD outputs are summed together at FILTER to generate the RSSI output. Connect a capacitor from FILTER to VCC for proper operation. Received-Signal-Strength Indicator Output. The voltage at RSSI indicates the input-signal power. The RSSI output is reduced approximately 120mV when LOS is asserted. Inverting Data Input Noninverting Data Input Ground Autozero Capacitor Input. Connect a 0.027F capacitor between CZP and CZN. Autozero Capacitor Input. Connect a 0.027F capacitor between CZP and CZN. Output-Buffer Supply Voltage. Connect to the same potential as VCC. Noninverting PECL Data Output. Terminate with 50 to (VCC - 2V). Inverting PECL Data Output. Terminate with 50 to (VCC - 2V). Signal Detect, PECL Output. The SD output is high when input power is above the power-detect threshold, and low when input power is below the power-detect threshold. This pin is PECLcompatible and should be terminated with 50 to (VCC - 2V) or equivalent. Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is high when input power is below the power-detect threshold, and low when input power is above the power-detect threshold. Inverted Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is low when input power is below the power-detect threshold, and high when input power is above the power-detect threshold.
2 3 4 5 6 , 7, 8 9 10 11 12 13 14
FILTER RSSI ININ+ GND CZP CZN VCCO OUT+ OUTSD
15
LOS
16
LOS
4
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200Mbps SFP Limiting Amplifier
Pin Description
PIN 17, 18 19 NAME VCC SQUELCH Supply Voltage Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+ high when the signal is below the power-detect threshold. Connect to GND or leave unconnected to disable squelch. Connect to VCC to enable squelch. Output of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a resistor from VTH to INV (R2) and from INV to ground (R1 = 100k), to program the desired threshold voltage. Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. FUNCTION
MAX3969
20 EP
VTH Exposed Pad
CAZ CZP CZN
VCC
VCCO
OFFSET CORRECTION
CIN ININ+ CIN VCC FILTER CFILTER
1.2V REFERENCE
1
MAX3969
1 O
PECL
OUTOUT+ SQUELCH
FWD
FWD
FWD TTL
RSSI LOS LOS PECL SD
R1 100k
INV R2
VTH
GND
Figure 1. Functional Diagram
Detailed Description
The MAX3969 contains a series of limiting amplifiers and power detectors, offset correction, data-squelch circuitry, TTL buffers for LOS outputs, and PECL output buffers for signal detect (SD) and data outputs. See Figure 1 for the functional diagram.
Gain Stages and Offset Correction
A cascade of limiting amplifiers provides approximately 65dB of combined small-signal gain. The large gain makes the amplifier susceptible to small DC offsets in the signal path. To correct DC offsets, the amplifier has an internal feedback loop that acts as a DC autozero
circuit. By correcting the DC offsets, the limiting amplifier sensitivity and power-detector accuracy are improved. The offset correction is optimized for data streams with a 50% duty cycle. A different average duty cycle results in increased pulse-width distortion and loss of sensitivity. The offset-correction circuitry is less sensitive to variations of input duty cycle (for example, the 40% to 60% duty cycle encountered in 4B/5B coding) when the input is less than 30mVP-P. The data inputs must be AC-coupled for the offset correction loop to function properly. Differential input impedance is >5k.
5
_______________________________________________________________________________________
200Mbps SFP Limiting Amplifier MAX3969
Power Detector
Each amplifier stage contains a logarithmic FWD, which indicates the RMS input signal power. The FWD outputs are summed together at the FILTER pin where the signal is filtered by an external capacitor (CFILTER) connected between FILTER and VCC. The FILTER signal generates the RSSI output voltage (VRSSI), which is proportional to the input power in decibels. When LOS is low, VRSSI is approximated by the following equation: VRSSI (V) = 1.2V + 0.5log (VIN) where, VIN is the data input voltage measured in mVP-P. This relation translates to a 25mV increase in VRSSI for every 1dB increase in VIN. The RSSI output is reduced approximately 120mV when LOS is high. Typically the RSSI output is connected to an A/D converter for diagnostic monitoring. This output can be left open if not required in the application. The RSSI output is designed to drive a minimum load resistance of 10k to ground, and a maximum capacitance of 10pF. A 10k series resistor is required to buffer loads greater than 10pF.
PECL Outputs
The data outputs (OUT+, OUT-) and signal-detect output (SD) are supply-referenced PECL outputs. See Figure 2 for the equivalent output circuit. Both data outputs must be terminated for proper operation, but the SD output can be left open if not required in the application. The proper termination for a PECL output is 50 to (VCC - 2V), but other standard termination techniques can be used. For more information on PECL terminations and how to interface with other logic families, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML.
TTL Outputs
The LOS outputs (LOS, LOS) are implemented with open-collector, Schottky-clamped, ESD-protected, TTLcompatible outputs. See Figure 3 for the equivalent output circuit. The LOS outputs require external pullup resistors for proper operation. Resistor values between 4.7k and 10k are recommended. If the LOS outputs are not required for the application, they can be left open.
Signal-Strength Comparator
A comparator is used to indicate the input signal strength relative to a user-programmable threshold. One of the comparator inputs is connected to the RSSI output signal, and the other is connected to the threshold voltage (VTH), which is set externally and provides a trip point for signal-strength indication. When the signal strength is above the threshold, the SD output asserts high and the LOS output deasserts low. Likewise, when the signal strength falls below the threshold, SD deasserts low and LOS asserts high. To ensure chatter-free operation, the comparator is designed with approximately 5dB of hysteresis.
Design Procedure
Program the Power-Detect Threshold
The suggested procedure for setting the power-detect threshold is given below and is illustrated in Figure 4. 1) Determine the maximum receiver sensitivity (RX_MAX) in dBm and the PIN-TIA responsivity (G) in V/W. 2) Calculate the differential voltage swing (VIN_SEN) at the MAX3969 inputs while operating at sensitivity. VIN_SEN = 10(RX_MAX / 10) x 2 x G 3) Calculate the threshold voltage (VIN_TH) at which LOS must be low (SD must be high) by allowing 3.6dB (1.8dB optical) margin for power-detector accuracy. VIN_TH = VIN_SEN x 0.66 4) Use VIN_TH and the line labeled (SD HIGH / LOS LOW) in the Power-Detect Threshold vs. R2 graph in the Typical Operating Characteristics to determine the value of R2. Select R1=100k.
Squelch
The squelch function disables the data outputs by forcing OUT- low and OUT+ high when the input signal is below the programmed threshold. This function ensures that when there is a loss of signal, the limiting amplifier and all downstream devices do not respond to input noise. Connect SQUELCH to GND or leave it unconnected to disable squelch. Connect SQUELCH to VCC to enable squelch.
6
_______________________________________________________________________________________
200Mbps SFP Limiting Amplifier MAX3969
10 log(OPTICAL POWER) VCCO PIN-TIA RESPONSIVITY = G RX_MAX (SENSITIVITY) 1.8dB SD HIGH / LOS LOW 2.5dB SD LOW / LOS HIGH
OUTOUT+ ESD STRUCTURES 5dB 3.6dB 20 log(VIN)
VIN_TH VIN_SEN
Figure 4. Signal Levels for Power-Detect Threshold
Select CFILTER
For SFP/SFF, FDDI, 155Mbps ATM LAN, Fast Ethernet, and ESCON receivers, Maxim recommends CFILTER = 0.01F. This capacitor value ensures chatter-free LOS/SD and provides a typical assert/deassert time of 10s. For other applications, the value of CFILTER can be calculated using the following equation: CFILTER = / 825 where is the desired time constant of the power detector.
Figure 2. Equivalent PECL Output Circuit
VCCO
Select CAZ and CIN
External-coupling capacitors (CIN) are required on the data inputs for the offset correction loop to function properly. The offset correction loop bandwidth is determined by the external capacitor (C AZ ) connected between CZP and CZN. The poles associated with CIN and CAZ must work together to provide a flat response at the lower -3dB corner frequency. For SFP/SFF, FDDI, 155Mbps ATM LAN, Fast Ethernet, and ESCON receivers, Maxim recommends the following: CIN = 0.01F CAZ = 0.027F
LOS/LOS
ESD STRUCTURES
Figure 3. Equivalent TTL Output Circuit
_______________________________________________________________________________________
7
200Mbps SFP Limiting Amplifier MAX3969
Applications Information
Wire Bonding
For high-current density and reliable operation, the MAX3969 uses gold metalization. For best results, use gold-wire ball-bonding techniques. Use caution if attempting wedge bonding. Die pad size is 4 mils x 4 mils. Die thickness is 16 mils. Table 1 lists the bond pad coordinates for the MAX3969. The origin for pad coordinates is defined as the bottom left corner of the bottom left pad. All pad locations are referenced from the origin and indicate the center of the pad where the bond wire should be connected. Refer to Maxim Application Note HFAN-08.0.1: Understanding Bonding-Coordinates and Physical Die Size for detailed information.
Table 1. Bond Pad Coordinates
PAD 1 2 3 4 5 6 7 8 9 10 11 12 NAME INV FILTER RSSI ININ+ GND GND GND CZP CZN VCCO OUT+ OUTSD LOS LOS VCC VCC SQUELCH VTH COORDINATES (m) X 46.6 46.6 46.6 46.6 46.6 195.1 432.7 589.3 743.2 945.7 1204.9 1204.9 1204.9 1204.9 1204.9 1053.7 808.0 586.6 432.7 195.1 Y 659.5 505.6 351.7 197.8 46.6 -99.1 -99.1 -99.1 -99.1 -99.1 -96.4 81.7 262.6 492.1 697.3 818.8 818.8 818.8 818.8 818.8
Pin Configuration
SQUELCH
13 14 15 16 17 18 19 20
TOP VIEW
20
INV FILTER RSSI ININ+
19
18
17
16 15 14
LOS SD
1 2 3 4 5 6
GND
LOS
VCC
VCC
VTH
MAX3969
13 12 11
OUTOUT+
VCCO
Chip Information
TRANSISTOR COUNT: 915 SUBSTRATE CONNECTED TO GND PROCESS: Silicon Bipolar DIE THICKNESS: 16 mils
7
GND
8
GND
9
CZP
10
CZN
THIN QFN
8
_______________________________________________________________________________________
200Mbps SFP Limiting Amplifier MAX3969
Chip Topography
VTH SQUELCH VCC VCC LOS
20
19
18
17
16 15 LOS
INV
1
FILTER
2
14
SD 47mil (1.19mm)
RSSI
3 13 OUT-
IN-
4 12 OUT+
IN+ ORIGIN
5
6
7
8
9
10
11
VCCO
GND
GND
GND 57mil (1.45mm)
CZP
CZN
_______________________________________________________________________________________
9
200Mbps SFP Limiting Amplifier MAX3969
Typical Application Circuits (continued)
CAZ 0.027F CFILTER 0.01F CZP RSSI VCC VCC FILT OUTCIN 0.01F SQUELCH LOS SD OUTIN CZN FILTER VCC VCCO LOS VCC
SFF OR 1 x 9 MSA RECEIVER
0.01F
IN-
MAX3969
MAX3657
GND
OUT+ CIN 0.01F
IN+ INV R1 100k VTH
OUT+ GND 50 50 50
R2 VCC - 2V
10
______________________________________________________________________________________
200Mbps SFP Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
MAX3969
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
1
2
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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