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| Genesis Microchip Publication DATA SHEET GMZAN2 Flat Panel Monitor Controller IC Publication number: C0022-DAT-01D Publication date: August 2002 Genesis Microchip Inc. 2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365 165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422 George Thangiah Complex(E), 2nd Floor, 80 Feet Road, Jeevan Bhima Nagar, Bangalore 560 075, India, Tel 91-80-526 3878 Fax 91-80-529 6245 4F , No 57 , Sing Jung Road , NeiHu , Taipei, Taiwan 114 .R.O.C Tel: 886-2-2791-0118 Fax: 886-2-2791-0196 143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090 Tel 82-2-553-5693 Fax 82-2-552-4942 Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guandong, P.R.C., Tel (0755)386-0101, Fax (0755)386-7874 2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759 www.genesis-microchip.com / info@genesis-microchip.com GMZAN2 Data Sheet Document History: Revision C0022-DAT-01A C0022-DAT-01B Initial Release Description Date June 2001 4 pins were changed from reserve to three VSS (pin 5, July 2001 59 and 147) one VDD (pin 60). Voltages have been swapped (pin 40 and108) from 2.5V to 3.3V and vice versa (pin 125); Table 3 and Table 6 Added ESM in section 1 and 2.1.15 and updated October 2001 section 3 with measured values Changed max. external OSD Clock frequency to 80MHz August 2002 in section 2.8.4 and in Table 18 and Figure 14 C0022-DAT-01C C0022-DAT-01D Related Documents: Doc Number C0022-PBR-01C C0021-DAT-01F GMZAN2 Product Brief gmZAN1 Data Sheet Title Copyright 2002, Genesis Microchip Inc. All Rights Reserved. Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. It is the customer's responsibility to obtain the most recent revision of the document. Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or omissions that may appear in this document. GMZAN2 Data Sheet Table of Contents 1. Overview .......................................................................................................................... 1 1.1 Features .................................................................................................................... 2 1.2 Pin Out Diagram........................................................................................................ 3 1.3 Pin Description .......................................................................................................... 4 1.4 System-level Block Diagram ................................................................................... 10 1.5 Operating Modes..................................................................................................... 11 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 Native ................................................................................................................ 11 Slow DCLK ........................................................................................................ 11 Zoom ................................................................................................................. 12 Downscaling (Recovery).................................................................................... 12 Destination Stand Alone .................................................................................... 12 Source Stand Alone .......................................................................................... 12 2. Functional Description ................................................................................................. 13 2.1 Overall Architecture................................................................................................. 13 2.2 Clock Recovery Circuit ............................................................................................ 13 2.2.1 2.2.2 2.2.3 2.3.1 2.3.2 2.4.1 2.4.2 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.6.1 2.6.2 2.6.3 2.6.4 2.7.1 Reset................................................................................................................. 15 Sampling Phase Adjustment ............................................................................. 15 Source Timing Generator .................................................................................. 15 Pin Connection .................................................................................................. 16 Display Mode Support ....................................................................................... 18 Source Timing Measurement ............................................................................ 18 IRQ Controller ................................................................................................... 19 Scaling Filter...................................................................................................... 20 Gamma Table.................................................................................................... 20 RGB Offset ........................................................................................................ 21 Panel Data Dither .............................................................................................. 21 Panel Background Color.................................................................................... 21 TFT Panel Interface Timing Specification.......................................................... 21 Power Manager ................................................................................................. 24 Energy Spectrum Management (ESM).............................................................. 26 Panel Interface Drive Strength .......................................................................... 26 Serial Communication Protocol ......................................................................... 27 2.3 Analog-to-Digital Converter ..................................................................................... 16 2.4 Input Timing Measurement...................................................................................... 18 2.5 Data Path ................................................................................................................ 20 2.6 Panel Interface ........................................................................................................ 21 2.7 Host Interface .......................................................................................................... 26 August 2002 -iii- C0022-DAT-01D GMZAN2 Data Sheet 2.7.2 2.7.3 2.8.1 2.8.2 2.8.3 2.8.4 2.9.1 2.9.2 Four bit Parallel Host interface .......................................................................... 29 Multi-Function Bus (MFB).................................................................................. 31 OSD Color Map ................................................................................................. 31 On-Chip OSD Controller.................................................................................... 31 Built-in OSD Fonts............................................................................................. 34 External OSD Support ....................................................................................... 35 External Oscillator mode ................................................................................... 37 Internal Oscillator mode .................................................................................... 38 2.8 On-Screen Display Control...................................................................................... 31 2.9 On-chip TCLK Oscillator.......................................................................................... 37 2.10 Sleep Mode Power Down........................................................................................ 41 3. Electrical Characteristics ............................................................................................. 42 4. Ordering Information .................................................................................................... 43 5. Mechanical Dimensions ............................................................................................... 44 August 2002 -iv- C0022-DAT-01D GMZAN2 Data Sheet Table of Figures Figure 1. GMZAN2 Pin Diagram....................................................................................... 3 Figure 2. Typical Stand-alone Configuration.................................................................. 10 Figure 3. Block Diagram for GMZAN2 ............................................................................ 13 Figure 4. Clock Recovery Circuit ................................................................................... 14 Figure 5. Capture Window ............................................................................................. 16 Figure 6. GMZAN2 Data Path......................................................................................... 20 Figure 7. Timing Diagrams of the TFT Panel Interface (one pixel per clock)................. 23 Figure 8. Data latch timing of the TFT Panel Interface .................................................. 24 Figure 9. Panel Power Sequence .................................................................................. 25 Figure 10. Timing Diagram of the GMZAN2 Serial Communication ................................. 28 Figure 11. Timing diagram for read/write using 4-bit Parallel Host Interface ................... 30 Figure 12. On-Chip OSD Window Location ..................................................................... 33 Figure 13. Built-in OSD Fonts .......................................................................................... 35 Figure 14. External OSD Interface Data Latch Timing..................................................... 36 Figure 15. Using an External Oscillator ........................................................................... 38 Figure 16. Using an Internal Oscillator............................................................................ 39 Figure 17. Internal Oscillator output at TCLK................................................................... 39 Figure 18. Parasitic Capacitance Sources....................................................................... 40 Figure 19. 160 pin PQFP Package Dimensions .............................................................. 44 August 2002 -v- C0022-DAT-01D GMZAN2 Data Sheet List of Tables Table 1. Analog-to-Digital Converter .............................................................................. 4 Table 2. Host Interface (HIF) / External On-Screen Display........................................... 5 Table 3. Clock Recovery / Time Base Conversion ......................................................... 6 Table 4. TFT Panel Interface .......................................................................................... 7 Table 5. Test Pins & Reserve Pins ................................................................................. 8 Table 6. VDD / VSS for Core Circuitry, Host Interface, and Panel/Memory Interface .... 9 Table 7. Clock Recovery Characteristics...................................................................... 15 Table 8. Pin Connection for RGB Input with HSync/Vsync........................................... 16 Table 9. Pin Connection for RGB Input with Composite Sync...................................... 17 Table 10. ADC Characteristics ....................................................................................... 17 Table 11. Input Timing Parameters Measured by the STM Block .................................. 18 Table 12. IRQ-Generation Conditions ............................................................................ 19 Table 13. GMZAN2 TFT Panel Interface Timing ............................................................. 22 Table 14. Panel Interface Pad Drive Strength ................................................................ 26 Table 15. GMZAN2 Serial Channel Specification............................................................ 29 Table 16. Programmability of On-chip OSD Locations ................................................... 34 Table 17. Pin Connection Between the GMZAN2 and an External OSD controller ........ 36 Table 18. External OSD Interface Timing Parameters ................................................... 37 Table 19. TCLK Specification ......................................................................................... 37 Table 20. Absolute Ratings............................................................................................. 42 Table 21. DC Electrical Characteristic ............................................................................ 42 August 2002 -vi- C0022-DAT-01D GMZAN2 Data Sheet 1. OVERVIEW The GMZAN2 is a continuation of Genesis Microchips's successful and most widely adopted design, the gmZAN1, used in the analog interface mainstream XGA LCD monitors. It provides a further overall cost reduction alternative to the existing gmZAN1 designs with lower power consumption. It is as fully featured as the gmZAN1 by integrating the Genesis patented Display Perfection Technology as well as the latest generation of analog mixed signal technology that has proven to be high-quality and most reliable. In addition, the GMZAN2 includes Energy Spectrum Management that helps further reduce the cost associated with the LCD monitors meeting emissions standards by reducing EMI. It may eliminate the use of parallel-to-serial transmitter and serial-to-parallel receiver devices As shown Figure 2, the GMZAN2 has an integrated the Genesis sixth generation ADC and is feature compatible to the gmZAN1. It is the LCD monitor controller for the mainstream XGA LCD monitors. It provides a very cost-effective and simplified design. A reference design is available to demonstrate the GMZAN2 solution. August 2002 -1- C0022-DAT-01D GMZAN2 Data Sheet 1.1 Features Feature Overview * Fully integrated 135MHz 8-bit tripleADC, PLL, and pre-amplifier * Adaptive Contrast Enhancement (ACE) scaling * On-chip programmable OSD engine * Integrated PLLs * 10-bit programmable gamma correction * Host interface with 1 or 4 data bits * Pin-compatible & firmware compatible to gmZAN1 * Built In High-Speed Clock Generator * Fully programmable timing parameters * On-chip PLLs generate clocks for the on-chip ADC and pixel clock from a single reference oscillator * Auto-Configuration / AutoDetection * Phase and image positioning * Input format detection * Integrated Analog Front End * * * * Integrated 8-bit triple ADC Up to 135MHz sampling rates No additional components needed All color depths up to 24-bits/pixel are supported * Operating Modes * Bypass mode with no filtering * Multiple zoom modes: with filtering with adaptive (ACE) filtering * Integrated On-Screen Display * On-chip character RAM and ROM for better customization * External OSD supported for greater flexibility * Many other font capabilities including: blinking, overlay and transparency * High-Quality Advanced Scaling * Fully programmable zoom * Independent horizontal / vertical zoom * Enhanced and adaptive scaling algorithm for optimal image quality * Recovery Mode / Native Mode * * Input Format * Analog RGB up to XGA 85Hz Package * 160-pin PQFP Output Format * Support for 8 or 6-bit panels (with high quality dithering) * One or two pixel output format August 2002 -2- C0022-DAT-01D GMZAN2 Data Sheet 1.2 Pin Out Diagram Figure 1. GMZAN2 Pin Diagram 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 OSD_DATA3 OSD_FSW MFB11 MFB10 DVDD DVSS DAC_DGNDA DAC_DVDDA PLL_DVDDA Reserved PLL_DGNDA SUB_DGNDA SUB_SGNDA PLL_SGNDA Reserved PLL_SVDDA DAC_SVDDA DAC_SGNDA SVDD SVSS TCLK XTAL PLL_RVDDA PLL_RGNDA Reserved SUB_RGNDA CVSS5 VSYNC SYN_VDD HSYNC/CS SYN_VSS Reserved STI_TM1 STI_TM2 SCAN_IN1 Reserved SCAN_IN2 SRVSS2 SCAN_OUT1 SCAN_OUT2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 OSD_DATA2 OSD_DATA1 OSD_DATA0 OSD_CLK OSD_VREF OSD_HREF CVSS4 MFB0 MFB1 MFB2 MFB3 MFB4 RVDD3A MFB5 MFB6 MFB7 MFB8 HCLK MFB9 IRQ RESETn HDATA HFS N/C ADC_RVDDA RED+ REDADC_RGNDA ADC_GVDDA GREEN+ GREENADC_GGNDA ADC_BVDDA BLUE+ BLUEADC_BGNDA ADC_VDDA Reserved ADC_GNDA SUB_GNDA 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 GMZAN2 (160-Pin PQFP) ADC_GND1 ADC_VDD1 ADC_GND2 ADC_VDD2 PPWR PBIAS PHS PVS CVSS3 PD0 PD1 PD2 PD3 PD4 PD5 RVDD3 PD6 PD7 PD8 RVSS4 RVDD2B CVSS2A CVDD2 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 RVSS3 PD17 PD18 PD19 PCLKB PCLKA PDISPE PD20 CVSS2 August 2002 CVSS1 Reserved PSCAN Reserved CVSS!A PD47 PD46 RVSS1 PD45 PD44 SRVDD1 RVDD1 PD43 PD42 PD41 PD40 PD39 SRVSS1 PD38 PD37 SRVDD2 PD36 PD35 PD34 PD33 PD32 PD31 PD30 PD29 RVSS2 PD28 PD27 RVDD2 PD26 PD25 PD24 PD23 PD22 PD21 RVDD2A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 -3- C0022-DAT-01D GMZAN2 Data Sheet 1.3 Pin Description Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open. Table 1. Pin Name In/Out Drive Current (@10pF) 77 78 79 80 81 82 ADC_VDD2 ADC_GND2 ADC_VDD1 ADC_GND1 SUB_GNDA ADC_GNDA 2.5V 2.5V Digital power for ADC encoding logic. Must be bypassed with 0.1 uF capacitor to pin 78 (ADC_GND2) Digital GND for ADC encoding logic. Must be directly connected to the digital system ground plane. Digital power for ADC clocking circuit. Must be bypassed with 0.1 uF capacitor to pin 80 (ACD_GND1) Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane. Dedicated pin for substrate guard ring that protects the ADC reference system. Must be directly connected to the analog system ground plane. Analog ground for ADC analog blocks that are shared by all three channels. Includes bandgap reference, master biasing and full scale adjust. Must be directly connected to analog system ground plane. 3.3V Analog power for ADC analog blocks that are shared by all three channels. Includes bandgap reference, master biasing and full scale adjust. Must be bypassed with 0.1 uF capacitor to pin 82 (ADC_GNDA). Test output. Do not connect. Analog ground for the blue channel. Must be directly connected to the analog system ground plane. 3.3V In In Analog power for the blue channel. Must be bypassed with 0.1 uF capacitor to pin 85 (BGNDA). Negative analog input for the Blue channel. Positive analog input for the Blue channel. Analog ground for the green channel . Must be directly connected to the analog system ground plane. 3.3V In In Analog power for the green channe. Must be bypassed with 0.1 uF capacitor to pin 89 (ADC_GGNDA). Negative analog input for the Green channel. Positive analog input for the Green channel. Analog ground for the red channel. Must be directly connected to the analog sys tem ground plane. 3.3V In In Analog power for the red channel. Must be bypassed with 0.1 uF capacitor to pin 93 (ADC_RGNDA). Negative analog input for the Red channel. Positive analog input for the Red channel. Analog-to-Digital Converter Voltage Description 84 ADC_VDDA 83 85 88 86 87 89 92 90 91 93 96 94 95 Reserved ADC_BGNDA ADC_BVDDA BLUEBLUE+ ADC_GGNDA ADC_GVDDA GREENGREEN+ ADC_RGNDA ADC_RVDDA REDRED+ August 2002 -4- C0022-DAT-01D GMZAN2 Data Sheet Table 2. Pin Name Host Interface (HIF) / External On-Screen Display Voltage Description Current (@10pF) In / Out Drive 98 103 99 100 101 115 116 117 118 119 120 121 122 123 124 102 104 105 106 HFS HCLK HDATA RESETn IRQ OSD-HREF OSD-VREF OSD-Clk OSD-Data0 OSD-Data1 OSD-Data2 OSD-Data3 OSD-FSW MFB11 MFB10 MFB9 MFB8 MFB7 MFB6 in in in/out in out out out out in in in in in in/out in/out in/out in/out in/out in/out 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA 4 mA 4 mA 8 mA 4 mA Host Frame Sync. Frames the packet on the serial channel. Clock signal input for the 3-wire serial communication. Data signal for the 3-wire serial communication Resets the GMZAN2 chip to a known state when low. Interrupt request output HSYNC output for an external OSD controller chip. VSYNC output for an external OSD controller chip. Clock output for an external OSD controller chip. Data input 0 from an external OSD controller. Data input 1 from an external OSD controller. Data input 2 from an external OSD controller. Data input 3 from an external OSD controller. External OSD window display enable. Displays data from external OSD con troller when high. Multi-Function Bus 11. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 10. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 9. One of twelve multi-function signals MFB[11:0]. Also used as HDATA3 in a 4-bit host interface configuration. Multi-Function Bus 8. One of twelve multi-function signals MFB[11:0]. Also used as HDATA2 in a 4-bit host interface configuration. Multi-Function Bus 7. One of twelve multi-function signals MFB[11:0]. Also used as HDATA1 in a 4-bit host interface configuration. Multi-Function Bus 6. One of twelve multi-function signals MFB[11:0]. Internally pulled up. When externally pulled down (sampled at reset) the host interface is configured for 4 bits wide. In this configuration, MFB9:7 are used as HDATA3:1. Multi-Function Bus 5. One of twelve multi-function signals MFB[11:0]. Internally pulled up. When externally pulled down (sampled at reset) the chip uses an external crystal resonator across pins 141 and 142, instead of an oscillator. Multi-Function Bus 4. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 3. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 2. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 1. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 0. One of twelve multi-function signals MFB[11:0]. 107 MFB5 in/out 8 mA 109 110 111 112 113 MFB4 MFB3 MFB2 MFB1 MFB0 in/out in/out in/out in/out in/out 8 mA 8 mA 8 mA 8 mA 8 mA August 2002 -5- C0022-DAT-01D GMZAN2 Data Sheet Table 3. Pin Name Clock Recovery / Time Base Conversion Voltage Description In / Out Drive Current (@10pF) 125 127 128 129 130 131 132 133 134 135 136 137 138 139 141 142 DVDD DAC_DGNDA DAC_DVDDA PLL_DVDDA Reserved PLL_DGNDA SUB_DGNDA SUB_SGNDA PLL_SGNDA Reserved PLL_SVDDA DAC_SVDDA DAC_SGNDA SVDD TCLK XTAL In Out 2.5V Digital power for Destination DDS (direct digital synthesizer). Must be bypassed with a 0.1 uF capacitor to digital ground plane. Analog ground for Destination DDS DAC. Must be directly connected to the ana log system ground plane. 3.3V 3.3V Analog power for Destination DDS DAC. Must be bypassed with a 0.1 uF capaci tor to pin 127 (DAC_DGNDA) Analog power for the Destination DDS PLL. Must be bypassed with a 0.1 uF capacitor to pin 131 (PLL_DGNDA) Test output. Do not connect. Analog ground for the Destination DDS PLL. Must be directly connected to the analog system ground plane. Dedicated pin for the substrate guard ring that protects the Destination DDS. Must be directly connected to the analog system ground plane. Dedicated pin for the substrate guard ring that protects the Source DDS. Must be directly connected to the analog system ground plane. Analog ground for the Source DDS PLL. Must be directly connected to the ana log system ground. Test output. Do not connect. 3.3V 3.3V Analog power for the Source DDS PLL. Must be bypassed with a 0.1 uF capaci tor to pin 134 (PLL_SGNDA) Analog power for the Source DDS DAC. Must be bypassed with a 0.1 uF capaci tor to pin 138 (DAC_SGNDA) Analog ground for the Source DDS DAC. Must be directly connected to the ana log system ground. 2.5V Digital power for the Source DDS and destination DDS. bypassed with a 0.1 uF capacitor to digital ground plane. Reference clock (TCLK) input from the 50 Mhz crystal oscillator. Must be If using an external oscillator, leave this pin floating. If using an external crystal, connect crystal between TCLK (141) and XTAL (142). See MFB5 (pin 107). 3.3V Analog power for the Reference DDS PLL. Must be bypassed with a 0.1 uF capacitor to pin 144 (PLL_RGNDA) Analog ground for the Reference DDS PLL. Must be directly connected to the analog system ground plane. Test output. Do not connect. Dedicated pin for the substrate guard ring that protects the Reference DDS. Must be directly connected to the analog system ground plane. 143 144 145 146 148 149 150 PLL_RVDDA PLL_RGNDA Reserved SUB_RGNDA VSYNC SYN_VDD HSYNC/ CSYNC In In CRT Vsync input. TTL Schmitt trigger input. 2.5V Digital power for CRT Sync input CRT Hsync or CRT composite sync input. TTL Schmitt trigger input. August 2002 -6- C0022-DAT-01D GMZAN2 Data Sheet Table 4. Pin Name In / Out Drive Current (@10pF) TFT Panel Interface Description 2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk 8-bit 6-bit OB5 OB4 OB3 OB2 OB1 OB0 OG5 OG4 OG3 OG2 OG1 OG0 OR5 OR4 OR3 OR2 OR1 OR0 EB5 EB4 EB3 EB2 EB1 EB0 EG5 EG4 EG3 8-bit B1 B0 G1 G0 R1 R0 B7 B6 B5 B4 B3 B2 G7 G6 G5 6-bit B5 B4 B3 B2 B1 B0 G5 G4 G3 TFT 6 7 9 10 13 14 15 16 17 19 20 22 23 24 25 26 27 28 29 31 32 34 35 36 37 38 39 42 46 47 48 50 51 52 53 54 55 56 57 PD47 PD46 PD45 PD44 PD43 PD42 PD41 PD40 PD39 PD38 PD37 PD36 PD35 PD34 PD33 PD32 PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA OB1 OB0 OG1 OG0 OR1 OR0 EB1 EB0 EG1 EG0 ER1 ER0 OB7 OB6 OB5 OB4 OB3 OB2 OG7 OG6 OG5 OG4 OG3 OG2 OR7 OR6 OR5 OR4 OR3 OR2 EB7 EB6 EB5 EB4 EB3 EB2 EG7 EG6 EG5 August 2002 -7- C0022-DAT-01D GMZAN2 Data Sheet Pin Name In / Out Drive Current (@10pF) Description 2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk 8-bit 6-bit EG2 EG1 EG0 EG5 ER4 ER3 ER2 ER1 ER0 8-bit G4 G3 G2 R7 R6 R5 R4 R3 R2 6-bit G2 G1 G0 R5 R4 R3 R2 R1 R0 TFT 62 63 64 66 67 68 69 70 71 43 74 73 44 45 75 76 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDispE PHS PVS PCLKA PCLKB Pbias Ppwr out out out out out out out out out out out out out out out out 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 2 mA ~ 20 mA 8 mA 8 mA EG4 EG3 EG2 ER7 ER6 ER5 ER4 ER3 ER2 This output provides a panel display enable signal that is active when flat panel data is valid. This output provides the panel line clock signal. This output provides the frame start signal. This output is used to drive the flat panel shift clock. Same as PCLKA above. The polarity and the phase of this signal are independently programmable. This output is used to turn on / off the panel bias power or controls backlight. This output is used to control the power to a flat panel. NOTE: Drive current of the panel output pins are programmable. Table 5. Pin 2 3 Name Reserved PSCAN In Test Pins & Reserve Pins N/C. Do not connect. Enable automatic device test. When this input is pulled high, the automatic device test mode is entered. An internal pull-down resistor drives this input low for normal operation. This pin should always be tied to ground. N/C. Do not connect. N/C. Do not connect. N/C. Do not connect. In/Out Drive Current Description 4 152 156 155 157 159 160 153 154 Reserved Reserved Reserved SCAN_IN1 SCAN_IN2 In In Scan input 1 used for device testing. This pin should always be tied to ground. Scan input 2 used for automatic device testing. This pin should always be tied to ground. Scan output 1 used for automatic device testing. This pin should not be connected. Scan output 2 used for automatic device testing. This pin should not be connected. ST1_TM1 used for automatic device testing. This pin should always be tied to ground. ST1_TM2 used for automatic device testing. This pin should always be tied to ground. SCAN_OUT1 Out SCAN_OUT2 Out ST1_TM1 ST1_TM2 August 2002 -8- C0022-DAT-01D GMZAN2 Data Sheet Table 6. Pins VDD / VSS for Core Circuitry, Host Interface, and Panel/Memory Interface Description RVDD1 ~ RVDD3, RVDD2A, RVDD2B and RVDD3A for panel / memory interface. Connect to +3.3V. SRVDD2-1, CVDD2 and DVDD for core circuitry. Connect to +2.5V. 12, 33, 40, 60, 65, 108 11,21, 58, 125 1, 5, 8, 18, 30, 41, 49, 59, 61, 72, 114, 126, Digital grounds for core circuitry and panel / memory interface. CVSS1, CVSS1A, 140, 147, 151, 158 RVSS1, SRVSS1, RVSS2, CVSS2, RVSS3, CVSS2A, RVSS4, CVSS3, CVSS4, DVSS, SVSS, CVSS5 SYN_VSS and SRVSS2 August 2002 -9- C0022-DAT-01D GMZAN2 Data Sheet 1.4 System-level Block Diagram CVDD ADC_VDD ADC_GND GMZAN2 Core Clock Generator RVDDA RGNDA Red Blue Green ADC TCLK OSC Video Connector SVDDA Hsync Vsync SGNDA To Clock Generator DVDDA DGNDA R+,G+,B+ 4 On-Screen Display Controller OSD-FSW OSD-CLK OSD-HREF OSD-VREF 24 Even Data PCLKA Panel Interface Host Interface PHS PDISPE 24 Odd Data IRQ MPU with EEPROM HES HCLK HDATA Pbias Pbias MFBs RESETn 12 CVSS Power Switching Module +12V +5/3.3V Figure 2. Typical Stand-alone Configuration August 2002 -10- C0022-DAT-01D TFT Panel PVS GMZAN2 Data Sheet 1.5 Operating Modes The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows: * * The Source Clock is the sample clock regenerated from the input Hsync timing (called clock recovery) by SCLK DDS (direct digital synthesis) and the PLL. The Panel Clock is the timing clock for panel data at the single pixel per clock rate. The actual PCLK to the panel may be one-half of this frequency for double-pixel panel data format. When its frequency is different from that of source clock, the panel clock is generated by Destination Clock (or DCLK) DDS / PLL. There are six display modes: Native, Slow DCLK, Zoom, Downscaling, Destination Stand Alone, and Source Stand Alone. Each mode is unique in terms of: * * * * input video resolution vs. panel resolution, Source Clock frequency / Panel Clock frequency ratio, Source Hsync frequency / Panel Hsync frequency ratio, data source (analog RGB, panel background color, on-chip pattern generator) 1.5.1 Native Panel Clock frequency = Source Clock frequency Panel Hsync frequency = Input Hsync frequency Panel Vsync frequency = Input Vsync frequency This mode is used when the input resolution is the same as the panel resolution and the input data clock frequency is within the panel clock frequency specification of the panel being used. 1.5.2 Slow DCLK Panel Clock frequency < Source Clock frequency Panel Hsync frequency = Input Hsync frequency Panel Vsync frequency = Input Vsync frequency This mode is used when the input resolution is the same as the panel resolution, but the input data clock frequency exceeds the panel clock frequency specification of the panel being used. The panel clock is scaled to the Source Clock, and the internal data buffers are used to spread out the timing of the input data by making use of the large CRT blanking time to extend the panel horizontal display time. August 2002 -11C0022-DAT-01D GMZAN2 Data Sheet 1.5.3 Zoom Panel Clock frequency > Source Clock frequency Panel Hsync frequency > Input Hsync frequency Panel Vsync frequency = Input Vsync frequency This mode is used when the input resolution is less than the panel resolution. The input data clock is then locked to the panel clock, which is at a higher frequency. The input data is zoomed to the panel resolution. 1.5.4 Downscaling (Recovery) Panel Clock frequency < Source Clock frequency Panel Hsync frequency < Input Hsync frequency Panel Vsync frequency = Input Vsync frequency This mode is used when the input resolution is greater than the panel resolution, to provide enough of a display to enable the user to recover to a supported resolution. The input clock is operated at a frequency less than that of the input pixel rate (under-sampled horizontally) and the scaling filter is used to drop input lines. In this mode, zoom scaling must be disabled. 1.5.5 Destination Stand Alone Panel Clock = DCLK in open loop (not locked) Panel Hsync frequency = DCLK frequency / (Destination Htotal register value) Panel Vsync frequency = DCLK frequency / (Dest. Htotal register value * Dest. Vtotal register value) This mode is used when the input is changing or not available. The OSD may still be used as in all other display modes and stable panel timing signals are produced. This mode may be automatically set when the GMZAN2 detects input timing changes that could cause out-of-spec operation of the panel. 1.5.6 Source Stand Alone Panel Clock = DCLK in open loop (not locked to input Hsync) Panel Hsync frequency = SCLK frequency / (Source Htotal register value) Panel Vsync frequency = SCLK frequency / (Source Htotal register value * Source Vtotal register value) This mode is used to display the pattern generator data. This mode may be useful for testing an LCD panel on the manufacturing line (color temperature calibration, etc.). August 2002 -12C0022-DAT-01D GMZAN2 Data Sheet 2. FUNCTIONAL DESCRIPTION Figure 3 below shows the main functional blocks inside the GMZAN2. 2.1 Overall Architecture Figure 3. Block Diagram for GMZAN2 On-Screen Display Control Analog RGB Triple ADC Source Timing Measurement / Generation Scaling Engine Gamma Control (CLUT) + Dither Panel Timing Control Panel MCU Host Interface Clock Recovery Pixel Clock Generator Clock Reference 2.2 Clock Recovery Circuit The GMZAN2 has a built-in clock recovery circuit. This circuit consists of a digital clock synthesizer and an analog PLL. The clock recovery circuit generates the clock used to sample analog RGB data (SCLK or source clock). This circuit is locked to the HSYNC of the incoming video signal. The RCLK generated from the TCLK input is used as a reference clock. The clock recovery circuit adjusts the SCLK period so that the feedback pulse generated every SCLK period multiplied by the Source Horizontal Total value (as programmed into the registers) locks to the rising edge of the Hsync input. Even though the initial SCLK frequency and the final August 2002 -13- C0022-DAT-01D GMZAN2 Data Sheet SCLK frequency are as far apart as 60MHz, locking can be achieved in less than 1ms across the operating voltage/temperature range. The SCLK frequency (1/SCLK period) can be set to the range of 10- to 135-MHz. Using the DDS (direct digital synthesis) technology the clock recovery circuit can generate any SCLK clock frequency within this range. The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2). It is generated by a circuit virtually identical to the clock recovery circuit. The difference is that DCLK is locked to SCLK while SCLK is locked to the Hsync input. DCLK frequency divided by N is locked to SCLK frequency divided by M. The values M and N are calculated and programmed in the register by firmware. The value M should be close to the Source Htotal value. Figure 4. Clock Recovery Circuit Hsync Sample Phase Delay DDS Digital Clock Synthesis Course Adjust Fine Adjust DDS Output VCO Output Analog PLL & VCO Clock Divider /n SCLK RCLK PLL Divider /m Prescaler / 2 (or 1) Source Horizontal Total Divider TCLK Analog PLL & VCO Post Scale / 2 (or 1) RCLK PLL Divider / n (2 to 8) Prescaler / 2 (or 1) August 2002 -14- C0022-DAT-01D GMZAN2 Data Sheet The table below summarizes the characteristics of the clock recovery circuit. Table 7. Minimum SCLK Frequency 20 MHz Sampling Phase Adjustment Clock Recovery Characteristics Typical Maximum 135 MHz 0.5 ns/step, 64 steps Patented digital clock synthesis technology makes the GMZAN2 clock circuits very immune to temperature/voltage drift. 2.2.1 Reset A reset pin (RESETn) sets the GMZAN2 to a known state when this pin is pulled low. The RESETn pin must be low for at least 100ns after the CVDD has become stable (between +2.4V and +2.75V) or until the oscillator used is stable or whichever takes longer in order to reset the GMZAN2 to a known state. 2.2.2 Sampling Phase Adjustment The ADC sampling phase is adjusted by delaying the Hsync input at the programmable delay cell inside the GMZAN2. The delay value can be adjusted in 64 steps, 0.5 ns/step. The accuracy of the sampling phase is checked by the GMZAN2 and the "score" can be read in a register. This feature will enable accurate auto-adjustment of the ADC sampling phase. 2.2.3 Source Timing Generator The STG module defines a capture window and sends the input data to the data path block. Figure 5 below shows how the window is defined. For the horizontal direction, it is defined in SCLKs (equivalent to a pixel count). For the vertical direction, it is defined in lines. All the parameters in the figure that begin with "Source" are programmed into the GMZAN2 registers. Note that the vertical total is solely determined by the input. The reference point is as follows: * The first pixel of a line: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high. * The first line of a frame: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high. August 2002 -15C0022-DAT-01D GMZAN2 Data Sheet Figure 5. Capture Window Source Horizontal Total (pixels) Reference Point Source Hstart Source Width Source Vstart Source Vertical Total (lines) Capture Window Source Height 2.3 Analog-to-Digital Converter 2.3.1 Pin Connection The RGB signals are to be connected to the GMZAN2 chip as described in Table 8 and Table 9. Table 8. Pin Connection for RGB Input with HSync/Vsync CRT Signal Name Red N/A (Tie to Analog GND for Red on the board) Green N/A (Tie to Analog GND for Green on the board) Blue N/A (Tie to Analog GND for Blue on the board) Horizontal Sync Vertical Sync GMZAN2 Pin Name (Pin Number) Red+(#95) Red- (#94) Green+ (#91) Green- (+90) Blue+ (#87) Blue- (#86) HSYNC/CS (#150) VSYNC (#148) August 2002 -16- C0022-DAT-01D GMZAN2 Data Sheet Table 9. Red+ (#95) Red- (#94) Green+ (#91) Green- (#90) Blue+ (#87) Blue- (#86) HSYNC/CS (#150) Pin Connection for RGB Input with Composite Sync CRT Signal Name Red N/A (Tie to Analog GND for Red on the board) Green When using Sync-On-Green this signal also carries the sync pulse. N/A (Tie to Analog GND for Green on the board) Blue N/A (Tie to Analog GND for Blue on the board) Digital composite sync. Not applicable for Sync-On-Green GMZAN2 Pin Name (Pin Number) The GMZAN2 chip has three ADC's (analog-to-digital converters), one for each color (red, green, and blue). Table 10 summarizes the characteristics of the ADC. Table 10. ADC Characteristics MIN RGB Track & Hold Amplifiers Band Width Settling Time to 1/2 % Full Scale Adjust Range @ R,G,B Inputs Full Scale Adjust Sensitivity Zero Scale Adjust Range 0.60 V +/- 1 LSB 160 MHz 8.5 ns 0.95 V Measured @ ADC Output (**) For a larger DC offset from an external video source, the AC coupling feature is used to remove the offset. +/- 1 LSB Measured @ ADC Output Full Scale Input = 0.75V, BW=160MHz (*) TYP MAX NOTE Zero Scale Adjust Sensitivity ADC + RGB Track & Hold Amplifiers Sampling Frequency (fs) DNL INL Channel to Channel Matching Effective Number of Bits (ENOB) Power Dissipation Shut Down Current (*) Guaranteed by design 20 MHz +/- 1.5 LSB +/- 0.5 LSB 7 Bits 400 mW 135 MHz +/- 0.9 LSB fs = 80 MHz fs = 80 MHz fin = 1 MHz, fs = 80 MHz Vin= -1 db below full scale = 0.75V fs = 110 MHz, Vdd = 3.3V 100uA (**) Independent of full scale R,G,B input The GMZAN2 ADC has a built-in clamp circuit. By inserting series capacitors (about 10 nF) the DC offset of an external video source can be removed. The clamp pulse position and width are programmable. August 2002 -17- C0022-DAT-01D GMZAN2 Data Sheet 2.3.2 Display Mode Support A mode calculation utility (MODECALC.EXE) provided by Genesis Microchip may be run before compilation of the firmware to determine which input modes can be supported. Refer to firmware documents for more details. 2.4 Input Timing Measurement As described in section 2.2.3 above, input data is sent from the analog-to-digital converter to the source timing generator (STG) block. The STG block defines a capture window (Figure 5). The input timing measurement block consists of the source timing measurement (STM) block and interrupt request (IRQ) controller. Input timing parameters are measured by the STM block and stored in registers. Some input conditions will generate an IRQ to an external microcontroller. The IRQ-generating conditions are programmable. 2.4.1 Source Timing Measurement When it receives the active CRT signal (R, G, B and Sync signals) the Source Timing Measurement unit begins measuring the horizontal and vertical timing of the incoming signal using the sync signals and TCLKi as a reference. Horizontal measurement occurs by measuring a minimum and a maximum value for each parameter to account for TCLKi sampling granularity. The measured value is updated every line. Vertical parameters are measured in terms of horizontal lines. The trailing edge of the Hsync input is used to check the polarity of the Vsync input. The table below lists all the parameters that may be read in the source timing measurement (STM) registers of the GMZAN2. Table 11. Input Timing Parameters Measured by the STM Block Parameter HSYNC Missing VSYNC Missing HSYNC / VSYNC Timing Change Unit N/A N/A N/A Updated at: Every 4096 TCLKs and every 80ms (2-bits) Every 80 ms When the horizontal period delta or the vertical period delta to the previous line / frame exceeds the threshhold value (programmable). After register read Every frame After register read After register read Every frame Every frame Every frame HSYNC Polarity VSYNC Polarity Horizontal Period Min / Max HSYNC High Period Min / Max Vertical Period VSYNC High Period Horizontal Display Start Positive / Negative Positive / Negative TCLKs and SCLKs TCLKs Lines Lines SCLKs August 2002 -18- C0022-DAT-01D GMZAN2 Data Sheet Parameter Horizontal Display End Vertical Display Start Vertical Display End Interlaced Input Detect CRC Data / Line Data CSYNC Detect Unit SCLKs Lines Lines N/A N/A N/A Updated at: Every frame Every frame Every frame Every frame Every frame Every 80 ms The display start / end registers store the first and the last pixels / lines of the last frame that have RGB data above a programmed threshold. The reference point of the STM block is the same as that of the source timing generator (STG) block: * The first pixel: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high. * The first line: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high. The CRC data and the line data are used to detect a test pattern image sent to the GMZAN2 input port. 2.4.2 IRQ Controller Some input timing conditions can cause the GMZAN2 chip to generate an IRQ. The IRQgenerating conditions are programmable, as given in the following table. Table 12. IRQ-Generation Conditions IRQ Event Timing Event Remark One of the following three events: * Leading edge of Vsync input, * Panel line count (the line count is programmable), * Every 10 ms Only one event may be selected at a time. Any of the following timing changes: * Sync loss, * DDS tracking error beyond threshold, * Horizontal / vertical timing change beyond threshold. Threshold values are programmable. Timing Change Reading the IRQ status flags will not affect the STM registers. August 2002 -19- C0022-DAT-01D GMZAN2 Data Sheet Note that if a new IRQ event occurs while the IRQ status register is being read, the IRQ signal will become inactive for a minimum of one TCLK period and then get re-activated. The polarity of the IRQ signal is programmable. 2.5 Data Path The data path block of GMZAN2 is shown in Figure 6. Figure 6. GMZAN2 Data Path Sampled Data (or from pattern generator) 8 8 10 Panel Data Dither 8 or 6 1 0 S 1 0 Internal OSD 1 0 S S 8 or 6 Scaling Filter Gamma Table RGB Offset Background Color Panel Data External OSD 2.5.1 Scaling Filter The GMZAN2 scaling filter uses an advanced adaptive scaling technique proprietary to Genesis Microchip Inc. and provides high-quality scaling of real time video and graphics images. This is Genesis' third generation scaling technology that benefits from the expertise and feedback gained by supporting a wide range of solutions and applications. 2.5.2 Gamma Table The gamma table is used to adjust the RGB data for the individual display characteristics of the TFT panel. The overall gamma of the display may be set, as well as separate corrections for each of the three display channels. In addition, the gamma table may be used for contrast, brightness, and white balance (temperature) adjustments. The lookup table has an 8-bit input (256 different RGB entries) and produces a 10-bit output. August 2002 -20C0022-DAT-01D GMZAN2 Data Sheet 2.5.3 RGB Offset The RGB offsets provide a simple shift (positive or negative) for each of the three color channels. This may be used as a simple brightness adjustment within a limited range. The data is clamped to zero for negative offsets, and clamped to FFh for positive offsets. This adjustment is much faster than recalculating the gamma table, and could be used with the OSD user controller to provide a quick brightness adjust. An offset range of plus 127*4 to minus 127*4 is available. 2.5.4 Panel Data Dither For TFT panels that have fewer than eight bits for each R, G, B input, the GMZAN2 provides ordered and random dithering patterns to help smoothly shade colors on 6-bit panels. 2.5.5 Panel Background Color A solid background color may be selected for a border around the active display area. The background color is most often set to black. 2.6 Panel Interface The GMZAN2 chip interfaces directly with all of today's commonly used active matrix flat panels with 640x480, 800x600 and 1024x768 resolutions. The resolution and the aspect ratio are NOT limited to specific values. 2.6.1 TFT Panel Interface Timing Specification The TFT panel interface timing parameters are listed in Table 13 below. Refer to the three timing diagrams of Figure 7 and Figure 8 for the timing parameter definition. All aspects of the GMZAN2 interface are programmable. For horizontal parameters, Horizontal Display Enable Start, Horizontal Display Enable End, Horizontal Sync Start and Horizontal Sync End are programmable. Vertical Display Enable Start, Vertical Display Enable End, Vertical Sync Start and Vertical Sync End are also fully programmable. In order to maximize panel data setup and hold time, the panel clock (PCLKA, PCLKB) output skew is programmable. In addition, the current drive strength of the panel interface pins is programmable. August 2002 -21- C0022-DAT-01D GMZAN2 Data Sheet Table 13. GMZAN2 TFT Panel Interface Timing Signal Name PVS Period t1 min 0 16.67 60 t2 t3 t4 t5 t6 t18 t19 t7 t8 t9 t10 t11 t12 t13 t14 t15 0 0 0 0 0 1 1 0 0 0 0 0 0 DCLK/2 - 3 DCLK/2 - 3 DCLK/2 - 5 DCLK/2 - 5 3 bits [DCLK - 3] [DCLK - 3] One pxl/clock [two pxl/clock] [DCLK - 5] [DCLK - 5] 18bits [36 bits] Typical Max 2048 2048 2048 2048 2048 2048 2048 2048 2048 [1024] 2048 2048 2048 2048 [1024] 2048 120 [60] DCLK/2 - 2 [DCLK - 2] DCLK/2 - 2 [DCLK - 2] unit lines ms Hz lines lines lines lines lines PCLK PCLK PCLK PCLK PCLK PCLK PCLK PCLK MHz ns ns Frequency front porch back porch pulse width PdispE Disp. start from VS PVS set up to PHS PVS hold from PHS PHS Period front porch back porch pulse width PdispE Disp. start from HS PCLKA, Frequency PCLKB*4 Clock (H) *2 Clock (L) *2 Type Data set up *3 hold *3 Width Panel height Panel width *1 *1 *1 *1 *1 *1 *1 *1 t16 t17 DCLK/2 - 2 [DCLK - 2] ns DCLK/2 - 2 [DCLK - 2] ns 24bits [48bits] bits/pixel NOTE: Numbers in [ ] are for two pixels/clock mode. NOTE: The drive current of the panel interface signals is programmable as shown in Table 1 on page 4. The drive current is to be programmed through the API upon chip initialization. Output current is programmable from 2 mA to 20 mA in increments of 2 mA. Drive strength should be programmed to match the load presented by the cable and input of the panel. Values shown are based on a loading of 20 pF and a drive strength of 8 mA. NOTE *1:The PCLK is the panel shift clock. NOTE *2: The DCLK stands for Destination Clock (DCLK) period. is equal to: - PCLK period in one pixel/clock mode, - twice the PCLK period in two pixels/clock mode. NOTE *3: The setup/hold time spec. for PCLK also applies to PHS and PDispE. The setup time (t16) and the hold time (t17) listed in this table are for the case in which no clock-to-data skew is added. The PVS/PHS/ PDispE/PData signals are asserted on the rising edge of the PCLK. The polarity of the PCLK and its skew are programmable. Clock to Data skew can be adjusted in sixteen 800-ps increments. In combination with the PCLK polarity inversion, the clock-to-data phase can be adjusted in total of 31 steps. NOTE *4: The polarity of the PCLKA and the PCLKB are independently programmable. The microcontroller must have all the timing parameters of the panel used for the monitor. The parameters are to be stored in a non-volatile memory. As can be seen from this table, the wide range of timing programmability of the GMZAN2 panel interface makes it possible to support various kinds of panels known today. August 2002 -22- C0022-DAT-01D GMZAN2 Data Sheet Figure 7. Timing Diagrams of the TFT Panel Interface (one pixel per clock) (a) Vertical size in TFT PVS t1 PHS t3 PDE (b) Vsync width and display position in TFT t4 t18 t19 t5 t2 PVS PHS RGBs t6 (c) Horizontal size in TFT t10 t7 PHS PCLK PDE t12 t11 t8 RGB data from data paths t9 Panel BackgroundColor Displayed (d) Hsync width in TFT t10 t13 t16 t16 t14 t15 August 2002 -23- C0022-DAT-01D GMZAN2 Data Sheet Figure 8. Data latch timing of the TFT Panel Interface (a) Two pixel per clock mode in TFT PDE t16 PCLK t14 R0,(N:0) R2,(N:0) G2,(N:0) t13 t15 t16 R4,(N:0) t17 ER EG G0,(N:0) EB B0,(N:0) R1,(N:0) B2,(N:0) R3,(N:0) OR OG G1,(N:0) G3,(N:0) OB B1,(N:0) B3,(N:0) (b) One pixel per clock mode in TFT PDE t16 t13 t14 t15 t16 t17 PCLK R0 G0 R(n:0) G(n:0) R1 B(n:0) B0 2.6.2 Power Manager LCD panels require logic power, panel bias power, and control signals to be sequenced in a specific order, otherwise severe damage may occur and disable the panel permanently. The GMZAN2 has a built-in power sequencer (Power Manager) that prevents this kind of damage. The Power Manager controls the power up/down sequences for LCD panels within the four states described below. See the timing diagram Figure 9. August 2002 -24C0022-DAT-01D GMZAN2 Data Sheet 2.6.2.1 State 0 (Power Off) The Pbias signal and Ppower signal are low (inactive). The panel controls and data are forced low. This is the final state in the power down sequence. PM is kept in state 0 until the panel is enabled. 2.6.2.2 State 1 (Power On) Intermediate step 1. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is forced low (inactive). 2.6.2.3 State 2 (Panel Drive Enabled) Intermediate step 2. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is active. 2.6.2.4 State 3 (Panel Fully Active) This is the final step in the power up sequence, with Ppower and Pbias high (active), and the panel interface active. PM is kept in this state until the internal TFT_Enable signal controlled by Panel Control register is disabled. The panel can be disabled through either an API call under program control or automatically by the GMZAN2 to prevent damage to the panel. Figure 9. Panel Power Sequence TFT_EN Bit (register bit) t1 t4 t6 PPWR Output Data/Controls Signals t2 t3 t5 PBias Output In Figure 9 above, t2=t6 and t3=t5. t1, t2, t3 and t4 are independently programmable from one to eight steps in length. The length of each step is in the range of 511 * X * (TCLKi cycle) or (TCLKi cycle) * 32193 * X, where X is any positive integer value equal to or less than 256. TCLKi is the reference clock to the GMZAN2 chip, and ranges from 14.318 MHz to 50 MHz in August 2002 -25C0022-DAT-01D GMZAN2 Data Sheet frequency. This programmability provides enough flexibility to meet a wide range of power sequencing requirements by various panels. 2.6.3 Energy Spectrum Management (ESM) High spikes in the electromagnetic interference (EMI) power spectrum can cause LCD monitor products to violate emissions standards. The Energy Spectrum Management in the GMZAN2 uses the following features to reduce EMI: * * ESM Clock Control Programmable Panel Interface Drive strength These features eliminate the costs associated with EMI-reducing components and shielding. In particular, the use of parallel-to-serial transmitter and serial-to-parallel receiver devices may not be necessary. 2.6.4 Panel Interface Drive Strength As mentioned previously, the GMZAN2 has programmable output pads for the TFT panel interface. Three groups of panel interface pads (panel clock, data, and control) are independently controllable and are programmable. Table 14. Panel Interface Pad Drive Strength Value (4 bits) 0 1 2 3 4 5 6 7 8 9 10,11,12,13,14,15 Drive Strength in mA Outputs are in tri-state condition 2 mA 4 mA 6 mA 8 mA 10 mA 12 mA 14 mA 16 mA 18 mA 20 mA 2.7 Host Interface The host microcontroller interface of the GMZAN2 has two modes of operation, a serial interface data transfer mode and a 4-bit parallel interface mode. August 2002 -26C0022-DAT-01D GMZAN2 Data Sheet * Serial interface data transfer mode - Four signals consisting of 1 data bit, a frame synchronization signal, a clock signal and an Interrupt Request signal (IRQ). This mode is entered when a pull-down resistor is not connected to MFB6 (pin number 106). 4-bit parallel interface mode - Three additional data bits are used so that four data bits are transferred on each clock edge. The 4-bit port uses MFB [9:7] as HDATA [3:1] and HDATA is used as HDATA0. The HFS and HCLK are used to control the data transfers. This mode is entered when a pull-down resistor (10K ohm) is connected from MFB6 (pin number 106) to ground. * The host interface mode is selected when the GMZAN2's reset is asserted by sampling the state of MFB6 (pin number 106). The GMZAN2 chip has an on-chip, pull-down resistor in the HFS input pad. The signal stays low until driven high by the microcontroller. The burst mode operation then uses three clocks (instead of twelve) for each 12-bit data (or address) transmission. In both modes, a reset pin sets the chip to a known state when the pin is pulled low. The RESETn pin must be low for at least 100ns after the CVDD has become stable (between +2.4V and +2.75V) or until the oscillator used is stable or whichever takes longer in order to reset the chip to a known state. 2.7.1 Serial Communication Protocol In the serial communication between the microcontroller and the GMZAN2, the microcontroller always acts as an initiator while the GMZAN2 is always the target. The following timing diagram describes the protocol of the serial channel of the GMZAN2 chip. In the read operation, the microcontroller (Initiator) issues an instruction lasting 12 HCLKs. After the last bit of the command is transferred to the GMZAN2, on the 12th clock, the microcontroller must stop driving data before the next rising edge of HCLK at which point the GMZAN2 will start driving data at the 13th rising edge of HCLK. August 2002 -27- C0022-DAT-01D GMZAN2 Data Sheet Figure 10. Timing Diagram of the GMZAN2 Serial Communication HFS t1 t2 HCLK HDATA (Write to GMZAN2) 01234 5 6 7 8 9 10 11 0 1 23 4 5 6 7 8 9 10 11 0 1 2 3 8 9 10 11 Instruction Write Data 0 Write Data 1 Write Data n HDATA (Read from GMZAN2) 0123 4567 8 9 10 11 0123 4 5 6 7 8 9 10 11 0 1 2 8 9 10 11 Instruction Read Data 0 HDATA Turn Around Time (t3) Read Data 1 t4 Read Data n HCLK WRITE Operation HDATA t5 t6 Valid Valid HCLK READ Operation HDATA t7 Valid August 2002 -28- C0022-DAT-01D GMZAN2 Data Sheet Table 15 summarizes the serial channel specification of the GMZAN2. Refer to Figure 10 for the timing parameter definition. Table 15. GMZAN2 Serial Channel Specification Parameter Word Size (Instruction and Data) HCLK low to HFS high (t1) HFS low to HCLK inactive (t2) HDATA Write to Read Turnaround Time (t3) HCLK cycle (t4) Data in setup time (t5) Data in hold time (t6) Data out valid (t7) min. --100 ns 100 ns 1 HCLK cycle 100 ns 25 ns 25 ns 5 ns 10 1 HCLK cycle typ. 12 bits max. --- 2.7.2 Four bit Parallel Host interface When the chip is configured for a 4-bit host interface, MFB[9:7] are used as HDATA[3:1] and HDATA is used as HDATA0. The command and address information are transferred as Address3:0 and Address7:4, and Command1:0 + Address9:8. The data information is transferred as Data3:0, Data7:4, Data11:8. The following diagrams illustrate the four-bit parallel read and write protocol. This is also referred to as the 6-wire mode. August 2002 -29- C0022-DAT-01D GMZAN2 Data Sheet Figure 11. Timing diagram for read/write using 4-bit Parallel Host Interface Reading from GMZAN2 GMZAN2 RECEIVE GMZAN2 RECEIVE GMZAN2 RECEIVE GMZAN2 TRANSMIT GMZAN2 TRANSMIT GMZAN2 TRANSMIT STOP START HFS HCLK HDATA[0] HDATA[1] REGISTER ADDRESS [0] REGISTER ADDRESS [1] REGISTER ADDRESS [2] REGISTER ADDRESS [3] REGISTER ADDRESS [4] REGISTER ADDRESS [5] REGISTER ADDRESS [6] REGISTER ADDRESS [7] REGISTER ADDRESS [8] REGISTER ADDRESS [9] DATA [0] DATA [4] DATA [8] DATA [1] DATA [5] DATA [9] HDATA[2] COMMAND [0] DATA [2] DATA [6] DATA [10] HDATA[3] COMMAND [1] DATA [3] DATA [7] DATA [11] HOST TRANSMIT HOST TRANSMIT HOST TRANSMIT HOST RECEIVE HOST RECEIVE HOST RECEIVE Host Disables Bus Output Buffers Set Host Bus for Input Before Fourth HCLK Rising Edge Writing to GMZAN2 GMZAN2 RECEIVE GMZAN21 RECEIVE GMZAN2 RECEIVE GMZAN2 RECEIVE GMZAN2 RECEIVE GMZAN2 RECEIVE STOP START HFS HCLK HDATA[0] HDATA[1] REGISTER ADDRESS [0] REGISTER ADDRESS [1] REGISTER ADDRESS [2] REGISTER ADDRESS [3] REGISTER ADDRESS [4] REGISTER ADDRESS [5] REGISTER ADDRESS [6] REGISTER ADDRESS [7] REGISTER ADDRESS [8] REGISTER ADDRESS [9] DATA [0] DATA [4] DATA [8] DATA [1] DATA [5] DATA [9] HDATA[2] HDATA[3] COMMAND [0] DATA [2] DATA [6] DATA [10] COMMAND [1] DATA [3] DATA [7] DATA [11] HOST TRANSMIT HOST TRANSMIT HOST TRANSMIT HOST TRANSMIT HOST TRANSMIT HOST TRANSMIT August 2002 -30- C0022-DAT-01D GMZAN2 Data Sheet 2.7.3 Multi-Function Bus (MFB) The Multi-Function Bus provides 12 additional pins that are used as general purpose input and output (GPIO) pins. Each pin can be independently configured as input or output. MFB pins 9 through 5 have special functions: * When a 10K ohm, pull-down resistor is connected to MFB6 (MFB6 has an internal pull-up resistor) MFB9:7 are used as host data bits HDATA3:1. * When a 10K ohm, pull-down resistor is connected to MFB5 (MFB5 has an internal pull-up resistor) a crystal can be placed between XTAL and TCLK instead of using an external oscillator for the TCLK input. Note that all pins on the multi-function bus MFB11:0 are internally pulled-up. 2.8 On-Screen Display Control The GMZAN2 chip has a built-in OSD (On-Screen Display) controller with an integrated font ROM. The chip also supports an external OSD controller for monitor vendors to maintain a familiar user interface. The internal and external OSD windows may be displayed anywhere the panel Display Enable is active, regardless of whether the panel would otherwise display panel background color or active data. 2.8.1 OSD Color Map Both the internal and external OSD display use a 16-location SRAM block for the color programming. Each color location is a twelve-bit value that defines the upper four bits of each of the 8 bit Red, Blue and Green color components as follows: * * * D3:0 Blue; D7:4 of blue component of color D7:4 Green; D7:4 of green component of color D11:8 Red; D7:4 of red component of color To extend the 4-bit color value programmed to the full 8 bits, the following rule is applied: if any of the upper four color bits is a "1", then R (G, B) data 3:0 = 1111b; otherwise R (G, B) data 3:0 = 0000b. 2.8.2 On-Chip OSD Controller The internal OSD uses a block of SRAM of 1536x12 bits and a ROM of 1024x12 bits. The SRAM is used for both the font data and the character-codes while the ROM is used to store the bit data for 56 commonly used characters. The font data is for 12 pixel x 18 line characters, one bit per pixel. The font data starts at address zero. The character-codes start at any offset (with an address resolution of 16) that is greater than the last location at which font data has been written. It is the programmer's responsibility to ensure that there is no overlap between fonts and character-codes. This implementation results in a trade-off between the number of unique fonts August 2002 -31C0022-DAT-01D GMZAN2 Data Sheet on-screen at any one time and the total number of characters displayed. For example, one configuration would be 98 font maps (56 fonts in ROM and 42 fonts in SRAM) and 768 characters (e.g. in a 24x32 array). The on-chip OSD of the GMZAN2 can support a portrait mode (in which the LCD monitor screen is rotated 90 degrees). In this portrait mode, all the fonts must be loaded in the SRAM, because the ROM stores fonts for a landscape mode (typical orientation) only. The font size in the portrait mode is 12 pixels by 12 lines. As is the case in landscape mode, the SRAM is divided into a font storage area and a character code storage area. For example, 64 fonts can be stored in RAM and an OSD window of 768 characters (such as 24 x 32) can still be displayed. The first address of SRAM to be read for the first character displayed (upper left corner of window) is also programmable, with an address resolution of 16 (8-bits as the top bits of the 12bit SRAM address). The character-code is a 12-bit value used as follows: * * * * D6:0 D8:7 D10:9 D11 font-map select, this is the top seven bits of the address for the first line of font bits Background color, 00=bcolor0, 01=bcolor1, 10=bcolor2, 11=transparent background Foreground color (0, 1, 2 or 3) Blink enable if set to 1, otherwise no blink Although the OSD color map has room for sixteen colors, only seven are used by the internal OSD: three background colors and four foreground colors. The blink rate is based on either a 32 or 64 frame cycle and the duty cycle may be selected as 25/75 50/50% or 75/25%. The 2-bit foreground and background attributes directly select the color (there is no indirect "look-up", i.e. there is no TMASK function). The 2560 addresses of the ROM/SRAM are mapped as 10 segments of 256 contiguous addresses each, to the OSD memory page of 100h - 1FFh in the host interface. A 4-bit register value selects the segment to map to the host R/W page. The character cell height and width are programmable from 5-66 pixels or 2-65 lines. The X/Y offset of the font bit-map upper-left pixel relative to the upper-left pixel of the character cell is also programmable from 0-63 (pixels or lines). The OSD window height and width in characters/rows is programmable from 1-64. The Start X/Y position for the upper left corner of the OSD window is programmable (in panel pixels and lines) from 0- 2047. There is an optional window border (equal width on all four sides of the window) or a window shadow (the window bottom and right side) the border is a solid color that is selected by an SRAM location as RGB444. The border width may be set as 1, 2, 4 or 8 pixels/lines. These parameters are summarized in Figure 12 and Table 16. The Font Data D11:0 for each line is displayed with bit D11 first (leftmost) and D0 last. The reference point for the OSD start is always the upper left corner of the Panel display, which is the start (leading edge) of Panel Display Enable for both Horizontal and Vertical timing. The OSD Window start position sets the location of the first pixel of the OSD to display, including any border. That is, if the border is enabled, the start of the character display of the OSD is offset from the OSD start position by the width/height of the border. August 2002 -32C0022-DAT-01D GMZAN2 Data Sheet To improve the appearance and make it easy to find the OSD window on the screen, the user may select optional shadowing (3D effect). The "Shadow" feature operates in the same manner as in the gmZAN1; that is, it produces a region of half intensity (scaler data) pixels of the same width and height as the OSD window, but offset to the right and down by 8 pixels/lines (the border width setting has no effect). OSD foreground and background colors always cover the OSD window region of the "shadow", but transparent background pixels in the OSD will show the half intensity panel data. Therefore, it is not recommended to use both the "shadow" feature and transparent background OSD pixels together. The "shadow" does not change the intensity of any panel background color over which it may be located. The border and shadow are mutually exclusive, only one may be selected at a time. The OSD window is not affected by the scaling operation. The size will stay the same whether the source input data is scaled or not. Figure 12. On-Chip OSD Window Location OSD_HSTART: Starting pixel number 0-2047 OSD_VSTART Font Y offset OSD_HSTAR T Font X offset OSD_VSTART: Starting line number 0-2047 Font cell width Font cell height Font X offset: Location of left pixel of font inside cell 0-63 Font Y offset: Location of top line of font inside cell 0-63 OSD_HEIGHT ABC 18 12 Font Cell Width: Cell width in pixels 5-66 Font Cell Height: Cell height in lines 2-65 OSD_Width: OSD Window Width in char cells 1-64 OSD_Height: OSD Window Height in char cells 1-64 DEF OSD_WIDTH OSD_Width x OSD_Height <= 32 (1x32, 2x16, 3x10, 4x8, 5x5, 6x5, etc.) Shadows (8 lines down, 8 pixels out) Font size = 12 pixels x 18 scanlines August 2002 -33- C0022-DAT-01D GMZAN2 Data Sheet Table 16. Programmability of On-chip OSD Locations Parameter OSD Window Horizontal Start Position OSD Window Vertical Start Position Font X Offset Font Y Offset Font Cell Width Font Cell Height OSD Window Width OSD Window Height OSD Window Width x OSD Window Height Font Size Range 0 ~ 2047 pixels 0 ~ 2047 scanlines 0 ~ 63 pixels 0 ~ 63 scanlines 5 ~ 66 pixels 2 ~ 65 lines 1 ~ 64 characters 1 ~ 64 characters 0 ~ 32 character locations (rectangle or square) 12 pixels wide x 16 scanlines high Reference Point End-of-line pulse (internal signal) End-of-frame pulse (internal signal) Upper-left corner of a screen location Upper-left corner of a screen location There is no hardware cursor supported. Character blinking can be done by changing the foreground and background colors in the character attribute table. On-chip OSD as well as external OSD is controlled through the API calls. The external OSD is explained in section 2.8.4. 2.8.3 Built-in OSD Fonts To minimize external memory requirements, the GMZAN2 has a set of commonly used characters stored on an on-chip ROM. The ROM contains bit data for the fonts shown in Figure 13. These are the set of alphanumeric characters minus the upper and lower case Q, W and Y. August 2002 -34- C0022-DAT-01D GMZAN2 Data Sheet Figure 13. Built-in OSD Fonts Index Font Index Font Index Font Index Font 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F * N/A N/A N/A N/A N/A N/A N/A * Last two lines overlap into SRAM and must be cleared to use this character. 2.8.4 External OSD Support The GMZAN2 supports an external OSD controller for monitor vendors who wish to maintain a specific user interface, or the look and feel consistent with some previous device. Only those OSD controllers that are developed for a flat-panel monitor application and have a pixel-clock input pin are supported. As is the case with an on-chip OSD, the OSD window size is not affected by scaling. An external OSD controller is connected to the GMZAN2 chip as shown in Table 17. August 2002 -35- C0022-DAT-01D GMZAN2 Data Sheet Table 17. Pin Connection Between the GMZAN2 and an External OSD controller GMZAN2 Pin Name (Pin#, in/out) OSD-HREF (#115, output) OSD-VREF (#116, output) OSD-CLK (#117, output) OSD-FSW (#122, input) External OSD Controller Pin (in/out) HSync (input) VSync (input) Pixel Clock (input) OSD Window Indicator (output) Programmable Horizontal: M OSD-CLK cycles after the HREF for N pixels. Vertical: M' HREF pulses after the VREF for N' lines (M, N, M',N' programmed to external OSD chip) Programmable Programmable Active during horizontal blanking period. Active during vertical blanking period. Polarity Position The four-bit data from an external OSD controller becomes one of the 16 entries to the OSD look-up table (LUT), which is 12 bits wide (4 bits/color). Figure 14. External OSD Interface Data Latch Timing DCLK (gmZRX1 Internal Clock) OSD-CLK delay OSD-DATA[3:0] (#118~#121, inputs) Intensity, R, G, and B (outputs) OSD-CLK cycle time OSD-CLK (to OSD chip) OSD-FSW (from OSD chip) OSD chip output delay setup hold hold OSD-Data3:0 (from OSD chip) OSD-CLK delay = 3 ns default. Additional 0 ~ 12 ns delay can be added. OSD-FSW/OSD-DATA setup/hold time = 1.5 ns min. OSD-CLK cycle time = 80 MHz max. When the external OSD controller interface is enabled, data from the OSD LUT is displayed on a TFT panel instead of the ADC output whenever the OSD-FSW signal is active. The OSD-CLK output to an external OSD controller chip is derived from the DCLK (destination clock) whose clock frequency is the same as the panel clock in frequency (or twice the panel clock frequency on a two-pixels-per-clock panel). The maximum frequency is 80MHz. Both the OSD Data and OSD-FSW signals are latched by GMZAN2 on the rising edge of the DCLK. To maximize the setup/ hold time for the OSD-Data and OSD-FSW signal, a delay of up to 6 ns can be added to the OSD-CLK. August 2002 -36C0022-DAT-01D GMZAN2 Data Sheet Table 18. External OSD Interface Timing Parameters Parameter OSD-CLK Frequency OSD-FSW/OSD-DATA setup time OSD-FSW/OSD-DATA hold time OSD-CLK delay from DCLK OSD-HREF delay from DCLK OSD-CLK/DCLK ratio 1.5 ns 1.5 ns 0 ~ 5.6 ns, programmable in 800-ps increment 0 ~ 12 ns, programmable in 800-ps increment 1/4x, 1/2x, 1x, programmable minimum typical maximum 80 MHz The external-OSD window position is referenced to the edge of the OSD-HREF and OSD-VREF. The horizontal start position is defined in terms of OSD-CLK pulse counts. The vertical position is defined in terms of OSD-HREF pulse counts. These values must be programmed into an external OSD controller chip. The trailing edge of OSD-HREF and OSD-VREF are always positioned at the beginning of a display period. Thus, the external OSD window position will stay at the same place regardless of input resolution and refresh rate. Enabling and configuring the external OSD interface and writing to the OSD LUT is achieved using API calls. 2.9 On-chip TCLK Oscillator The GMZAN2 on-chip TCLK oscillator circuitry is a custom-designed circuit that supports the use of an external oscillator or an external crystal resonator to generate a reference frequency source for the GMZAN2 device. When used with an external crystal resonator, the oscillator circuit provides a very low jitter and very low harmonic clock to the internal circuitry of the GMZAN2. The on-chip oscillator circuit also minimizes the overdrive of the crystal, which reduces the aging of the crystal. The requirements for the TCLK signal are shown below. Table 19. TCLK Specification Frequency Jitter Rise Time (10% to 90%) Duty Cycle 20 MHz to 50 MHz 250 ps maximum 5 ns 40-60 2.9.1 External Oscillator mode The first mode of operation of the TCLK circuitry is the external oscillator mode. When the GMZAN2 is in reset, the state of the MFB5 (pin 107) is sampled. If the pin is pulled high to Vdd (there is an internal 60K Ohm pull up resistor on this pin) the external oscillator mode is enabled. August 2002 -37C0022-DAT-01D GMZAN2 Data Sheet In this mode the internal oscillator circuit is disabled and the external oscillator signal that is connected to the TCLK (pin 141) is routed to an internal clock buffer as shown in figure 15. Vdd 20 to 50 MHz GMZAN2 Oscillator TCLK pin 141 OSC_OUT TCLK Distribution GND XTAL pin 142 Vdd Internal Oscillator Disable Internal Pull Up Resistor ~ 60 K MFB5 pin 107 Reset State Logic External Oscillator Enable Figure 15. Using an External Oscillator 2.9.2 Internal Oscillator mode The second mode of operation for the TCLK circuitry is the internal oscillator mode. When the GMZAN2 is in reset, the state of the pin MFB5 (pin 107) is sampled. If the pin is pulled low by connecting the pin directly to GND, or by connecting the pin to GND through a pull down resistor, the internal oscillator is enabled. The maximum value of the pull down resistor is 15K Ohm. In this mode, an external crystal resonator is connected between the XTAL (pin 142) and the TCLK (pin 141) with the appropriately sized loading capacitors CL1 and CL2. The sizes of CL1 and CL2 are determined from the crystal manufacturer's specification and by compensating for the parasitic capacitance of the GMZAN2 device and the printed circuit board traces. The loading capacitors are terminated to the Vdda power supply. This connection increases the power supply rejection ratio when compared to terminating the loading capacitors to ground. The oscillator circuit is a Pierce Oscillator circuit and a simplified schematic is shown in Figure 16. The output of the oscillator circuit, measured at the TCLK (pin 141), is an approximate sine wave with a bias of about 2 volts above ground (see Figure 17). The peak-to-peak voltage of the output can range from 250 mV to 1000 mV depending on the specific characteristics of the external crystal used and variation in the oscillator characteristics. The output of the oscillator is connected to a comparator that converts the sine wave to a square wave. The comparator requires a minimum signal level of about 50mV peak-to-peak to function correctly. The output of the comparator is buffered and is then distributed to the GMZAN2 circuits. August 2002 -38- C0022-DAT-01D GMZAN2 Data Sheet GMZAN2 Vdda CL1 TCLK pin 141 Vdda Vdd CL2 XTAL pin 142 Vdd 100 K 180 uA OSC_OUT TCLK Distribution Internal Pull Up Resistor ~ 60K MFB5 pin 107 10 K Reset State Logic Internal Oscillator Enable Figure 16. Using an Internal Oscillator 3.3 Volts ~ 2 Volts 250 mV peak to peak to 1000 mV peak to peak time Figure 17. Internal Oscillator output at TCLK August 2002 -39- C0022-DAT-01D GMZAN2 Data Sheet One of the design parameters that must be given some consideration is the value of the loading capacitors used with the crystal. GMZAN2 Vdda Cex1 Cpcb TCLK pin 141 Cesd Cpin Cpad Cshunt Vdda Internal Oscillator Cex2 Cpcb XTAL pin 142 Cpin Cpad Cesd CL1 = Cex1 + Cpcb + Cpin + Cpad + Cesd CL2 = Cex1 + Cpcb + Cpin + Cpad + Cesd Figure 18. Parasitic Capacitance Sources The loading capacitance (Cload) on the external crystal is the combination of CL1 and CL2 and is calculated by: Cload = ((CL1 * CL2) / (CL1 + CL2)) + Cshunt. The shunt capacitance Cshunt is the effective capacitance between the XTAL and TCLK pins. For the GMZAN2 this is approximately 9 pF. CL1 and CL2 are a parallel combination of the external loading capacitors (Cex), the PCB board capacitance (CPCB), the pin capacitance (Cpin), the pad capacitance (Cpad), and the ESD protection capacitance (CESD). The capacitances are symmetrical so that CL1 = CL2 = Cex + CPCB + Cpin + Cpad + CESD The correct value of Cex must be calculated given the value of the parasitics. CPCB ~ Layout dependent. Approximately 2 pF to 10 pF Cpin ~ 1.1 pF Cpad ~ 1 pF CESD ~ 5.3 pF Cshunt ~ 9 pF August 2002 -40- C0022-DAT-01D GMZAN2 Data Sheet Some attention must be given to the details of the oscillator circuit when used with an external crystal resonator. The value of Cload that is specified by the manufacturer should not be exceeded because of potential start up problems with the oscillator. Additionally, the external crystal used should be a parallel resonate cut and the value of the equivalent series resistance must be less than 90 Ohms. 2.10 Sleep Mode Power Down Recent energy efficiency requirements, based on various standards, specify a low power standby mode when the monitor is not in use. To support these standards, the GMZAN2 incorporates control bits that provides selective disabling of the core modules in the GMZAN2 This is under firmware control. The selective enabling and disabling of the various cores give the firmware designer the flexibility to adjust the power consumption of the GMZAN2 device based on the task required. Power consumption in a CMOS device is the sum of the leakage currents plus switching currents of the logic. If all the logic switching is stopped, the current consumption of the GMZAN2 is reduced to a few milli-amperes which is being used for the analog inputs. The philosophy for the GMZAN2 sleep mode programming is to turn off all possible sources of switching logic when no video signal is present. The GMZAN2 is configured for sleep mode operation by a register programming sequence that disables the SCLK, DCLK PLL's, turning off the ADC, the panel drivers and establishing other conditions to minimize the power consumption of the GMZAN2. The register programming sequence is to disable the high frequency clocks and places the remaining logic into a state that minimizes any logic switching. In this condition, only the TCLK is running with the Source Timing Measurement (STM) logic active (Registers 0x60 to 0x7F), and the GMZAN2 can be polled for input signal activity to determine when to exit the standby mode. For more detailed information on this programming sequence please refer to Appendix A of the GMZAN2 Register Programming Guide. Sleep Mode Current Specification: Register programming as specified in the Appendix A of the GMZAN2 Register Programming Guide. TCLK Frequency 50 MHz 14.3 MHz 0 MHz Sleep Mode Current < 40 mA < 10 mA < 5 mA August 2002 -41- C0022-DAT-01D GMZAN2 Data Sheet 3. ELECTRICAL CHARACTERISTICS Table 20. Absolute Ratings Parameter Min. Typ. Max. 3.6 volts Note RVDD1, RVDD2, RVDD2A, RVDD2B, RVDD3, RVDD3A, -0.3 DAC_DVDDA, PLL_DVVDA, PLL_SVDDA, DAC_SVDDA, PLL_RVDDA, ADC_RVDDA, ADC_GVDDA, ADC_BVDDA, ADC_VDDA SRVDD1, SRVDD2, CVDD2, DVDD, SVDD, SYN_VDD, -0.25 ADC_VDD1, ADC_VDD2 Vin Operating temperature Maximum power consumption at XGA 75Hz output resolution Maximum power consumption at XGA 85Hz output resolution Vss - 0.5volt 0 degreeC 2.75 volts Vcc + 0.5V 70 degreeC 1.28 watts 1.35 watts (4) (4) Table 21. DC Electrical Characteristic Parameter Min. Typ. 3.3 volts Max. 3.6 volts Note RVDD1, RVDD2, RVDD2A, RVDD2B, RVDD3, 3.0 volts RVDD3A, DAC_DVDDA, PLL_DVVDA, PLL_SVDDA, DAC_SVDDA, PLL_RVDDA, ADC_RVDDA, ADC_GVDDA, ADC_BVDDA, ADC_VDDA SRVDD1, SRVDD2, CVDD2, DVDD, SYN_VDD, ADC_VDD1, ADC_VDD2 Vil (TTL inputs) Vih (TTL inputs) Voh Vol Input Current 3.3 volt operating supply current 2.5 volt operating supply current NOTE 1: 5V-Tolerent TTL Input pads are as follows: SVDD, 2.25 volts GND 2.0 volts 2.4 volts GND -10 uA 0 mA 0 mA 2.5 volts 2.75 volts 0.8 volts 2.5 volts 2.5 volts 0.4 volts 10 uA 20 mA/pad @ 10pF (2) (3) (1) 400mA * * * * CRT Interface: HSYNC (pin #150),VSYNC (#148) Host Interface: HFS (#98), HCLK (#103), HDATA (#99), RESETN (#100), MFB[11:0]: MFB11 (#123), MFB10 (#124), MFB9 (#102), MFB8 (#104), MFB7 (#105), MFB6 (#106), MFB5(#107),MFB4 (#109), MFB3 (#110), MFB2 (#111), MFB1 (#112), MFB0 (#113) OSD Interface: OSD_DATA3 (#121), OSD_DATA2 (#120), OSD_DATA1 (#119), OSD_DATA0 (#118), OSD_FSW (#122) Non-5V-Tolerant TTL Input Pad is: TCLK (#141) NOTE 2: When the panel interface is disabled, the supply current is 0 mA. The drive current of each pad can be programmed in the range of 2 mA to 20 mA (@capacitive loading = 10 pF). NOTE 3: When all circuits are powered down and TCLK is stopped, the CVDD supply current becomes 0mA. NOTE 4: This depends on the refresh rate supported by the LCD panel chosen. August 2002 -42- C0022-DAT-01D GMZAN2 Data Sheet 4. ORDERING INFORMATION Order Code GMZAN2 Package 160-pin PQFP Temperature Rating Commercial 0C to 70C August 2002 -43- C0022-DAT-01D GMZAN2 Data Sheet 5. MECHANICAL DIMENSIONS Figure 19. 160 pin PQFP Package Dimensions A B 121 80 Symbol Millimeter Inch Min A B C D E 30.95 27.90 Nom 31.20 28.00 0.65 Max 31.45 28.10 4.25 Min Nom Max 1.218 1.228 1.238 1.098 1.102 1.106 0.026 0.167 0.063 0.125 0.131 0.137 0.025 0.031 0.037 0.002 0.010 0.020 0 7 0.008 0.012 0.016 0.004 0.006 0.008 1.60 3.17 0.65 0.05 0 0.20 0.10 0.30 0.15 3.32 0.80 0.25 3.47 0.95 0.50 7 0.40 0.20 GMZAN2 G H I 160 C pin 1 40 J L M Depressed dot on package indicates pin 1 (lower left corner) D E G I L M H J August 2002 -44- C0022-DAT-01D |
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