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ISL54056
Data Sheet October 30, 2006 FN6357.1
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
The Intersil ISL54056 device is a low ON-resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1.65V to +4.5V supply. Targeted applications include battery powered equipment that benefit from low RON (0.39) and fast switching speeds (tON = 30ns, tOFF = 16ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. With a supply voltage of 4.2V and logic high voltage of 2.85V at both logic inputs, the part draws only 12A max of ICC current. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL54056 is offered in small form factor package, alleviating board space limitations. The ISL54056 consists of four SPDT switches. It is configured as a dual double-pole/double-throw (DPDT) device with two logic control inputs that control two SPDT switches each. The configuration can be used as a dual differential 2-to-1 multiplexer/demultiplexer. The ISL54056 is pin compatible with the NLAS3799 and NLAS3799L.
TABLE 1. FEATURES AT A GLANCE ISL54056 Number of Switches SW 4.3V RON 4.3V tON/tOFF 3.0V RON 3.0V tON/tOFF 1.8V RON 1.8V tON/tOFF Package 4 Quad SPDT (Dual DPDT) 0.39 30ns/16ns 0.45 34ns/18ns 0.65 48ns/23ns 16 Ld 2.6x1.8x0.5mm TQFN
Features
* Pb-Free Plus Anneal Available (RoHS Compliant) * Pin Compatible Replacement for the NLAS3799 and NLAS3799L * ON Resistance (RON) - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39 - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65 * RON Matching between Channels . . . . . . . . . . . . . . . . 0.05 * RON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05 * Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . <0.68W * Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns * Break-Before-Make * 1.8V Logic Compatible (+3V supply) * Low ICC Current when VinH is not at the V+ Rail * Available in 16 Ld 2.6x1.8x0.5mm TQFN * ESD HBM Rating - COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV - All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54056 Pinouts
(Note 1) ISL54056 (TQFN) TOP VIEW
COM4 IN3-4 NO4 NC3
Truth Table
LOGIC 0 1 NOTE:
COM3 NO3 8
NC SW ON OFF
NO SW OFF ON
12
11
10
13
NC4 V+ NO1 COM1
9
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
Pin Descriptions
PIN FUNCTION System Power Supply Input (+1.65V to +4.5V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin V+ GND IN COM NO
14
7 6 1 2 3 IN1-2 NO2 NC1 COM2 4 5
15
GND NC2
NOTE: 1. Switches Shown for Logic "0" Input.
16
NC
Ordering Information
PART NUMBER ISL54056IRUZ-T (Note) PART MARKING GAA TEMP. RANGE (C) -40 to 85 PACKAGE PKG. DWG. # 16 Ld Thin QFN Tape and Reel (Pb-free) L16.2.6x1.8A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating: HBM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV HBM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>6kV MM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>700V MM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>300V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) TQFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C (Lead Tips Only)
Operating Conditions
Temperature Range ISL54056IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4), unless otherwise specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+ (See Figure 5) V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at max RON (Note 7) V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+ (Note 6) V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V 25 Full
0 0.4 0.45 0.05 0.06 0.05 0.05 -70 -165 -70 -165
V+
V
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
70 165 70 165
nA nA nA nA
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 6) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25 Full 25 Full Full 25 25 25 25
33 38 16 21 3 248 65 -85 0.008
ns ns ns ns ns pC dB dB %
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion
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ISL54056
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4), unless otherwise specified (Continued) TEST CONDITIONS TEMP (C) 25 25 (NOTE 5) MIN TYP 38 102 (NOTE 5) MAX UNITS pF pF
PARAMETER
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = +4.5V, VIN = 0V or V+ Full 25 Full Positive Supply Current, I+ V+ = +4.2V, VIN = 2.85V 25 1.65 4.5 0.15 1.4 12 V A A A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 7. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4. V+ = 4.5V, VIN = 0V or V+ Full Full Full 1.6 -0.5 0.5 0.5 V V A
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), unless otherwise specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+ (See Figure 5) V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max RON (Note 7) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+ (Note 6) V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating 25 Full
0 0.45
V+ 0.55 0.65 0.05 0.12 0.15 0.07 0.15 0.15 1.1 30 1.5 45
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1) V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3)
25 Full 25 Full Full
34 39 18 23 3
ns ns ns ns ns
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD
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ISL54056
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), unless otherwise specified (Continued) TEST CONDITIONS CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 6) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 TEMP (C) 25 25 25 25 25 25 (NOTE 5) MIN TYP 126 65 -85 0.012 38 102 (NOTE 5) MAX UNITS pC dB dB % pF pF
PARAMETER Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full Full Full 1.4 -0.5 0.5 0.5 V V A 0.021 0.72 A A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4), unless otherwise specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+ (See Figure 5) 25 Full
0 0.65
V+ 0.8 0.85
V
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 2.0V, VNO or VNC = 1.0V, RL = 50, CL = 35pF (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) 25 Full 25 Full Full 25 50 55 25 30 8 48 ns ns ns ns ns pC
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ Full Full Full 1.0 -0.5 0.5 0.4 V V A
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ISL54056 Test Circuits and Waveforms
V+ LOGIC INPUT 50% 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON VOUT 90% LOGIC INPUT SWITCH INPUT NO or NC COM IN GND RL 50 CL 35pF VOUT V+ C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT ON
VOUT
RG
NO or NC
COM
VOUT
V+ LOGIC INPUT ON OFF 0V
VG
GND
IN
CL LOGIC INPUT
Q = VOUT x CL
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+
C
V+ LOGIC INPUT 0V VNX
NO
COM
NC
VOUT RL 50 CL 35pF
IN SWITCH OUTPUT VOUT 90% 0V tD LOGIC INPUT GND
CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST CIRCUIT
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ISL54056 Test Circuits and Waveforms (Continued)
V+ C SIGNAL GENERATOR RON = V1/100mA
NO or NC NO or NC
V+ C
VNX IN 0V or V+ 100mA V1 IN 0V or V+
ANALYZER RL
COM
COM
GND
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+ C V+ C SIGNAL GENERATOR
NO or NC COM
50
NO or NC
IN1 0V or V+ IMPEDANCE ANALYZER
COM NC or NO COM
IN
0V or V+
ANALYZER RL
GND
N.C.
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54056 is a bidirectional, quad single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.65V to 4.5V supply with low on-resistance (0.39) and high speed operation (tON = 30ns, tOFF = 16ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65V), low power consumption (6.3W max), low leakage currents (165nA max), and the tiny TQFN package. The ultra low on-resistance and Ron flatness provide very low insertion loss and distortion to applications that require signal reproduction.
Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see 7
FN6357.1 October 30, 2006
ISL54056
This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch. Connecting schottky diodes to the signal pins as shown in Figure 8 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current. the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL54056 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 2.85V logic (0V to 2.85V) while operating with a 4.2V supply the device draws only 12A of current (see Figure 16 for VIN = 2.85V).
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR
High-Frequency Performance
In 50 systems, the ISL54056 has a -3dB bandwidth of 104MHz (see Figure 21). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels.
VCOM
INX VNX
GND OPTIONAL SCHOTTKY DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54056 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL54056 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and "Typical Performance" curves for details. V+ and GND also power the internal logic and level shiftiers. The level shiftiers convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 22 details the high Off Isolation and Crosstalk rejection provided by this part. At 100kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 3.0V to 4.5V (see Figure 14). At 3.0V the VIL level is about 0.53V. This is still above the 1.8V CMOS guaranteed low output maximum level of 0.5V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving
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ISL54056 Typical Performance Curves TA = +25C, unless otherwise specified
0.4 ICOM = 100mA 0.39 0.38 0.43 0.37 RON () RON () 0.36 0.35 V+ = 3.9V 0.34 0.38 0.33 0.32 0 1 2 VCOM (V) V+ = 4.3V 0.37 V+ = 4.5V 3 4 5 0.36 0 0.5 1 1.5 2 VCOM (V) 2.5 3 3.5 V+ = 3.3V 0.42 0.41 0.4 0.39 V+ = 3V V+ = 2.7V 0.46 0.45 0.44 ICOM = 100mA
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.8 ICOM = 100mA V+ = 1.65V 0.7 V+ = 1.8V RON ()
FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.45 V+ = 4.3V ICOM = 100mA 0.4 +85C RON () 0.35 +25C
0.6 V+ = 2V 0.5
0.3 -40C
0.4 0 0.5 1 VCOM (V) 1.5 2
0.25 0 1 2 VCOM (V) 3 4 5
FIGURE 11. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.5 V+ = 3.3V ICOM = 100mA
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
0.55 V+ = 2.7V ICOM = 100mA 0.5
0.45 +85C +85C RON () 0.4 +25C 0.35 0.35 -40C RON () 0.45 +25C 0.4 -40C
0.3 0 0.5 1 1.5 2 2.5 3 3.5 VCOM (V)
0.3 0 0.5 1 1.5 VCOM (V) 2 2.5 3
FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE
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FN6357.1 October 30, 2006
ISL54056 Typical Performance Curves TA = +25C, unless otherwise specified (Continued)
0.7 +85C 0.65 0.6 0.55 0.5 0.45 0.4 0 0.35 0 0.5 1 VCOM (V) 1.5 2 1 2 3 VIN1&2 (V) 4 5 50 +25C -40C iON (A) V+ = 1.8V ICOM = 100mA 150 200 V+ = 4.2V Sweeping Both Logic Inputs
RON ()
100
FIGURE 15. ON RESISTANCE vs SWITCH VOLTAGE
250 200 150 VINH AND VINL (V)
FIGURE 16. SUPPLY CURRENT vs VLOGIC VOLTAGE
1 0.9 0.8 VINH 0.7 0.6 VINL 0.5 0.4
Q (pC)
100 50 V+ = 4.3V 0 V+ = 1.8V -50 -100 0 1 2 VCOM (V) 3 4 5 V+ = 3V
0.3 0.2 1.5
2
2.5
3 V+ (V)
3.5
4
4.5
FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE
250
FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
40
200
35
30 tON (ns) tOFF (ns) 150
25 +85C 20 +25C -40C
100
50
+85C -40C
+25C 15
0 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5
10 1 1.5 2 2.5 V+ (V) 3 3.5 4 4.5
FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE
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ISL54056 Typical Performance Curves TA = +25C, unless otherwise specified (Continued)
NORMALIZED GAIN (dB) -10 V+ = 3V 0 -20 CROSSTALK (dB) GAIN V+ = 4.3V -20 -30 -40 0 20 40 60 80 RL = 50 VIN = 0.2VP-P to 2VP-P 1M 10M 100M FREQUENCY (Hz) PHASE () -50 ISOLATION -60 -70 -80 CROSSTALK -90 -100 -110 1k 90 100 110 100M 500M 60 70 80 20 30 OFF ISOLATION (dB) 40 50 10
PHASE
100 600M
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 21. FREQUENCY RESPONSE
FIGURE 22. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 228 PROCESS: Si Gate CMOS
11
FN6357.1 October 30, 2006
ISL54056 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS
6 INDEX AREA 2X 2X 0.10 C
N
E
SYMBOL A
MIN 0.45 -
NOMINAL 0.50 0.127 REF
MAX 0.55 0.05
NOTES -
12 0.10 C
A1 A3
TOP VIEW
b D
0.15 2.55 1.75
0.20 2.60 1.80 0.40 BSC
0.25 2.65 1.85
5 -
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW A
C
E e L L1 N Nd
0.35 0.45
0.40 0.50 16 4 4
0.45 0.55
2 3 3
e PIN #1 ID 12 L1 NX L NX b 5 16X 0.10 M C A B 0.05 M C BOTTOM VIEW
Ne NOTES: 0
-
12
4 Rev. 4 8/06
(DATUM B) (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
3.00 1.80 1.40 1.40
2.20
0.90 0.40 0.20 0.50 0.40 10 LAND PATTERN 0.20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6357.1 October 30, 2006

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