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19-3818; Rev 0; 9/05
622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications
General Description
The MAX3634 burst-mode clock phase aligner (CPA) is designed specifically for 622Mbps or 1244Mbps GPON (ITU G.984) optical line terminal (OLT) receiver applications. The MAX3634 provides clock and clock-aligned resynchronized upstream data through differential LVPECL outputs. Using the OLT system clock as a reference, the MAX3634 aligns to the input data and acquires within the first 13 bits of the burst. The CPA operates with received data that is frequency locked to the OLT reference. The acquisition time, bit-error ratio, and jitter tolerance all support GPON PMD specifications. LVPECL high-speed clock and data outputs provide compatibility with FPGAs at 622Mbps and with the MAX3885 deserializer at 1244Mbps. The MAX3634 is available in a low-profile, 7mm x 7mm, 48-lead TQFN package. The MAX3634 operates from a single +3.3V supply, over the -40C to +85C temperature range.
Features
DC-Coupled Clock Phase Aligner for Burst-Mode GPON Applications 13-Bit Burst Acquisition Time 0.85UI High-Frequency Jitter Tolerance Continuous Clock Output Byte Rate (1/8th Data Rate) Reference Clock Input Lock Detect Output LVPECL Serial Data Input and Output LVPECL Reset Input
MAX3634
Ordering Information
PART TEMP RANGE -40C to +85C PINPACKAGE 48 TQFN (7mm x 7mm) PKG CODE T4877-6
Applications
622Mbps GPON OLT Receivers 1244Mbps GPON OLT Receivers
MAX3634ETM
Pin Configuration appears at end of data sheet.
Typical Application Circuit
BURST RESET
BURST ENABLE
DATA
4
DATA CLOCK
MAX3634
CLOCK BURST-MODE CLOCK PHASE ALIGNER
BURST-MODE TIA/LA
UPSTREAM 1244Mbps
MAX3656
BURST-MODE LASER DRIVER
MAX3892
DATA SERIALIZER
DIVIDE BY 16 DIVIDE BY 8 OLT CLOCK DATA RATESEL
MAX3738
CONTINUOUS LASER DRIVER DOWNSTREAM 2488Mbps
MAX3864 MAX3748A
TIA/LA
MAX3872
SONET CDR
CLOCK DATA
GPON OPTICAL LINE TERMINATION
GPON OPTICAL NETWORK TERMINATION
________________________________________________________________ Maxim Integrated Products
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622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications MAX3634
ABSOLUTE MAXIMUM RATINGS
VCC, VCCI, VCCO, VCCV ........................................-0.5V to +4.0V SDI, RST, REFCLK, RATESEL, FILT, TEST.............................-0.5V to (VCC + 0.5V) LVPECL Output Current (SDO, SCLK, LOCK).............50mA Continuous Power Dissipation (TA = +85C) 48-Lead TQFN package (derate 27.8mW/C above +85C) .............................1800mW Storage Temperature Range .............................-55C to +150C Operating Ambient Temperature Range .............-40C to +85C Lead Temperature (soldering, 10s) .................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER Supply Current Data Rate Reference Clock Input Frequency SDI, RST, REFCLK Differential Input SDI, RST, REFCLK Input Current RST Input Rise/Fall Times SDI, RST, REFCLK CommonMode Input TA = 0C to +85C (Note 1) VOL TA = -40C to 0C (Note 1) TA = 0C to +85C (Note 1) VOH TA = -40C to 0C (Note 1) Jitter Tolerance Acquisition Time Bit-Error Ratio SDO, LOCK Transition Time SCLK Transition Time tr, tf tr, tf 622Mbps (Notes 2, 5, 6) 1244Mbps (Notes 2, 5, 6) (Notes 2, 3) After acquisition (Notes 2, 4) 20% to 80% (Note 1) 20% to 80% (Note 1) tr, tf Rate = 1244Mbps Rate = 622Mbps VCC - 1.49 VCC - 1.81 VCC - 1.83 VCC - 1.025 VCC - 1.085 0.73 0.73 0.83 0.81 13 10-10 265 200 ps ps VIN SYMBOL ICC CONDITIONS Not including LVPECL output current RATESEL = low RATESEL = high RATESEL = low RATESEL = high 200 -180 MIN TYP 315 1244.16 622.08 155.52 77.76 1600 +180 200 200 VCC - VIN/4 VCC - 1.62 V VCC - 1.555 VCC - 0.88 V VCC - 0.88 UIP-P Bits MAX 390 UNITS mA Mbps MHz mVP-P A ps V
SDO, SCLK, LOCK Output Voltage Low
SDO, SCLK, LOCK Output Voltage High
2
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622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER Serial Data Output Clock-to-Q Delay (Figure 1) Serial Data Output Q-to-Clock Delay (Figure 1) RATESEL Input High RATESEL Input Low RATESEL Input Current SYMBOL tCLK-Q tQ-CLK VIH VIL VIN = 0V or VCC -100 CONDITIONS 622Mbps (Notes 1, 2) 1244Mbps (Notes 1, 2) 622Mbps (Notes 1, 2) 1244Mbps (Notes 1, 2) MIN 500 250 500 250 2 0.8 +100 TYP MAX UNITS ps ps V V A
MAX3634
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
PECL output must have external termination of 50 to VCC - 2V (Thevenin equivalent). AC parameters are guaranteed by design and characterization. From start of PON burst, 101010101010 preamble sequence. BER, acquisition time requirements are met with 100mVP-P sinusoidal noise on VCC, 0 < fNOISE 10MHz. Measured with 20psRMS input random jitter (1.244Mbps), 30psRMS (622Mbps) Jitter tolerance refers to the variation in phase between REFCLK and SDI after acquisition.
(SCLK+) - (SCLK-)
(SDO+) - (SDO-) tCLK-Q tQ-CLK
Figure 1. Definition of Clock-to-Q and Q-to-Clock Delay
Typical Operating Characteristics
(VCC = +3.3V and TA = +25C, unless otherwise noted)
1.244Gbps INPUT AND OUTPUT EYE DIAGRAMS
MAX3634 toc01
622Mbps INPUT AND OUTPUT EYE DIAGRAMS
MAX3634 toc02
BURST CAPTURE AT 1.244Gbps
RST
MAX3634 toc03
SDI
SDI
SDI
LOCK SDO SDO SDO
200ps/div
400ps/div
1ns/div
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622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications MAX3634
Typical Operating Characteristics (continued)
(VCC = +3.3V and TA = +25C, unless otherwise noted)
JITTER TOLERANCE vs. SDI-TO-REFCLK PHASE (1.244Gbps)
MAX3634 toc04
JITTER TOLERANCE vs. SDI-TO-REFCLK PHASE (622Mbps)
MAX3634 toc05
SUPPLY CURRENT vs. TEMPERATURE
MAX3634 toc06
1.0 0.9 JITTER TOLERANCE (UIP-P) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 200 400 600 LIMITED BY TEST EQUIPMENT
1.0 0.9 JITTER TOLERANCE (UIP-P) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 LIMITED BY TEST EQUIPMENT
340 320 SUPPLY CURRENT (mA) 300 280 260 240 220 EXCLUDES PECL OUTPUT CURRENT 200
800
0
200
400
600
800
-50
0
50
100
SDI-TO-REFCLK PHASE (ps)
SDI-TO-REFCLK PHASE (ps)
AMBIENT TEMPERATURE (C)
Pin Description
PIN 1, 2, 12, 25, 36, 37, 48 3, 6, 7, 10 4 5 8 9 11, 38, 39, 44, 47 13-20, 22, 23 21, 24, 26, 29, 32, 35 27 28 30 31 33 34 40 41, 43 42 45 46 EP NAME GND VCCI SDI+ SDIRST+ RSTVCC TEST VCCO LOCKLOCK+ SDOSDO+ SCLKSCLK+ RATESEL VCCV FILT REFCLKREFCLK+ Supply Ground +3.3V Supply for Input Buffers Positive Serial Data Input, LVPECL Negative Serial Data Input, LVPECL Positive Reset Input, LVPECL. Reset (= RST+ - RST-) is falling edge triggered. Negative Reset Input, LVPECL +3.3V Supply for Digital Circuitry Production Test Pins, Reserved. Leave open for normal operation. +3.3V Supply for Output Buffers Negative Lock Status Output, LVPECL Positive Lock Status Output, LVPECL. Lock (= (LOCK+) - (LOCK-)) high indicates that the MAX3634 has acquired the correct phase. Negative Serial Data Output, LVPECL Positive Serial Data Output, LVPECL Negative Serial Clock Output, LVPECL Positive Serial Clock Output, LVPECL Rate Select Input, TTL. High selects 622.08Mbps operation. +3.3V Supply for VCO PLL Filter Capacitor. Connect a 0.1F X7R capacitor from pin 42 to VCCV. Negative Reference Clock Input, LVPECL (1/8th data rate) Positive Reference Clock Input, LVPECL FUNCTION
Exposed Pad The exposed pad must be connected to the ground plane for proper thermal performance.
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622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications
General Description
Theory of Operation
The MAX3634 CPA provides serial clock and data outputs for GPON upstream bursts. The burst-mode CPA operates on the principle that the recovered clock from the ONT CDR is used at each ONT to clock upstream data bursts out of the ONT controller. The burst-mode CPA has logic that determines the correct phase relationship between the upstream data and the OLT reference clock at the beginning of each ONT's burst, and resamples the upstream data at each bit using that clock. The burst-mode CPA contains a phase-locked loop (PLL) that synchronizes its oscillator to the reference clock input. This oscillator drives a phase splitter, which generates eight evenly spaced phases of the serial clock, which are used to sample the input data at 1/8th bit intervals in eight flip-flops. Combinatorial and sequential logic measures the preamble, and based on the phase of the preamble, determines which one of the eight clock phases is at the center of the input data bits. The data from the flip-flop associated with this phase is then steered through a multiplexer to the CPA output, which requires four or five additional clock periods until valid data is output. The CPA serial output clock is continuous, without any phase jumps or discontinuities from burst to burst. The burst-mode CPA requires a preamble sequence of 1010101010101 (13 bits) for correct phase alignment. Typically, output begins after the 12th bit, although for certain data/phase relationships, 13 bits are required. An LVPECL-compatible lock status output is provided, which indicates when the correct phase has been acquired and valid serial output data is available. This output remains low until reset by the burst reset input (RST). The output data is disabled (held low) during the period between reset and lock.
MAX3634
Reference Clock Input
The MAX3634 includes a PLL, which multiplies the reference clock by eight for use in the retiming circuitry. For correct operation, the REFCLK input must be connected to the OLT byte-rate reference clock, which must be equal to 1/8th the serial data rate, and must have a 40% to 60% duty cycle. This must be the same clock source used to time the downstream data, and the upstream data must be frequency locked to this source. The RATESEL input is used to configure 622Mbps or 1244Mbps operation; when RATESEL is high, the MAX3634 operates at 622Mbps.
REFCLK+ REFCLKLVPECL 622Mbps/1244Mbps PLL/PHASE SPLITTER 0 RATESEL TTL 7 D Q SYNCHRONIZER MUX SDI+ SDILVPECL D Q LVPECL
MAX3634
BURST-MODE CPA SDO+ SDO-
SCLK+ LVPECL SCLK-
D
Q
RST+ RSTLVPECL PHASE-ACQUISITION LOGIC LVPECL
LOCK+ LOCK-
Figure 2. Functional Block Diagram _______________________________________________________________________________________ 5
622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications MAX3634
Input Stage
The LVPECL serial data input, SDI, and burst-mode reset input, RST, provide 200mVP-P sensitivity. The RST input rise and fall times (20% to 80%) must not exceed 200ps. LVPECL inputs must be DC-coupled with external termination for correct operation with burst data (see Maxim Application Note HFAN 1.0 for termination configuration). rest (BRST) signal. It then uses the next 8 bits of preamble (10101010) to measure the phase relationship between the reference clock and upstream data (after the internal logic has been reset), and 3 to 5 bits later begins outputting data. The time interval from BRST to the end of the preamble must be no less than 18 bits long. If the 8 bits of preamble that it uses to measure phase have been excessive pulse-width distortion, the phase measurement is in error. The active edge of the reset input (BRST) must arrive at the MAX3634 after the TIA has finished its level recovery, but no sooner than 18 bits prior to the end of the (repeating 10 pattern) preamble, in order to provide adequate time for the MAX3634 to initialize, measure the phase, and load the output pipelines. This timing is shown in Figure 3.
Lock Detect
After the first 12 or 13 bits of the preamble, plus 4 or 5 bits of synchronizer delay, LOCK asserts to indicate the beginning of valid data output.
Applications Information
GPON Burst-Mode Timing
Internally, the MAX3634 requires five internal clock cycles (8x REFCLK) to initialize itself after receiving the
DATA INPUT TO MAX3634
TDSR RESET
TLR
TCR
TDSR: BURST-TO-BURST SEPARATION TIME TLR: TIA/LA LEVEL RECOVERY TIME TCR: CPA RESET AND ACQUISITION TIME, 19 BITS
DATA VALID
GUARD TIME
TIA/LA ACQUISITION
CPA RESET (5 BITS)
CPA ACQUISITION (12 OR 13 BITS)
OUTPUT DATA VALID
Figure 3. Clock Phase Aligner Operation Timing Diagram
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622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications
Pin Configuration
LOCK+ SCLK+ VCCO LOCKSCLKSDO+ VCCO VCCO VCCO SDOGND GND
Chip Information
TRANSISTOR COUNT: 10,805 PROCESS: Silicon Germanium BiCMOS
MAX3634
36 35 34 33 32 31 30 29 28 27 26 25 GND 37 VCC 38 VCC 39 RATESEL 40 VCCV 41 FILT 42 VCCV 43 VCC 44 REFCLK- 45 REFCLK+ 46 VCC 47 GND 48 1 GND 2 GND 3 VCCI 4 SDI+ 5 SDI6 VCCI 7 VCCI 8 RST+ 9 RST10 11 12 GND VCCI VCC EP* 24 VCCO 23 TEST10 22 TEST9 21 VCCO 20 TEST8
MAX3634
19 TEST7 18 TEST6 17 TEST5 16 TEST4 15 TEST3 14 TEST2 13 TEST1
TQFN
*EP MUST BE CONNECTED TO GROUND.
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622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications MAX3634
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
E E/2
DETAIL A
(NE-1) X e
k e D/2
D
(ND-1) X e
C L
D2
D2/2
b L E2/2 DETAIL B e L k
C L
E2
C L
C L
L1
L e e
L
A1
A2
A
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
E
1
2
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
32, 44, 48L QFN.EPS

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