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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9330/D Rev 1, 01/2002
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3.3V/2.5V 1:6 LVCMOS PLL Clock Generator
The MPC9330 is a 3.3V or 2.5V compatible, 1:6 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance telecomm, networking and computing applications. With output frequencies up to 200 MHz and output skews less than 150 ps1 the device meets the needs of the most demanding clock applications. The MPC9330 is specified for the extended temperature range of -40C to +85C. Features * 1:6 PLL based low-voltage clock generator
MPC9330
3.3V/2.5V 1:6 LVCMOS PLL CLOCK GENERATOR
* * * * * * * * * * * * * *
2.5V or 3.3V power supply Generates clock signals up to 200 MHz Maximum output skew of 150 ps1 On-chip crystal oscillator clock reference Alternative LVCMOS PLL reference clock input Internal and external PLL feedback PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4 Supports zero-delay operation in external feedback mode Synchronous output clock stop in logic low eliminates output runt pulses Power_down feature reduces output clock frequency Drives up to 12 clock lines 32 lead LQFP packaging Ambient temperature range -40C to +85C
FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A
Pin and function compatible to the MPC930 Functional Description The MPC9330 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9330 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers (divide-by-2, divide-by-4 and divide-by-6), the internal VCO of the MPC9330 is running at either 4x, 8x, 12x, 16x or 24x of the reference clock frequency. In internal feedback configuration (divide-by-16) the internal VCO is running 16x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible input as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9330 output clock stop control allows the outputs to start and stop synchronously in the logic low state, without the potential generation of runt pulses. The MPC9330 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9330 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package. 1. Design target, pending final characterization.
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This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 2002
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MPC9330
VCC 25k XTAL_IN XTAL_OUT CCLK REF_SEL 25k FB_IN 25k VCC FB_SEL 25k VCC 25k PWR_DN VCC 25k 1 FB 0 /16 Bank A XTAL 0 1 Ref VCO /2 /4 0 1 1 0 /2 /4 /6 Bank B QB0 0 1 CLK STOP QB1 Bank C QC0 0 1 CLK STOP QC1 0 1 CLK STOP QA1 QA0
PLL
PLL_EN FSELA FSELB FSELC 3 x 25k CLK_STOP0 CLK_STOP1 OE/MR VCC 3 x 25k 3
Figure 1. MPC9330 Logic Diagram
REF_SEL PLL_EN 18 FB_SEL GND VCC
QB0
QB1
24 GND QA1 QA0 VCC FSELA FSELB FSELC NC 25 26 27 28
23
22
21
20
19
NC 17 16 15 14 13 GND QC1 QC0 VCC FB_IN CLK_STOP1 CLK_STOP0 NC 12 11 10 9 8 GND
MPC9330
29 30 31 32 1 2 3 4 5 6 7
VCC_PLL
PWR_DN
CCLK
XTAL_IN
OE/MR
The MPC9330 requires an external RC filter for the analog power supply pin VCC_PLL. Please see application section for details.
Figure 2. MPC9330 32-Lead Package Pinout (Top View)
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XTAL_OUT
NC
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MPC9330
Table 1: PIN CONFIGURATION
Pin CCLK XTAL_IN, XTAL_OUT FB_IN FB_SEL REF_SEL PWR_DN FSELA FSELB FSELC PLL_EN CLK_STOP0-1 OE/MR QA0-1, QB0-1, QC0-1 GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Input Output Supply Supply Supply Type LVCMOS Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock signal Crystal oscillator interface PLL feedback signal input, connect to an output Feedback select Reference clock select Output frequency and power down select Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs PLL enable/disable Clock output enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Negative power supply PLL positive power supply (analog power supply). The MPC9330 requires an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
Table 2: FUNCTION TABLE
Control REF_SEL FB_SEL PLL_EN Default 0 0 1 0 The crystal oscillator output is the PLL reference clock Internal PLL feedback of 16. fVCO = 16 * fref Test mode with PLL disabled. The reference clock is substituted for the internal VCO output. MPC9330 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 2 (High output frequency range) Output divider / 2 Output divider / 2 Output divider / 4 See Table 3 Outputs disabled (high-impedance state) and reset of the device. During reset in external feedback configuration, the PLL feedback loop is open. The VCO is tied to its lowest frequency. The MPC9330 requires reset at power-up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLK). Reset does not affect PLL lock in internal feedback configuration. Outputs enabled (active) 1 CCLK is the PLL reference clock External feedback. Zero-delay operation enabled for CCLK as reference clock Normal operation mode with PLL enabled.
PWR_DN FSELA FSELB FSELC CLK_STOP[0:1] OE/MR
1 0 0 0 11 1
VCO / 4 (Low output frequency range) Output divider / 4 Output divider / 4 Output divider / 6
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 1 to Table 3 for supported frequency ranges and output to input frequency ratios.
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Table 3: CLOCK OUTPUT SYNCHRONOUS DISABLE (CLK_STOP) FUNCTION TABLEa
CLK_STOP0 0 0 1 1 a. CLK_STOP1 0 1 0 1 QA[0:1] Active Active Stopped in logic L state Active QB[0:1] Stopped in logic L state Stopped in logic L state Stopped in logic L state Active QC[0:1] Stopped in logic L state Active Active Active
Output operation for OE/MR=1 (outputs enabled). OE/MR=1=0 will high-impedance tristate all outputs independend on CLK_STOP[0:1]
Table 4: GENERAL SPECIFICATIONS
Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC
B2
Max
Unit V V V mA pF pF
Condition
Per output Inputs
Table 5: ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 Unit V V V mA mA Condition
TS Storage Temperature -65 125 C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 6: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40C to 85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICC_PLL ICCQ a. b. Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Currentb Maximum PLL Supply Current Maximum Quiescent Supply Current 14 - 17 200 3.0 5.0 1.0 2.4 0.55 0.30 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V Condition LVCMOS LVCMOS IOH=-24 mAa IOL= 24 mA IOL= 12 mA VIN = VCC or GND VCC_PLL Pin
W
A mA
mA All VCC Pins The MPC9330 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Inputs have pull-down resistors affecting the input current.
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Table 7: AC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40C to 85C)a b
Symbol fref Characteristics Input Reference Frequencyc PLL mode, external feedback / 4 feedbackd / 8 feedback / 12 feedback / 16 feedback / 24 feedback PLL mode, internal feedback / 16 feedback) Input Reference Frequency in PLL bypass modee Min 50 25 16.67 12.5 8.33 12.5 200 10 / 4 output / 8 output / 12 output / 16 output / 24 output 50 25 16.67 12.5 8.33 40 CCLK or PCLK to FB_IN 100 150 45 0.1 50 55 1.0 10 10 RMS (1s)i RMS (1s) RMS (1s) / 4 feedback / 8 feedback / 12 feedback / 16 feedback / 24 feedback TBD TBD TBD TBD TBD TBD TBD TBD Typ Max 100 50 33.3 25 16.67 25 TBD 400 20 100 50 33.3 25 16.67 60 1.0 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps % ns ns ns ps ps ps kHz kHz kHz kHz kHz 0.55 to 2.4V 0.8 to 2.0V FB_SEL=1 & PLL locked PLL locked Condition PLL locked
fVCO fXTAL fMAX
VCO Lock Frequency Rangef Crystal Interface Frequency Rangeg Output Frequency
frefDC tr, tf t() tsk(o) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW
Reference Input Duty Cycle CCLK Input Rise/Fall Time Propagation Delay (static phase offset) Output-to-Output Skewh Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter PLL closed loop bandwidthj PLL mode, external feedback
a. b. c. d. e. f. g. h. i. j.
tLOCK Maximum PLL Lock Time 10 ms All AC characteristics are design targets and subject to change upon device characterization. AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN = 0 to enable the PLL. /4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one /2 output to FB_IN. See Table 1 to Table 3 for other feedback configurations. In bypass mode, the MPC9330 divides the input reference clock. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO / FB. The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio. See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 s. -3 dB point of PLL transfer characteristics.
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Table 8: DC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40C to 85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICC_PLL ICC a. Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current Maximum PLL Supply Current 2.0 17 - 20 200 5.0 Min 1.7 -0.3 1.8 0.6 Typ Max VCC + 0.3 0.7 Unit V V V V Condition LVCMOS LVCMOS IOH=-15 mAa IOL= 15 mA VIN = VCC or GND VCCA Pin
W
A mA
Maximum Quiescent Supply Current 1.0 mA All VCC Pins The MPC9330 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. Characteristics Input Reference Frequencyc PLL mode, external feedback Min 50 25 16.67 12.5 8.33 12.5 200 10 / 4 outputg / 8 output / 12 output / 16 output / 24 output 50 25 16.67 12.5 8.33 40 CCLK or PCLK to FB_IN 100 150 45 0.1 50 55 1.0 10 10 RMS (1s)i RMS (1s) RMS (1s) / 4 feedback / 8 feedback / 12 feedback / 16 feedback / 24 feedback TBD TBD TBD TBD TBD TBD TBD TBD Typ Max 100 50 33.3 25 16.67 25 TBD 400 20 100 50 33.3 25 16.67 60 1.0 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps % ns ns ns ps ps ps kHz kHz kHz kHz kHz 0.6 to 1.8V 0.7 to 1.7V FB_SEL=1 & PLL locked PLL locked Condition PLL locked
Table 9: AC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40C to 85C)a b
Symbol fref / 4 feedbackd / 8 feedback / 12 feedback / 16 feedback / 24 feedback PLL mode, internal feedback / 16 feedback) Input Reference Frequency in PLL bypass modee
fVCO fXTAL fMAX
VCO Lock Frequency Rangef Crystal Interface Frequency Rangeg Output Frequency
frefDC tr, tf t() tsk(o) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW
Reference Input Duty Cycle CCLK Input Rise/Fall Time Propagation Delay (static phase offset) Output-to-Output Skewh Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter PLL closed loop bandwidthj
a. b. c. d. e. f. g. h. i. j.
tLOCK Maximum PLL Lock Time 10 ms All AC characteristics are design targets and subject to change upon device characterization. AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN = 0 to enable the PLL. /4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one /2 output to FB_IN. See Table 1 to Table 3 for other feedback configurations. In bypass mode, the MPC9330 divides the input reference clock. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO / FB. The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio. See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 -3 dB point of PLL transfer characteristics.
s.
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MPC9330
APPLICATIONS INFORMATION
Output power down (PWR_DN) timing diagram
VCO/2 VCO/4 PWR_DWN QAx (/2) QBx (/4) QBCx (/6)
Output clock stop (CLK_STOP) timing diagram
QAx (/2) QBx (/4) QCx (/6)
CLK_STOP0 CLK_STOP1 QAx (/2) QBx (/4) QCx (/6)
Programming the MPC9330 The MPC9330 supports output clock frequencies from 6.67 to 200 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC and PWR_DN pins select the desired output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 1:4, 1:3, 1:2, 1:1, 2:3, 4:3 and 3:2. Tables 10 through 12 illustrate the various output configurations and frequency ratios supported by the MPC9330.
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Table 10: MPC9330 Example Configurations (Internal Feedback: FB_SEL = 0)
frefa [MHz] PWR_DN 0 0 0 0 0 0 0 0 10.0-25.0 1 1 1 1 1 1 1 a. FSELA 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 FSELB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 FSELC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 QA[0:1]:fref ratio fref 4 (40-100 MHz) fref 4 (40-100 MHz) fref 4 (40-100 MHz) fref 4 (40-100 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref fref fref (10-25 MHz) (10-25 MHz) (10-25 MHz) (10-25 MHz) QB[0:1]:fref ratio fref 4 (40-100 MHz) fref 4 (40-100 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 4 (40-100 MHz) fref 4 (40-100 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref fref (10-25 MHz) (10-25 MHz) QC[0:1]:fref ratio fref 2 fref 2 fref 2 fref 2 fref fref fref fref (20-50 MHz) (20-50 MHz) (20-50 MHz) (20-50 MHz) (10-25 MHz) (10-25 MHz) (10-25 MHz) (10-25 MHz) fref 4/3 (13.3-33.3 MHz) fref 4/3 (13.3-33.3 MHz) fref 4/3 (13.3-33.3 MHz) fref 4/3 (13.3-33.3 MHz) fref 2/3 (6.67-16.67 MHz) fref 2/3 (6.67-16.67 MHz) fref 2/3 (6.67-16.67 MHz) fref 2/3 (6.67-16.67 MHz)
fref 2 (20-50 MHz) fref 2 (20-50 MHz) fref fref (10-25 MHz) (10-25 MHz)
1 1 1 1 fref fref is the input clock reference frequency (CCLK or XTAL) frefa [MHz] 40-100 FSELA 0 0 0 0 FSELB 0 0 1 1 0 0 1 1 0 1 0 FSELC 0 1 0 1 0 1 0 1 1 1 1
Table 11: MPC9330 Example Configurations (External Feedback and PWR_DN = 0)
PLL Feedback VCO / 4b QA[0:1]:fref ratio fref (40-100 MHz) fref (40-100 MHz) fref (40-100 MHz) fref (40-100 MHz) fref (20-50 MHz) fref (20-50 MHz) fref (20-50 MHz) fref (20-50 MHz) fref 3 (40-100 MHz) fref 3 (40-100 MHz) fref 3/2 (20-50 MHz) QB[0:1]:fref ratio fref fref fref/2 fref/2 fref 2 fref 2 fref fref fref 3 (40-100 MHz) (40-100 MHz) (20-50 MHz) (20-50 MHz) (40-100 MHz) (40-100 MHz) (20-50 MHz) (20-50 MHz) (40-100 MHz) QC[0:1]:fref ratio fref/2 fref/2 fref/3 fref fref fref fref fref fref (20-50 MHz) (20-50 MHz) (13.3-33.3MHz) (20-50 MHz) (20-50 MHz) (13.3-33.3 MHz) (13.3-33.3 MHz) (13.3-33.3 MHz) (13.3-33.3 MHz)
fref/3 (13.3-33.3MHz)
VCO / 8c
20-50
1 1 1 1
fref 2/3 (13.3-33.3 MHz) fref 2/3 (13.3-33.3 MHz)
VCO / 12d
13.3-33.3
0 0 1
fref 3/2 (20-50 MHz) fref 3 (40-100 MHz) fref 3/2 (20-50 MHz)
a. b. c. d.
1 1 1 fref 3/2 (20-50 MHz) fref is the input clock reference frequency (CCLK or XTAL) QAx connected to FB_IN and FSELA=0, PWR_DN=0 QAx connected to FB_IN and FSELA=1, PWR_DN=0 QCx connected to FB_IN and FSELC=1, PWR_DN=0 frefa [MHz] 10-25 FSELA 1 1 1 1 FSELB 0 0 1 1 0 1 0 FSELC 0 1 0 1 1 1 1 QA[0:1]:fref ratio fref fref fref fref fref 3 fref 3 (10-25 MHz) (10-25 MHz) (10-25 MHz) (10-25 MHz) (20-50 MHz) (20-50 MHz)
Table 12: MPC9330 Example Configurations (External Feedback and PWR_DN = 1)
PLL Feedback VCO / 16b QB[0:1]:fref ratio fref 2 fref 2 fref fref fref 3 fref 3 (20-50 MHz) (20-50 MHz) (10-25 MHz) (10-25 MHz) (20-50 MHz) (20-50 MHz) QC[0:1]:fref ratio fref fref fref fref fref fref (10-25 MHz) (10-25 MHz) (6.67-16.67 MHz) (6.67-16.67 MHz) (6.67-16.67 MHz) (6.67-16.67 MHz)
fref 2/3 (6.6-16.6 MHz) fref 2/3 (6.6-16.6 MHz)
VCO / 24c
6.67-16.67
0 0 1
fref 3/2 (10-25 MHz) fref 3/2 (10-25 MHz)
fref 3/2 (10-25 MHz) fref 3/2 (10-25 MHz)
a. b. c.
1 1 1 fref is the input clock reference frequency (CCLK or XTAL) QAx connected to FB_IN and FSELA=1, PWR_DN=1 QCx connected to FB_IN and FSELC=1, PWR_DN=1
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MPC9330
APPLICATIONS INFORMATION
Power Supply Filtering The MPC9330 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9330 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9330. Figure 3. illustrates a typical power supply filter scheme. The MPC9330 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 3. "VCC_PLL Power Supply Filter" must have a resistance of 270W (VCC=3.3V) or 9-10W (VCC=2.5V) to meet the voltage drop criteria.
RF = 270 for VCC = 3.3V RF = 9-10 for VCC = 2.5V RF VCC CF 10 nF CF = 1 F for VCC = 3.3V CF = 22 F for VCC = 2.5V
differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC9330 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9330 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4. "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9330 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9330 OUTPUT BUFFER IN
14
VCC_PLL MPC9330 VCC 33...100 nF
RS = 36
ZO = 50 OutA
MPC9330 OUTPUT BUFFER IN
14
RS = 36
ZO = 50 OutB0
Figure 3. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3. "VCC_PLL Power Supply Filter", the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9330 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully
RS = 36
ZO = 50 OutB1
Figure 4. Single versus Dual Transmission Lines The waveform plots in Figure 5. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9330 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9330. The output waveform in Figure 5. "Single
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versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 ( 25 / (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 1. Final skew data pending specification.
3.0 OutA tD = 3.8956 OutB tD = 3.9386
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9330 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 6. Optimized Dual Line Termination
2.5
VOLTAGE (V)
2.0 In 1.5
1.0
0.5
0 2 4 6 8 TIME (nS) 10 12 14
Figure 5. Single versus Dual Waveforms
MPC9330 DUT Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 7. CCLK MPC9330 AC test reference for Vcc = 3.3V and Vcc = 2.5V
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VCC VCC VCC VCC
B2 B2
GND
CCLK
VCC VCC VCC VCC
B2 B2
GND FB_IN
GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
GND t()
Figure 8. Output-to-output Skew tSK(O)
Figure 9. Propagation delay (t(), static phase offset) test reference
VCC VCC tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
B2
CCLK
GND FB_IN
TJIT() = |T0 -T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 10. Output Duty Cycle (DC)
Figure 11. I/O Jitter
TN
TN+1
TJIT(CC) = |TN -TN+1 |
T0
TJIT(PER) = |TN -1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 12. Cycle-to-cycle Jitter
Figure 13. Period Jitter
VCC=3.3V 2.4 0.55 tF tR
VCC=2.5V 1.8V 0.6V
Figure 14. Output Transition Time Test Reference
TIMING SOLUTIONS
11
MOTOROLA
MPC9330
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V DETAIL Y
17
V1
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.
-T-, -U-, -Z-
G -AB-
SEATING PLANE
DETAIL AD
-AC- 0.10 (0.004) AC AE
8X
M_ R
P AE
CE
DETAIL Y
GAUGE PLANE
0.250 (0.010)
H
W X DETAIL AD
K
Q_
BASE METAL
N
F
D
J
SECTION AE-AE
MOTOROLA
12
0.20 (0.008)
M
AC T-U Z
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
EE EE EE
TIMING SOLUTIONS
MPC9330
NOTES
TIMING SOLUTIONS
13
MOTOROLA
MPC9330
NOTES
MOTOROLA
14
TIMING SOLUTIONS
MPC9330
NOTES
TIMING SOLUTIONS
15
MOTOROLA
MPC9330
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2002.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
MOTOROLA
16
MPC9330/D TIMING SOLUTIONS

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