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S i 5 1 0 0 / Si 5 11 0 - EVB
E v a l u a t i o n B o a r d S e t f o r S i 5 1 0 0 a n d S i 5 11 0 OC-48/STM-16 SONET/SDH TRANSCEIVERS
Description
The SI5100-EVB and Si5110-EVB motherboard/ daughter card sets provide a platform for testing and characterizing Silicon Laboratories' Si5100/Si5110 SiPHYTM OC-48/STM-16 SONET/SDH Transceiver. The Si5100 and Si5110 transceiver devices provide fullduplex operation at serial data rates up to 2.7 Gbps. The transceiver device is mounted on the EVB daughter card. The high-speed serial signals are accessed via SMA connectors on the daughter card itself. The lowspeed parallel data channels are routed from the daughter card to the motherboard through the industrystandard 300-pin meg-array connector. The included transceiver loopback motherboard provides a hardware connection between the transceiver low-speed parallel data outputs, RXDOUT, and the transceiver low-speed parallel data inputs, TXDIN. Test points are provided on the motherboard to allow monitoring of the parallel data channels. The clock signals associated with the low-speed data channels are routed to SMA connectors on the loopback motherboard. Static control and status signals are routed to standard 100-mil center posts. An optional full-duplex motherboard is also available for the transceiver daughter card. The full-duplex motherboard also utilizes the industry-standard 300-pin meg-array connector to allow attachment of the daughter card. The full-duplex motherboard routes all of the transceiver low-speed parallel data outputs and inputs to standard SMA connectors. The optional fullduplex motherboard is useful when connecting the transceiver device to a parallel bit error rate tester (ParBERT), or in other applications that require full access to the low-speed parallel data channels.
Features
!
! ! ! !
!
Separate supply connections for VDD (1.8 V) and VDDIO (1.8 V or 3.3 V) allow LVTTL I/Os to be powered at either 1.8 V or 3.3 V. Control inputs are jumper configurable. Status outputs brought out to headers for easy access. Potentiometers provided for controlling analog inputs. Loopback Motherboard (included) provides hardware path between low-speed parallel data outputs RXDOUT and low-speed parallel data inputs TXDIN. Optional full-duplex motherboard provides access to all low-speed parallel data outputs and inputs via SMA connectors.
Preliminary Rev. 0.5 6/03
Copyright (c) 2003 by Silicon Laboratories
Si5100/Si5110-EVB-05
Si5100/Si5110-EVB
Motherboard/Daughter Card Set
300-Pin Meg-Array Connector
Testpoints
Control Input Headers Pow er Connectors
er eiv nsc ac k Tra op b ard Lo erbo th Mo
Status Header & LEDs
0/ 10 Si5 11 0 i5 S
2.5 GHz transmit clock output
SMA Connectors for Parallel Interface Clock signals
2.5 Gbps Interface SMA Connectors Daughter Card
2
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Testpoints
RXDOUT Bus
TXDIN Bus
TXCLK16OUT
RXCLK2
TXCLK16IN
300-Pin MSA Connector
RXCLK1
TXREFCLK 3.3 V 1.8 V GND
RXREFCLK
Control Inputs Status Ouputs
Figure 1. Loopback Motherboard Functional Block Diagram
TXCLK16OUT
TXCLK16IN
RXCLK1
RXCLK2
TXDIN15
RXDOUT15
TXDIN1
RXDOUT1
TXDIN0
300-Pin MSA Connector
RXDOUT0
TXREFCLK 3.3V 1.8V GND
RXREFCLK
Control Inputs Status Ouputs
Figure 2. Optional Full-Duplex Motherboard Functional Block Diagram
Preliminary Rev. 0.5
3
Si5100/Si5110-EVB
Control Inputs Status Ouputs 300-Pin MSA Connector 3.3 V 1.8 V
TXCLK16IN/TXCLK4IN TXCLK16OUT/TXCLK4OUT
RXREFCLK
TXREFCLK
RXCLK1
RXCLK2
VREF SLICELVL TXDIN 16 pairs VREF LOSLVL VDD VDD33 VREF PHASEADJ
RXDOUT 16 pairs
2
2
2
22
RESET_N RXCLK2DSBL_N RXCLK2DIV_N LPTM_N FIFOERR_N FIFORST_N Other Input Signals Other Ouput Signals
Si5100/Si5110
Test Inputs Test Ouputs Control Inputs Status Ouputs
RXDIN
TXCLKOUT
TXDOUT
Figure 3. Daughter Card Functional Block Diagram
4
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Functional Description
The SI5100-EVB and Si5110-EVB motherboard and daughter card sets simplify characterization of the OC48/STM-16 and FEC transceiver devices by providing convenient access to the device I/Os. Device performance can be evaluated in various modes by following the "Basic Test Setup" section.
Data I/O Signals
The serial 2.5 Gbps data and 2.5 GHz clock paths are routed as coplanar differentially-coupled microstrip transmission lines on the daughter card. These three signals (RXDIN, TXCLKOUT, and TXDOUT) are ac coupled to standard SMA jacks for ease in connection to industry standard test equipment. Take care when connecting cables to these jacks. Use a standard SMA torque wrench to minimize reflections at the cable-tojack interface. Finally, match all differential connections in length to minimize phase differences between the positive and negative terminals.
Power Supply
The transceiver device can be powered from a single 1.8 V supply or seperate 1.8 V and 3.3 V supplies. When the additional 3.3 V supply is applied, the status outputs are LVTTL compatible. The daughter card can be configured for either mode of operation by setting the VDD_IO SEL jumper as shown in Figure 4.
Differential Parallel Data and Clock I/O Signals
The differential parallel data lines are routed through the 300-pin meg-array connector to the motherboard. The standard loopback motherboard directly couples the RXDOUT bus to the TXDIN bus. The optional fullduplex motherboard directly couples the RXDOUT and TXDIN buses to standard SMA jacks for connection to industry standard test equipment.
For 3.3 V/1.8 V operation 1.8 V VDD_IO SEL 3.3 V For 1.8 V operation only VDD_IO SEL 1.8 V
Slice Level, Loss-of-Signal Level, and Phase Adjust
Voltages present at the Slice Level (SLICELVL), Lossof-Signal Level (LOSLVL) and Phase Adjust (PHASEADJ) pins can be used to adjust the data slicing level, the loss-of-signal alarm level, and the sampling phase position, respectively. Because these inputs are high impedance, simple turn-based potentiometers are used to apply the control voltage. The SI5100-EVB provides 50 k potentiometers for each of these inputs: potentiometer R16 sets the voltage applied to the SLICELVL pin; R14 sets the voltage applied to the LOSLVL pin, and R15 sets the voltage applied to the PHASEADJ pin. The Si5110-EVB also provides 50 k potentiometers for each of these inputs. Potentiometer R5 sets the voltage applied to the SLICELVL pin; R3 sets the voltage applied to the LOSLVL pin, and R4 sets the voltage applied to the PHASEADJ pin. The potentiometers are connected so the voltage applied varies from GND to VREF. Refer to the device data sheet for details on the operation of these inputs.
3.3 V
Figure 4. VDD_IO Selection Jumpers
Control Inputs
The device control inputs are located on the motherboard and daughter card. Signals with equivalent module functions are routed to the motherboard header, JP1. Signals specific to the transceiver are routed on the daughter card to jumpers JP1 and JP2. In both cases, the signal is routed to the center pin of a three pin group where the adjacent pins are power and ground. The device inputs are pulled high or low so that leaving a signal unconnected will not harm the device.
Status Outputs
The device status outputs are located on the motherboard and daughter card. Signals with equivalent module functions are routed to the motherboard header, JP2. Signals specific to the transceiver are routed on the daughter card to headers JP3 and JP4. In both cases, the signal is routed to a header pin adjacent to a ground pin.
Basic Test Setup
The configurations listed in Tables 1 and 3 allow easy setup of the transceiver evaluation system for operation in the line loopback, full duplex, or diagnostic loopback modes. Other configurations are supported; however, operation should first be verified in one of these modes in order to minimize the number of unknown variables.
Preliminary Rev. 0.5
5
Si5100/Si5110-EVB
Line Loopback When configured in line-loopback mode, the device passes the received/recovered data and timing to the transmitter. The transmitter buffers the data through the FIFO and filters the jitter using the loop-bandwidth selected by BWSEL[1:0]. Operation in line loopback mode is depicted in Figure 5. Jumper settings for line loopback mode are given in Tables 1, 3 (Si5100), and 4 (Si5110). This mode of operation is attainable with both versions of the motherboard. Full-Duplex This mode is identical to normal operation of the device in a system. TX and RX can be asynchronous (up to 300 ppm) so all timing is independent. TXCLK16IN is chosen as the transmitter CMU reference clock via the REFSEL pin. Operation in full-duplex mode is depicted in Figure 6. Jumper settings for full-duplex mode are given in Tables 1, 3 (Si5100), and 4 (Si5110). If the loopback motherboard is used, the full-duplex mode effectively becomes an external loopback mode, and RXCLK1 should be connected to TXCLK16IN/ TXCLK4IN to clock in the data. Diagnostic Loopback (Parallel Side Loopback) This mode passes the data present on the transmit parallel inputs (TXDIN[15:0] for Si5100; TXDIN[3:0] for Si5110) to the receive parallel data outputs (RXDOUT[15:0] for Si5100; RXDOUT[3:0] for Si5110). TXCLK16IN/TXCLK4IN is chosen as the transmitter CMU reference clock via the REFSEL pin. Operation in diagnostic loopback mode is depicted in Figure 7. Jumper settings for diagnostic loopback mode are given in Tables 2, 3 (Si5100), and 4 (Si5110). The full-duplex motherboard is required for this mode.
Si5100/Si5110
Receiver RXDIN RXCLK1 TXDOUT TXREFCLK TXCLK Transmitter TXCLK16IN/ TXCLK4IN TXDIN RXDOUT
Si5100/Si5110
Receiver RXDIN RXCLK1 TXDOUT TXREFCLK TXCLK Transmitter TXCLK16IN/ TXCLK4IN TXDIN RXDOUT
Figure 6. Full Duplex
Si5100/Si5110
Receiver RXDIN RXCLK1 TXDOUT TXREFCLK TXCLK Transmitter TXCLK16IN/ TXCLK4IN TXDIN RXDOUT
Figure 7. Diagnostic Loopback
Figure 5. Line Loopback
6
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Both the motherboard and daughter card are placed in line loopback mode before shipment to customers.
Table 1. Loopback Motherboard Setup
Header--Pin JP10--2 JP1--14 JP1--11 JP1--8 JP1--5 JP1--2 JP2--5 JP2--2 JP3--8 JP3--5 JP3--2 JP7--5 JP7--2 JP6--4 Signal Name Voltage Select RXCLK1DSBL_N LTR_N RXSQLCH_N RXCLK2DIV_N RXCLK2DSBL_N TXREFRATE TXRESET_N DLBK_N LLBK_N LPTM_N RXREFRATE RXRESET_N FIFORST_N Line Loopback 3.3 V high high low don't care don't care high high high low (enables line loopback) high open high tie to FIFOERR Asynchronous TX/RX 3.3 V high high high don't care don't care high high high high high open high tie to FIFOERR
Table 2. Full-Duplex Motherboard Setup
Header--Pin JP8--2 JP1--14 JP1--11 JP1--8 JP1--5 JP1--2 JP2--5 JP2--2 JP3--8 JP3--5 JP3--2 JP7--5 JP7--2 JP6--4 Signal Name Voltage Select RXCLK1DSBL_N LTR_N RXSQLCH_N RXCLK2DIV_N RXCLK2DSBL_N REFRATE RESET_N DLBK_N LLBK_N LPTM_N Si5530 REFRATE Si5530 RESET_N FIFORST_N Line Loopback 3.3 V high high low don't care don't care high high high low (enables line loopback) high open high tie to FIFOERR Asynchronous TX/RX 3.3 V high high high don't care don't care high high high high high open high tie to FIFOERR Diagnostic Loopback 3.3 V high high high don't care don't care high high low high high open high tie to FIFOERR
Table 3. Si5100 Daughter Card Setup
Line Loopback 11 (for widest CMU loop bandwidth) JP1--17 REFSEL high JP1--14 MODE16 high JP1--11 TXCLKDSBL low JP1--8 TXMSBSEL low JP1--5 TXSQLCH_N high JP1--2 RXMSBSEL low Note: Jump the VDD_IO selection jumper toward the 3.3 V side. Header--Pin JP1--20 JP1--23 Signal Name BWSEL0 BWSEL1 Asynchronous TX/RX 11 (for widest CMU loop bandwidth) high high low low high low Diagnostic Loopback 11 (for widest CMU loop bandwidth) high high low low high low
Preliminary Rev. 0.5
7
Si5100/Si5110-EVB
Table 4. Si5110 Daughter Card Setup
Line Loopback 11 (for widest CMU loop bandwidth) JP1--17 REFSEL high JP1--14 TXCLKDSBL low JP1--11 TXMSBSEL low JP1--8 TXSQLCH_N high JP1--5 SLICEMODE low JP1--2 RXMSBSEL low Note: Jump the VDD_IO selection jumper toward the 3.3 V side. Header--Pin JP1--20 JP1--23 Signal Name BWSEL0 BWSEL1 Asynchronous TX/RX 11 (for widest CMU loop bandwidth) high low low high low low Diagnostic Loopback 11 (for widest CMU loop bandwidth) high low low high low low
8
Preliminary Rev. 0.5
VDD_IO
VDD
H3
VDD_33
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36
E5 F5 G5 H5 J5 K5 E6 F6 G6 H6 J6 K6 E7 F7 G7 H7 J7 K7 E8 F8 G8 H8 J8 K8 E9 F9 G9 H9 J9 K9 E10 F10 G10 H10 J10 K10
C3 0402 0.033uF
J3
C1
0402 0.033uF
J1
C2
C4 0402 0.033uF C5
J4
J2 TXCLK16IN+ TXCLK16INTXCLK16IN+ TXCLK16INRXDIN+ RXDINREFCLK+ REFCLKTXCLKOUT+ TXCLKOUTG1 H1 RXCLK2+ RXCLK2B2 B3 RXCLK1+ RXCLK1D1 E1 G14 H14 REFSEL RXMSBSEL N2 N1 Si5100 U1 A2 A3
0402 0.033uF
TXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3TXDIN4+ TXDIN4TXDIN5+ TXDIN5TXDIN6+ TXDIN6TXDIN7+ TXDIN7TXDIN8+ TXDIN8TXDIN9+ TXDIN9TXDIN10+ TXDIN10TXDIN11+ TXDIN11TXDIN12+ TXDIN12TXDIN13+ TXDIN13TXDIN14+ TXDIN14TXDIN15+ TXDIN15TXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3TXDIN4+ TXDIN4TXDIN5+ TXDIN5TXDIN6+ TXDIN6TXDIN7+ TXDIN7TXDIN8+ TXDIN8TXDIN9+ TXDIN9TXDIN10+ TXDIN10TXDIN11+ TXDIN11TXDIN12+ TXDIN12TXDIN13+ TXDIN13TXDIN14+ TXDIN14TXDIN15+ TXDIN15RXCLK1+ RXCLK1RXCLK2+ RXCLK2J5 RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3RXDOUT4+ RXDOUT4RXDOUT5+ RXDOUT5RXDOUT6+ RXDOUT6RXDOUT7+ RXDOUT7RXDOUT8+ RXDOUT8RXDOUT9+ RXDOUT9RXDOUT10+ RXDOUT10RXDOUT11+ RXDOUT11RXDOUT12+ RXDOUT12RXDOUT13+ RXDOUT13RXDOUT14+ RXDOUT14RXDOUT15+ RXDOUT15-
P4 P3 N4 N3 P6 P5 N6 N5 P8 P7 N8 N7 P10 P9 N10 N9 P12 P11 N12 N11 P14 P13 N14 N13 L14 M14 L13 M13 J14 K14 J13 K13 RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3RXDOUT4+ RXDOUT4RXDOUT5+ RXDOUT5RXDOUT6+ RXDOUT6RXDOUT7+ RXDOUT7RXDOUT8+ RXDOUT8RXDOUT9+ RXDOUT9RXDOUT10+ RXDOUT10RXDOUT11+ RXDOUT11RXDOUT12+ RXDOUT12RXDOUT13+ RXDOUT13RXDOUT14+ RXDOUT14RXDOUT15+ RXDOUT15-
A4 A5 B4 B5 A6 A7 B6 B7 A8 A9 B8 B9 A10 A11 B10 B11 A12 A13 B12 B13 A14 B14 C13 D13 C14 D14 E13 F13 E14 F14 G13 H13
VDD_IO
C6
J6
JP1 REFRATE
2
RXMSBSEL
Si5530_REFCLK+ Si5530_REFCLK-
5
TXSQLCH_N
0402 0.033uF
8
TXMSBSEL
RXSQLCH_N
11
TXCLKDSBL
TXDOUT+ TXDOUT-
K1 L1
14
MODE16
RXCLK2DIV_N RXCLK1DSBL_N RXCLK2DSBL_N LTR_N
17
REFSEL
TXCLK16OUT+ TXCLK16OUT-
P2 P1
TXCLK16OUT+ TXCLK16OUT-
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39
R1 0603 3.09k
Do NOT install
Si5100/Si5110-EVB
Figure 8. SI5100-EVB Daughter Card Schematic (page 1 of 3)
R2 0603 3.09k
B1 C1 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 F1 J1 M1 J3 M3 J4 M4 D5 L5 D6 L6 D7 L7 D8 L8 D9 L9 D10 L10 D11 E11 F11 G11 H11 J11 K11 L11
Preliminary Rev. 0.5
TXSQLCH_N TXCLKDSBL TXMSBSEL MODE16 BWSEL0 BWSEL1 H4 L12 C9 D12 C12 F4 C8 E3 M12 K12 M9 G12 M7 M10 REFRATE REFSEL RXSQLCH_N RXMSBSEL RXCLK2DIV_N RXCLK1DSBL_N RXCLK2DSBL_N LTR_N TXSQLCH_N TXCLKDSBL TXMSBSEL MODE16 BWSEL[0] BWSEL[1] RXLOL_N TXLOL_N LOS_N FIFOERR_N DLBK_N LLBK_N LPTM_N DLBK_N LLBK_N LPTM_N FIFORST_N RESET_N FIFORST_N RESET_N M6 G4 F12 H12 J12 LOSLVL PHASEADJ SLICELVL LOSLVL PHASEADJ SLICELVL C3 D4 C4 RSVD_GND1 RSVD_GND2 RSVD_GND3 NC1 NC2 RSVD_GND4 RSVD_GND5 RSVD_GND6 RSVD_GND7 GND40 M8 K4 C7 C6 E4 RSVD_GND4 RSVD_GND5 RSVD_GND6 RSVD_GND7 GND40 TXREXT RXREXT L3 C11 VREF R17 0 ohm SW1 SW PUSHBUTTON
20
BWSEL0
1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24
23
BWSEL1
F3 M5 G3 K3
RXLOL_N TXLOL_N LOS_N FIFOERR_N HEADER 3X2 RSVD_GND1 RSVD_GND2 RSVD_GND3
HEADER 8X3
VDD_IO
JP2
2
RSVD_GND5
1 3 5 M11 E12 D3 NC1 C10 L4 NC2 C5 JP4
2 4 6
Reserved for Factory Testing
HEADER 2X1 1 2 JP7 HEADER 2X1 1 JP8 2
5
RSVD_GND4
8
RSVD_GND7
11
RSVD_GND6
1 3 4 6 7 9 10 12 13 15
14
GND40
HEADER 5X3
Reserved for Factory Testing
VREF
9
10
3.3V J7H J7J J7B J7D J7I DLBK_N RXCLK1DSBL_N RXCLK2DSBL_N RXLOL_N RXCLK2DIV_N LTR_N RXSQLCH_N RESET_N FIFORST_N FIFOERR_N TXLOL_N LLBK_N LPTM_N H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 3.3V J7F L1 Murata BLM31P601SG C29 + C13 3216 10 uF C14 3216 10 uF + 0402 0.1uF 0402 0.1uF 0402 100pF C8 C10 C7 0402 0.1uF 1.8V VDD
Si5100/Si5110-EVB
VDD
Place Close to 5100 part on bottom of board
C30
C28
C31
C9 0402 0.1uF
C21 0402 0.1uF
C22 0402 0.1uF
0805 4.7uF
0805 4.7uF
0402 0.1uF
LOS_N
C11 0402 100pF
C12 0402 100pF
C23 0402 100pF
C24 0402 100pF
Preliminary Rev. 0.5
3.3V VDD_IO C25 0805 4.7uF C15 0402 0.1uF REFRATE 0402 0.1uF C27 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
1.8V
C26 0805 4.7uF
JP6
Figure 9. SI5100-EVB Daughter Card Schematic (page 2 of 3)
J7A RXDOUT4+ RXDOUT4RXDOUT5+ RXDOUT5RXDOUT6+ RXDOUT6RXDOUT7+ RXDOUT7RXCLK2+ RXCLK2TXDIN4+ TXDIN4TXDIN5+ TXDIN5TXDIN6+ TXDIN6TXDIN7+ TXDIN7TXCLK16OUT+ TXCLK16OUTTXDIN11+ TXDIN11TXDIN15+ TXDIN15TXCLK16IN+ TXCLK16INTXDIN10+ TXDIN10TXDIN14+ TXDIN14TXDIN9+ TXDIN9TXDIN13+ TXDIN13TXDIN8+ TXDIN8TXDIN12+ TXDIN12RXCLK1+ RXCLK1RXDOUT11+ RXDOUT11RXDOUT15+ RXDOUT15RXDOUT10+ RXDOUT10RXDOUT14+ RXDOUT14RXDOUT9+ RXDOUT9RXDOUT13+ RXDOUT13RXDOUT8+ RXDOUT8RXDOUT12+ RXDOUT12-
J7C
J7E
J7G
RXDOUT0+ RXDOUT0-
RXDOUT1+ RXDOUT1-
RXDOUT2+ RXDOUT2-
RXDOUT3+ RXDOUT3-
RXREFCLK+ RXREFCLK-
TXDIN0+ TXDIN0-
TXDIN1+ TXDIN1-
TXDIN2+ TXDIN2-
TXDIN3+ TXDIN3C16 0402 0.1uF C17 0402 0.1uF
Si5530_REFCLK+
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30
Si5530_REFCLK-
JP9 VREF
1
R14 POT 2
HEADER 2X1 1 2 JP10 LOSLVL
C18 RXREFCLK+ R6 49.9 ohm 1%, 0603 0603 0.1uf
1
3
0603 0.1uf
1
3
Si5100/Si5110-EVB
Figure 10. SI5100-EVB Daughter Card Schematic (page 3 of 3)
3
Preliminary Rev. 0.5
R7 49.9 ohm 1%, 0603 C19 RXREFCLK-
R15 POT 2
HEADER 2X1 1 2 JP11 PHASEADJ
R16 POT 2
HEADER 2X1 1 2 JP12 SLICELVL
11
Si5100/Si5110-EVB
Bill of Materials: SI5100-EVB Daughter Card Assembly Revision D-01
Si5100EVB Assy Rev D-01 BOM Reference C1,C2,C3,C4,C5,C6 C7,C8,C9,C15,C16,C17, C21,C22,C27,C29,C31 C10,C11,C12,C23,C24 C14,C13 C18,C19 C25,C26,C28,C30 JP1 JP2 JP4 JP6 JP7,JP8,JP9,JP10,JP11, JP12 J1,J2,J3,J4,J5,J6 J7 L1 R1,R2 R6,R7 R14,R15,R16 U1 PCB No Load SW1 R17 Description CAP, SM, 0.033 uF, 0402 CAP, SM, 0.1 uF, 0402 CAP, SM, 100 pF, 0402 CAP, SM, 10 uF, TANTALUM, 3216 CAP, SM, 0.1 uF, 0603 CAP,SM,4.7UF,6.3V,X7R,0805 CONNECTOR, HEADER, 8X3 CONNECTOR, HEADER, 5X3 CONNECTOR, HEADER, 3X2 CONNECTOR, HEADER, 3X1 CONNECTOR, HEADER, 2X1 CONNECTOR, SMA, NOTCH MOUNT CONN,SM,RECPT,MEGARRAY,300 POS BGA FERRITE,SM,600 OHM,1500mA RESISTOR, SM, 3.09K, 1%, 0603 RES,SM,49.9,1%,0603 POT,50K,10%,MULTITURN TRIMMER Si5100 Rev D Device Printed Circuit Board Manu Number C0402X7R160333KNE C0402X7R160104KNE C0402C0G500-101JNE TA010TCM106KAR C0603X7R160-104KNE CEJMK212BJ475KG-T 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 82 SMA-S50-1-45/111 NE 84502-101 BLM31P601SGPT CR0603-16W-3091FT CR0603-16W-49R9FT T93YA-50K-10%-D06 Si5100 Rev D SI5100-EVB Daughter Card PCB Rev D Manufacturer VENKEL VENKEL VENKEL VENKEL VENKEL TAIYO YUDEN 3M 3M 3M 3M 3M HUBER SUHNER FCI/BERG MURATA VENKEL VENKEL VISHAY/DALE SILICON LABORATORIES SILICON LABORATORIES
SWITCH, PUSH BUTTON, MINIATURE RES,SM,0,0603
101-0161 CR0603-16W-000T
MOUSER VENKEL
12
Preliminary Rev. 0.5
VDD_IO
VDD
G2
TXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3TXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3-
J10 K10 J9 K9 G10 H10 G9 H9 RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3-
VDD_33
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14
D4 D5 D6 D7 E4 E5 E6 F4 F5 F6 G4 G5 G6 G7
A10 B10 A9 B9 C10 D10 C9 D9
VDD_IO C1 FIFOERR_N J5 FIFOERR_N 0402 0.1uF J1
JP1
2
SLICEMODE
5
RXMSBSEL
8
TXSQLCH_N C2 FIFORST_N FIFORST_N H5 0402 0.1uF Si5110 U1 RXCLK1+ RXCLK1RXCLK2+ RXCLK2A8 A7 B8 B7 C3 J3 J2
11
TXMSBSEL
14
TXCLKDSBL
17 TXCLK4IN+ TXCLK4INTXCLK4IN+ TXCLK4INRXDIN+ RXDINREFCLK+ REFCLKTXCLKOUTTXCLKOUT+ TXDOUT+ TXDOUTF1 E1 H1 J1 C5 B1 C1 0402 0.1uF J4 C6 TXREFCLK+ TXREFCLKRESET_N REFSEL E10 F10 K8 K7
REFSEL RXCLK1+ RXCLK1RXCLK2+ RXCLK2-
20
BWSEL0
1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24
23
BWSEL1
0402 0.1uF C4 J5
HEADER 8X3
VDD_IO J6 0402 0.1uF
0402 0.1uF
JP2
2
RSVD_GND2
5
RSVD_GND3
8
RSVD_GND0
REFRATE RXCLK2DIV_N RXCLK1DSBL_N RXCLK2DSBL_N RXSQLCH_N
TXCLK4OUT+ TXCLK4OUT-
K6 K5
TXCLK4OUT+ TXCLK4OUT-
1 3 4 6 7 9 10 12 RXMSBSEL TXCLKDSBL TXSQLCH_N TXMSBSEL BWSEL0 BWSEL1 SLICEMODE
11
RSVD_GND1
HEADER 4X3 DLBK_N LLBK_N LPTM_N LTR_N
RXLOL_N TXLOL_N LOS_N
C3 K4 D2
RXLOL_N TXLOL_N LOS_N VDD_IO
E3 J7 F3 C8 D3 C7 A5 D8 J8 J6 H4 H6 H3 C6 H7 H8 G8 C4 RESET_N REFSEL REFRATE RXCLK2DIV_N RXCLK1DSBL_N RXCLK2DSBL_N RXSQLCH_N RXMSBSEL TXCLKDSBL TXSQLCH_N TXMSBSEL BWSEL0 BWSEL1 SLICEMODE DLBK_N LLBK_N LPTM_N LTR_N
JP3 1 JP11 RSVD_GND5 RSVD_GND4 G3 C5 2 JP4 RXAMPMON B5 K2 NC
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15
HEADER 2X1 2 HEADER 1X3 1 3 HEADER 2X1 1 JP10 1 VREF B4 VREF 2 HEADER 2X1 2
R1 0603 3.09k 1%
R2 0603 3.09k 1%
Si5100/Si5110-EVB
Figure 11. Si5110-EVB Daughter Card Schematic (page 1 of 3)
B2 C2 D1 E2 E7 E8 E9 F2 F7 F8 F9 G1 H2 J2 K1
Preliminary Rev. 0.5
RSVD_GND3 RSVD_GND2 RSVD_GND1 RSVD_GND0 J4 J3 B6 A6 RSVD_GND3 RSVD_GND2 RSVD_GND1 RSVD_GND0 LOSLVL PHASEADJ SLICELVL LOSLVL PHASEADJ SLICELVL TXREXT RXREXT K3 A4 B3 A2 A3
13
14
J7J 1.8V 3.3V VDD_IO C7 JP5 0402 0.1uF 0402 0.1uF C8 RXCLK1DSBL_N RXCLK2DSBL_N RESET_N FIFORST_N FIFOERR_N VDD L1 Murata BLM31P601SG C9 J7D 0805 4.7uF 0805 4.7uF 0402 0.1uF 0402 0.1uF 0402 0.1uF J7I C10 C11 C12 C13 C14 0402 100pF K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 3.3V 1.8V J7F + C15 3216 10 uF + C16 3216 10 uF LOS_N REFRATE F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30
J7H
DLBK_N
LLBK_N
Si5100/Si5110-EVB
LPTM_N
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30
J7B
RXSQLCH_N
LTR_N
RXCLK2DIV_N
Preliminary Rev. 0.5
RXLOL_N
TXLOL_N
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30
Figure 12. Si5110-EVB Daughter Card Schematic (page 2 of 3)
JP6 J7A J7C J7E J7G VREF
RXDOUT0+ RXDOUT01
RXDOUT1+ RXDOUT1R3 POT 50K 2 HEADER 2X1 1 JP7
3
RXDOUT2+ RXDOUT22
LOSLVL
RXDOUT3+ RXDOUT3RXCLK2+ RXCLK21
RXREFCLK+ RXREFCLKR4 POT 50K 2 1 JP8
3
RXCLK1+ RXCLK1HEADER 2X1 2
TXDIN0+ TXDIN0-
PHASEADJ
TXDIN1+ TXDIN1-
TXDIN2+ TXDIN21
TXDIN3+ TXDIN3TXCLK4OUT+ TXCLK4OUTTXCLK4IN+ TXCLK4IN-
HEADER 2X1 1 JP9 2 SLICELVL
C17
R5 POT 50K 2
TXREFCLK+
0603 0.1uF C18
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
3
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30
TXREFCLK-
0603 0.1uF
C19 RXREFCLK+ R6 49.9 ohm 1%, 0603 0603 0.1uf
R7 49.9 ohm 1%, 0603 C20 RXREFCLKVDD
Place Close to 5110 part on bottom of board
0603 0.1uf
C21 0402 0.1uF 0402 0.1uF 0402 0.1uF 0402 0.1uF 0402 100pF 0402 100pF 0402 100pF
C22
C23
C24
C25
C26
C27
C28 0402 100pF
C29 0805 4.7uF
C30 0805 4.7uF
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 13. Si5110-EVB Daughter Card Schematic (page 3 of 3)
15
Si5100/Si5110-EVB
Bill of Materials: Si5110-EVB Daughter Card Assembly Revision D-01
Si5110 EVB Daughter Card Assy Rev. E-01 BOM Reference C1,C2,C3,C4,C5,C6,C7,C8 C11,C12,C13,C21,C22,C23 C24 C9,C10,C29,C30 C14,C25,C26,C27,C28 C15,C16 C17,C18,C19,C20 JP1 JP5 JP4,JP6,JP7,JP8,JP9 J1,J2,J3,J4,J5,J6 J7 L1 R2,R1 R3,R4,R5 R6,R7 U1 PCB Part Desc CAP,SM,0.1UF,16V,10%,X7R,0402 Part Number C0402X7R160-104KNE Manufacturer VENKEL
CAP,SM,4.7UF,6.3V,X7R,0805 CAP,SM,100PF,50V,5%,C0G,0402 CAP,SM,10UF,10V,10%,TANTALUM,3216 CAP,SM,0.1UF,16V,20%,X7R,0603 CONN,HEADER,8X3 CONN,HEADER,3X1 CONN,HEADER,2X1 CONNECTOR, SMA, NOTCH MOUNT CONN,SM,RECPT,MEGARRAY,300 POS BGA FERRITE,SM,600 OHM,1500mA RES,SM,3.09K,1%,0603 POT,50K,10%,MULTITURN TRIMMER RES,SM,49.9,1%,0603 Si5110 Rev E Device Printed Circuit Board
CEJMK212BJ475KG-T C0402C0G500-101JNE TA010TCM106KAR C0603X7R160-104KNE 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 82 SMA-S50-1-45/111 NE 84502-101 BLM31P601SGPT CR0603-16W-3091FT T93YA-50K-10%-D06 CR0603-16W-49R9FT Si5110-BC Si5110-EVB Daughter Card PCB Rev C
TAIYO YUDEN VENKEL VENKEL VENKEL 3M 3M 3M HUBER SUHNER FCI/BERG MURATA VENKEL VISHAY/DALE VENKEL SILICON LABS SILICON LABS
JP2 JP3, JP10 JP11
CONN,HEADER,4X3 CONN,HEADER,2X1 CONN,HEADER,1X3
2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN
3M 3M 3M
16
Preliminary Rev. 0.5
RXCLK1+ RXCLK1J2 R5 TXCLK16IN+ J1E TP18 In In TXCLK16IN0603, 0 ohm SMA J6 R9 RXREFCLK+ 0603, 0 ohm SMA J8 R11 RXREFCLK0603, 0 ohm SMA J10 R13 RXCLK1+ 0603, 0 ohm SMA J12 R15 RXCLK10603, 0 ohm SMA SMA 0603, 0 ohm J13 SMA R16 TXCLK16OUT0603, 0 ohm J11 SMA R14 TXCLK16OUT+ 0603, 0 ohm J9 SMA R12 RXCLK20603, 0 ohm R10 RXCLK2+ J7 SMA 0603, 0 ohm In In In
DATA15DATA15+ DATA14DATA14+ DATA13DATA13+ DATA12DATA12+
Layout Note: All loopback data pairs have testpoints to facilitate probing access.
J3 R6 TXREFCLK+ 0603, 0 ohm SMA R7 J5 R8 TXREFCLK0603, 0 ohm SMA J4
TP17 1 1 1 1 1 1 1 1 J1G
In
1
TP19 TP20 TP22 TP24 TP26 TP28 In In In TP30 TP32
In
1
TP21
In
1
TP23
In
1
TP25
In
1
TP27
In
1
In
1
TP31
In
1
TXCLK16OUT+ TXCLK16OUTTXCLK16IN+ TXCLK16INMeg-Array 300 Meg-Array 300
DATA11DATA11+ DATA10DATA10+ DATA9DATA9+ DATA8DATA8+
TP29
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30
Preliminary Rev. 0.5
3.3V POS1 1 2 3 VMBO J14 3.3V 1.8V J15 POS1 1 2 POS2 POS3 3 -5.2V 5V
1.8V
MOTHERBOARD OUTPUT SIGNAL VOLTAGE SELECT
3.3V/1.8V
POS2 POS3 MKDSN 2,5/3-5,08
-5.2V/5V
JP10 MKDSN 2,5/3-5,08
Si5100/Si5110-EVB
Figure 14. Loopback Motherboard Schematic (page 1 of 2)
17
1 3 4 6 10 GND U1 JP3 1 3 3 1x3 HEADER 2 1 2 2OE 3.3V 19 TP13 In In 1 In TP16 1 1 In 1 TP15 TP14
HEADER 2X3
JP4
DATA3DATA3+ DATA2DATA2+ DATA1DATA1+ DATA0DATA0+
DATA7DATA7+ DATA6DATA6+ DATA5DATA5+ DATA4DATA4+
18
RXREFCLK+ RXREFCLKTP1 In 3.3V 74LCX244T, 20TSSOP 20 VCC D1 D2 D3 D4 R2 R3 R4 R1 1OE 1 365r 0603 365r 0603 365r 0603 365r 0603 3.3V In In FIFOERR_N RXLOL_N TXLOL_N LOS_N 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 In In In 1 In TP12 1 1 In TP10 1 1 In TP8 1 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 1 In TP6 1 2 4 6 8 18 16 14 12 1 In TP4 1 1 In 1 TP3 TP5 TP7 TP9 TP11 J1A TP2 J1C RXCLK2+ RXCLK211 13 15 17 9 7 5 3 C1 0402 0.1uF C2 0402 100pF
VMBO
JP1
2
RXCLK2DSBL_N
5
RXCLK2DIV_N
8
RXSQLCH_N
11
LTR_N
1 3 4 6 7 9 10 12 13 15
14
RXCLK1DSBL_N
HEADER 5X3
JP2
2
TXRESET_N
5
TXREFRATE
2
LPTM_N
5 TXREFCLK+ TXREFCLKMeg-Array 300 Meg-Array 300
LLBK_N
LED ENABLE/ DISABLE
1 3 4 6 7 9
8
DLBK_N
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30
HEADER 3X3
74244 Decoupling Caps
JP5
1
2
FIFOERR_N
Si5100/Si5110-EVB
HEADER 1X2
JP6 1.8V J1B J1D J1F J1H 3.3V
1 3
2
FIFORST_N
Placed together to allow jumpering of FIFOERR_N to FIFORST
J1I
5V
-5.2V
HEADER 1X3
J1J
JP7 RXSQLCH_N LTR_N RXCLK2DIV_N RXLOL_N RXREFRATE LOS_N DLBK_N
2
RXRESET_N
RXRESET_N RXCLK1DSBL_N RXCLK2DSBL_N
1 3 4 6
5
RXREFRATE
HEADER 2X3
JP8
1 3 5
2 4 6
RXLOL_N TXLOL_N LOS_N
Preliminary Rev. 0.5
LLBK_N LPTM_N Meg-Array 300 TXLOL_N Meg-Array 300 Meg-Array 300 TXREFRATE Meg-Array 300
HEADER 3X2
TXRESET_N FIFORST_N FIFOERR_N Meg-Array 300
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 Meg-Array 300
Figure 15. Loopback Motherboard Schematic (page 2 of 2)
Si5100/Si5110-EVB
Bill of Materials: Loopback Motherboard Assembly Revision A-01
Si5100 Loopback Motherboard Assy Rev A-01 Reference Part Desc Part Number Manufacturer
C1 C2 D1,D2,D3,D4 JP1 JP2,JP7 JP3,JP6 JP4 JP5 JP8 JP10 J1 J2,J3,J4,J5,J6,J7,J8,J9, J10,J11,J12,J13 J15,J14 R1,R2,R3,R4 R5,R6,R7,R8,R9,R10,R11, R12,R13,R14,R15,R16 TP1,TP2,TP3,TP4,TP5,TP6, TP7,TP8,TP9,TP10,TP11, TP12,TP13,TP14,TP15,TP16, TP17,TP18,TP19,TP20,TP21, TP22,TP23,TP24,TP25,TP26, TP27,TP28,TP29,TP30,TP31, TP32 U1 PCB
CAP,SM,0.1UF,16V,10%,X7R,0402 CAP,SM,100PF,50V,5%,C0G,0402 LED,SM,RED CONN,HEADER,5X3 CONN,HEADER,2X3 CONN,HEADER,1X3 CONN,HEADER,3X3 CONN,HEADER,1X2 CONN,HEADER,3X2 CONN,HEADER,3X1 CONNECTOR,SM,300 POS,BGA CONNECTOR,SMA,SURFACE MOUNT CONNECTOR,POWER,3 POSITION RESISTOR, SM, 365 OHM, 1%, 0603 RES,SM,0,0402 TEST POINTS ON PCB
C0402X7R160-104KNE C0402C0G500-101JNE LN1271RAL-TR 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 84500-02 142-0711-201 1729021 CR0603-16W-121JT CR0402-16W-000T N/A
VENKEL VENKEL PANASONIC 3M 3M 3M 3M 3M 3M 3M BERG JOHNSON COMPONENTS PHOENIX CONTACT VENKEL VENKEL N/A
IC,SM,74LCX244,20TSSOP Printed Circuit Board
74LCX244MTC SI5100-EVB Loopback Motherboard PCB Rev A
FAIRCHILD SILICON LABORATORIES
Preliminary Rev. 0.5
19
20
J13 R13 RXDOUT6+ 0603, 0 ohm SMA J14 R14 RXDOUT60603, 0 ohm SMA J15 R15 RXDOUT7+ 0603, 0 ohm J40 J16 R16 TXDIN3RXDOUT130603, 0 ohm 0603, 0 ohm 0603, 0 ohm SMA J17 R17 RXDOUT8+ 0603, 0 ohm SMA J18 R18 RXDOUT80603, 0 ohm 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm SMA J19 R19 RXDOUT9+ 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm SMA J20 R20 RXDOUT90603, 0 ohm 0603, 0 ohm 0603, 0 ohm RXDOUT15TXDIN50603, 0 ohm SMA J21 R21 RXDOUT10+ 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm TXDIN0+ TXDIN6+ 0603, 0 ohm SMA J22 R22 RXDOUT100603, 0 ohm 0603, 0 ohm TXDIN00603, 0 ohm R34 R46 TXDIN60603, 0 ohm SMA J23 R23 RXDOUT11+ 0603, 0 ohm 0603, 0 ohm TXDIN1+ 0603, 0 ohm R35 J35 J47 R47 TXDIN7+ 0603, 0 ohm SMA J24 R24 RXDOUT110603, 0 ohm 0603, 0 ohm R36 TXDIN10603, 0 ohm J36 J48 R48 TXDIN70603, 0 ohm SMA J60 R60 TXDIN130603, 0 ohm J72 R72 RXCLK1J59 R59 TXDIN13+ 0603, 0 ohm J71 R71 RXCLK1+ J34 J46 J58 R58 TXDIN120603, 0 ohm J70 R70 RXCLK2R33 R45 J33 J45 J57 R57 TXDIN12+ 0603, 0 ohm J69 R69 RXCLK2+ R32 R44 J32 J44 J56 R56 TXDIN110603, 0 ohm J68 R68 Si5530_REFCLKRXDOUT15+ TXDIN5+ R31 R43 R55 TXDIN11+ 0603, 0 ohm J31 J43 J55 J67 R67 Si5530_REFCLK+ RXDOUT14TXDIN4TXDIN100603, 0 ohm R30 R42 R54 J30 J42 J54 J66 R66 RXREFCLK0603, 0 ohm 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm RXDOUT14+ TXDIN4+ TXDIN10+ R29 R41 R53 R65 RXREFCLK+ J29 J41 J53 J65 0603, 0 ohm TXDIN9TXDIN150603, 0 ohm RXDOUT70603, 0 ohm R28 R52 R64 J28 R40 J52 J64 J76 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm SMA R76 TXCLK16INRXDOUT13+ TXDIN3+ TXDIN9+ TXDIN15+ 0603, 0 ohm R27 R39 R51 R63 J27 J39 J51 J63 J75 R75 TXCLK16IN+ 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm RXDOUT12TXDIN2TXDIN8TXDIN14R26 R38 R50 R62 R74 TXCLK16OUTJ26 J38 J50 J62 J74 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm 0603, 0 ohm RXDOUT12+ TXDIN2+ TXDIN8+ TXDIN14+ TXCLK16OUT+ R25 R37 R49 R61 R73 J25 J37 J49 J61 J73
J1
R1
RXDOUT0+
0603, 0 ohm
J2
R2
RXDOUT0-
0603, 0 ohm
J3
R3
RXDOUT1+
0603, 0 ohm
J4
R4
RXDOUT1-
0603, 0 ohm
J5
R5
RXDOUT2+
0603, 0 ohm
Si5100/Si5110-EVB
J6
R6
RXDOUT2-
0603, 0 ohm
J7
R7
RXDOUT3+
0603, 0 ohm
J8
R8
RXDOUT3-
0603, 0 ohm
Preliminary Rev. 0.5
J9
R9
RXDOUT4+
0603, 0 ohm
J10
R10
RXDOUT4-
0603, 0 ohm
J11
R11
RXDOUT5+
0603, 0 ohm
J12
R12
RXDOUT5-
0603, 0 ohm
Figure 16. Full-Duplex Motherboard Schematic (page 1 of 2)
3.3V
JP1 J77A RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3RXREFCLK+ RXREFCLKTXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3Si5530_REFCLK+ Si5530_REFCLKMeg-Array 300 Meg-Array 300 Meg-Array 300 TXCLK16OUT+ TXCLK16OUTTXDIN7+ TXDIN7TXDIN11+ TXDIN11TXDIN15+ TXDIN15TXCLK16IN+ TXCLK16INTXDIN6+ TXDIN6TXDIN10+ TXDIN10TXDIN14+ TXDIN14TXDIN5+ TXDIN5TXDIN9+ TXDIN9TXDIN13+ TXDIN13TXDIN4+ TXDIN4TXDIN8+ TXDIN8TXDIN12+ TXDIN12RXCLK2+ RXCLK2RXCLK1+ RXCLK1RXDOUT7+ RXDOUT7RXDOUT11+ RXDOUT11RXDOUT15+ RXDOUT15RXDOUT6+ RXDOUT6RXDOUT10+ RXDOUT10RXDOUT14+ RXDOUT14RXDOUT5+ RXDOUT5RXDOUT9+ RXDOUT9RXDOUT13+ RXDOUT13RXDOUT4+ RXDOUT4RXDOUT8+ RXDOUT8RXDOUT12+ RXDOUT12J77C J77E J77G
2
RXCLK2DSBL_N
5
RXCLK2DIV_N
8
RXSQLCH_N
11
LTR_N
1 3 4 6 7 9 10 12 13 15
14
RXCLK1DSBL_N
HEADER 5X3
JP2
2
RESET_N
1 3 4 6
5
REFRATE
HEADER 2X3
JP3
2
LPTM
5
LLBK_N
1 3 4 6 7 9
8
DLBK_N
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 Meg-Array 300
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30
HEADER 3X3
JP5 1.8V 3.3V J77B J77D J77F J77H J77I 3.3V J77J
1
2
FIFOERR_N
HEADER 3X2
JP6
1 3
2
FIFORST_N
Placed together to allow jumpering of FIFOERR to FIFORST
HEADER 2X3 RXSQLCH_N LTR_N RXCLK2DIV_N RXLOL_N LOS_N
DLBK_N
JP7
Si5530_RESET_N RXCLK1DSBL_N RXCLK2DSBL_N Si5530_REFRATE
2
Si5530_RESET_N
Preliminary Rev. 0.5
LLBK_N REFRATE LPTM_N Meg-Array 300 TXLOL_N Meg-Array 300 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 Meg-Array 300 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30
1 3 4 6
5
Si5530_REFRATE
HEADER 2X3
JP4
1 3 5
2 4 6
RXLOL_N TXLOL_N LOS_N
RESET_N FIFORST_N FIFOERR_N Meg-Array 300 Meg-Array 300
HEADER 3X2
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 Meg-Array 300
J78
3.3V
1.8V
POS1
1
POS2
2
POS3
3
MKDSN 2,5/3-5,08
Si5100/Si5110-EVB
Figure 17. Full-Duplex Motherboard Schematic (page 2 of 2)
21
Si5100/Si5110-EVB
Bill of Materials: Full-Duplex Motherboard Assembly Revision C-01
Si5100 Motherboard Assy Rev C-01 BOM Reference R1,R2,R3,R4,R5,R6,R7,R8, R9,R10,R11,R12,R13,R14, R15,R16,R17,R18,R19,R20, R21,R22,R23,R24,R25,R26, R27,R28,R29,R30,R31,R32, R33,R34,R35,R36,R37,R38, R39,R40,R41,R42,R43,R44, R45,R46,R47,R48,R49,R50, R51,R52,R53,R54,R55,R56, R57,R58,R59,R60,R61,R62, R63,R64,R65,R66,R67,R68, R69,R70,R71,R72,R73,R74, R75,R76 JP1 JP2,JP4,JP7 JP3 JP5 JP6 J1,J2,J3,J4,J5,J6,J7,J8, J9,J10,J11,J12,J13,J14, J15,J16,J17,J18,J19,J20, J21,J22,J23,J24,J25,J26, J27,J28,J29,J30,J31,J32, J33,J34,J35,J36,J37,J38, J39,J40,J41,J42,J43,J44, J45,J46,J47,J48,J49,J50, J51,J52,J53,J54,J55,J56, J57,J58,J59,J60,J61,J62, J63,J64,J65,J66,J67,J68, J69,J70,J71,J72,J73,J74, J75,J76 J77 J78 PCB Part Desc RES,SM,0,0402 Part Number CR0402-16W-000T Manufacturer VENKEL
CONNECTOR,HEADER,5X3 CONNECTOR,HEADER,3X2 CONNECTOR,HEADER,3X3 CONNECTOR,HEADER,2X1 CONNECTOR,HEADER,3X1 CONNECTOR,SMA,SURFACE MOUNT
2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN 142-0711-201
3M 3M 3M 3M 3M JOHNSON COMPONENTS
CONNECTOR,SM,300 POS,BGA CONNECTOR,POWER,3 POSITION Printed Circuit Board
84500-02 1729021 SI5100-EVB Motherboard PCB Rev C
BERG PHOENIX CONTACT SILICON LABORATORIES
22
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 18. SI5100-EVB Component Side Assembly (Daughter Card)
Figure 19. SI5100-EVB Solder Side Assembly (Daughter Card)
Preliminary Rev. 0.5
23
Si5100/Si5110-EVB
Figure 20. SI5100-EVB Layer 1--Component Side (Daughter Card)
Figure 21. SI5100-EVB Layer 2--GND1 Plane (Daughter Card)
24
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 22. SI5100-EVB Layer 3--Signal Plane (Daughter Card)
Figure 23. SI5100-EVB Layer 4--GND2 Plane (Daughter Card)
Preliminary Rev. 0.5
25
Si5100/Si5110-EVB
Figure 24. SI5100-EVB Layer 5--VDD Plane (Daughter Card)
Figure 25. SI5100-EVB Layer 6--Signal Plane (Daughter Card)
26
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 26. SI5100-EVB Layer 7--GND3 Plane (Daughter Card)
Figure 27. SI5100-EVB Layer 8--Solder Side (Daughter Card)
Preliminary Rev. 0.5
27
Si5100/Si5110-EVB
Figure 28. Si5110-EVB Component Side Assembly (Daughter Card)
Figure 29. Si5110-EVB Solder Side Assembly (Daughter Card)
28
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 30. Si5110-EVB Layer 1--Component Side (Daughter Card)
Figure 31. Si5110-EVB Layer 2--GND1 Plane (Daughter Card)
Preliminary Rev. 0.5
29
Si5100/Si5110-EVB
Figure 32. Si5110-EVB Layer 3--Signal Plane (Daughter Card)
Figure 33. Si5110-EVB Layer 4--GND2 Plane (Daughter Card)
30
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 34. Si5110-EVB Layer 5--VDD Plane (Daughter Card)
Figure 35. Si5110-EVB Layer 6--Signal Plane (Daughter Card)
Preliminary Rev. 0.5
31
Si5100/Si5110-EVB
Figure 36. Si5110-EVB Layer 7--GND3 Plane (Daughter Card)
Figure 37. Si5110-EVB Layer 8--Solder Side (Daughter Card)
32
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 38. Component Side Assembly (Loopback Motherboard)
Preliminary Rev. 0.5
33
Si5100/Si5110-EVB
Figure 39. Layer 1--Component Side (Loopback Motherboard)
34
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 40. Layer 2--GND1 Plane (Loopback Motherboard)
Preliminary Rev. 0.5
35
Si5100/Si5110-EVB
Figure 41. Layer 3--Signal 1 Plane (Loopback Motherboard)
36
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 42. Layer 4--Signal 2 Plane (Loopback Motherboard)
Preliminary Rev. 0.5
37
Si5100/Si5110-EVB
Figure 43. Layer 5--GND2 Plane (Loopback Motherboard)
38
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 44. Layer 6--Solder Side (Loopback Motherboard)
Preliminary Rev. 0.5
39
Si5100/Si5110-EVB
Figure 45. Component Side Assembly (Optional Full-Duplex Motherboard)
40
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 46. Layer 1--Component Side (Optional Full-Duplex Motherboard)
Preliminary Rev. 0.5
41
Si5100/Si5110-EVB
Figure 47. Layer 2--GND1 Plane (Optional Full-Duplex Motherboard)
42
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 48. Layer 3--Signal 1 Plane (Optional Full-Duplex Motherboard)
Preliminary Rev. 0.5
43
Si5100/Si5110-EVB
Figure 49. Layer 4--Signal 2 Plane (Optional Full-Duplex Motherboard)
44
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Figure 50. Layer 5--GND2 Plane (Optional Full-Duplex Motherboard)
Preliminary Rev. 0.5
45
Si5100/Si5110-EVB
Figure 51. Layer 6--Solder Side (Optional Full-Duplex Motherboard)
46
Preliminary Rev. 0.5
Si5100/Si5110-EVB
Document Change List
Revision 0.4 to Revision 0.5
!
Split Table 3 into Tables 3 and 4 to reflect differences in the actual PCBs for the Si5100 and Si5110 devices. ! Updated table references to reflect the changes in Table 3 and the creation of Table 4.
Evaluation Board Assembly Revision History
SI5100-EVB Daughter Card Revision History
Assembly Level C-01 D-01 PCB Rev. B Rev. B Si5600 Device Rev. C Rev. D Assembly Notes Assemble per BOM rev C-01 Assemble per BOM rev D-01
Full-Duplex Motherboard Revision History
Assembly Level A-01 B-01 C-01 PCB Rev. A Rev. B Rev. C Assembly Notes Assemble per BOM rev A-01 Assemble per BOM rev B-01 Assemble per BOM rev C-01
Loopback Motherboard Revision History
Assembly Level A-01 PCB Rev. A Assembly Notes Assemble per BOM rev A-01
Preliminary Rev. 0.5
47
Si5100/Si5110-EVB
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holder
48
Preliminary Rev. 0.5

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