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19-3704; Rev 0; 5/05
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
General Description
The MAX7042 fully integrated, low-power, CMOS superheterodyne RF receiver is designed to receive frequency-shift-keyed (FSK) data at rates up to 66kbps nonreturn-to-zero (NRZ) (33kbps Manchester). The MAX7042 requires only a few external components to realize a complete wireless RF receiver at 308, 315, 418, and 433.92MHz. The MAX7042 includes all the active components required in a superheterodyne receiver including a lownoise amplifier (LNA), an image-rejection (IR) mixer, a fully integrated phase-locked loop (PLL), local oscillator (LO), 10.7MHz IF limiting amplifier with received-signalstrength indicator (RSSI), low-noise FM demodulator, and a 3V regulator. Differential peak-detecting data demodulators are included for baseband data recovery. The MAX7042 is available in a 32-pin thin QFN and is specified over the automotive -40C to +125C temperature range.
Features
+2.4V to +3.6V or +4.5V to +5.5V Single-Supply Operation Four User-Selectable Carrier Frequencies 308, 315, 418, and 433.92MHz -110dBm RF Input Sensitivity at 315MHz -109dBm RF Input Sensitivity at 433.92MHz Fast Startup (<250s) Small 32-Pin Thin QFN Package Low Operating Supply Current 6.2mA Continuous 20nA Power-Down Integrated PLL, VCO, and Loop Filter 45dB Integrated Image Rejection Selectable IF BW with External Filter Positive and Negative Peak Detectors RSSI Output
MAX7042
Ordering Information
PART TEMP RANGE -40C to +125C PIN-PACKAGE 32 Thin QFN-EP* PKG CODE 13255-3
Applications
MAX7042ATJ
Remote Keyless Entry Tire-Pressure Monitoring Home and Office Lighting Control Remote Sensing Smoke Alarms Home Automation Local Telemetry Systems Security Systems
*EP = Exposed pad.
Pin Configuration
PDMAX DGND DVDD OP+ DS+
TOP VIEW
24
N.C. EN FSEL1 FSEL2 HVIN DATA LNASEL N.C.
23
22
21
20
19
18
17 16 15 14 13
IFIN+ IFINAGND MIXOUT MIXINMIXIN+ LNAOUT LNASRC
25 26 27 28 29 30 31 32 1
N.C.
MAX7042
PDMIN
DF
DS-
12 11 10 9
2
N.C.
3
N.C.
4
RSSI
5
XTAL2
6
XTAL1
7
AVDD
8
LNAIN
Typical Application Circuit appears at end of data sheet.
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
ABSOLUTE MAXIMUM RATINGS
HVIN to AGND or DGND .......................................-0.3V to +6.0V AVDD, DVDD to AGND or DGND..........................-0.3V to +4.0V FSEL1, FSEL2, LNASEL, EN, DATA...............................(DGND - 0.3V) to (HVIN + 0.3V) All Other Pins............................(AGND - 0.3V) to (AVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (derate 34.5mW/C above +70C)....2759mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Maximum RF Input Power ................................................+0dBm Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = HVIN = +2.4V to +3.6V, fRF = 308, 315, 418, and 433.92MHz; T A = -40C to +125C, unless otherwise noted. Typical values are at AV DD = DV DD = HV IN = +3.0V, f RF = 433.92MHz, PRFIN -80dBm, TA = +25C, unless otherwise noted.)
PARAMETER Supply Voltage (3V) SYMBOL VDD CONDITIONS HVIN, AVDD, and DVDD connected to power supply HVIN connected to power supply, AVDD and DVDD unconnected from HVIN, but connected together 315MHz (3V) 315MHz (5V) Supply Current IDD 434MHz (3V) 434MHz (5V) All digital inputs low Operating, 1x ILNA Operating, 2x ILNA Operating, 1x ILNA Operating, 2x ILNA Operating, 1x ILNA Operating, 2x ILNA Operating, 1x ILNA Operating, 2x ILNA TA = +25C TA = +85C TA = +125C Shutdown Current (5V) ISHDN All digital inputs low TA = +25C TA = +85C TA = +125C Time from EN = high to final signal detection; does not include baseband filter or dataslicer reference settling MIN 2.4 TYP 3.0 MAX 3.6 UNITS V
Supply Voltage (5V)
HVIN
4.5
5.0 6.2 6.8 6.4 7.0 6.4 7.0 6.6 7.2 0.02 0.1 0.85 0.6 1.4 4
5.5
V
8.7 8.6 8.4 9.2
mA
Shutdown Current (3V)
ISHDN
A 6 A 7
Startup Time
tON
250
s
DIGITAL I/O Input High Threshold Input Low Threshold VIH VIL 0.9 x HVIN 0.1 x HVIN V V
2
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308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = HVIN = +2.4V to +3.6V, fRF = 308, 315, 418, and 433.92MHz; T A = -40C to +125C, unless otherwise noted. Typical values are at AV DD = DV DD = HV IN = +3.0V, f RF = 433.92MHz, PRFIN -80dBm, TA = +25C, unless otherwise noted.)
PARAMETER Input High Pulldown Current Input Low-Leakage Current Output High Voltage Output Low Voltage VOLTAGE REGULATOR Output Voltage VREG 2.5 3.0 3.5 V SYMBOL IIH IIL VOH VOL CONDITIONS HVIN = +3.6V HVIN = +5.5V HVIN = +3.6V HVIN = +5.5V ISOURCE = 500A ISINK = 500A MIN TYP 8 20 <1 <1 HVIN - 0.4 0.4 MAX 15 40 1 1 UNITS A A V V
MAX7042
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = HVIN = +2.4V to +3.6V, fRF = 308, 315, 418, and 433.92MHz; T A = -40C to +125C, unless otherwise noted. Typical values are at AV DD = DV DD = HV IN = +3.0V, f RF = 433.92MHz, PRFIN -80dBm, TA = +25C, unless otherwise noted.)
PARAMETER Maximum Input Level 315MHz setting Sensitivity (Note 1) 434MHz setting Receiver Image Rejection LNA/MIXER Input Impedance (Note 2) 1dB Input Compression Point (Notes 2, 3) Input-Referred 3rd-Order Intercept Point (Notes 2, 3) LO Signal Feedthrough to Antenna Mixer Output Impedance ZoutMIX 1x ILNA 315MHz Voltage Conversion Gain 330 IF filter load (Notes 2, 3) 2x ILNA 315MHz 1x ILNA 433.92MHz 2x ILNA 433.92MHz IF LIMITING AMPLIFIER Input Impedance -3dB Bandwidth Z11 330 10 MHz Z11 P1dB IIP3 Normalized to 2x ILNA 315MHz 50 2x ILNA 433.92MHz 1x ILNA 315MHz 2x ILNA 315MHz 1x ILNA 315MHz 2x ILNA 315MHz 0.94 - j3.2 0.94 - j2.1 -47 -52 -37 -42 -80 330 52 57 47 52 dB dBm dBm dBm Operating, 1x ILNA Operating, 2x ILNA Operating, 1x ILNA Operating, 2x ILNA SYMBOL CONDITIONS MIN TYP 0 -107 -110 -106 -109 45 dB dBm MAX UNITS dBm
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3
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = HVIN = +2.4V to +3.6V, fRF = 308, 315, 418, and 433.92MHz; T A = -40C to +125C, unless otherwise noted. Typical values are at AV DD = DV DD = HV IN = +3.0V, f RF = 433.92MHz, PRFIN -80dBm, TA = +25C, unless otherwise noted.)
PARAMETER Operating Frequency RSSI Slope FSK DEMODULATOR Conversion Gain ANALOG BASEBAND Maximum Peak-Detector Bandwidth Maximum Data-Filter Bandwidth Maximum Data-Slicer Bandwidth Maximum Data Rate CRYSTAL OSCILLATOR Crystal Frequency Crystal Load Capacitance fXTAL (fRF - 10.7) / 32 4.5 MHz pF BWDF BWDS Manchester coded NRZ 50 50 100 33 66 kHz kHz kHz kHz 1.1 2.1 3.0 mV/kHz SYMBOL fIF 10 CONDITIONS MIN TYP 10.7 16 21 MAX UNITS MHz mV/dB
Note 1: 0.2% BER, 4kbps, Manchester coded, 280kHz IF BW, 50kHz frequency deviation. Note 2: Input impedance is measured at the LNAIN pin 2x ILNA. Note that the impedance at 315MHz includes the 3.9nH inductive degeneration from the LNA source to ground. The impedance at 433.92MHz includes a 0nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 47 in series with 3.2pF at 315MHz and 47 in series with 3.5pF at 433.92MHz. Note 3: The voltage conversion gain is measured with the LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not include the IF filter insertion loss.
Typical Operating Characteristics
(Typical Application Circuit, VDD = 3.0V, fRF = 433.92MHz, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2%, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (1x ILNA)
MAX7042 toc01
SUPPLY CURRENT vs. SUPPLY VOLTAGE (2x ILNA)
MAX7042 toc02
SUPPLY CURRENT vs. RF FREQUENCY (1x ILNA)
MAX7042 toc03
7.2 7.0 SUPPLY CURRENT (mA) 6.8 6.6 6.4 6.2 6.0 5.8 5.6 5.4 2.4 2.7 3.0 3.3 -40C +25C +85C +125C
8.0 7.8 7.6 SUPPLY CURRENT (mA) 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 -40C 2.4 2.7 3.0 3.3 +25C +85C +125C
7.0 6.8 SUPPLY CURRENT (mA) 6.6 6.4 6.2 6.0 5.8 5.6 -40C +125C +85C +25C
3.6
3.6
300
325
350
375
400
425
450
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
RF FREQUENCY (MHz)
4
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308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
Typical Operating Characteristics (continued)
(Typical Application Circuit, VDD = 3.0V, fRF = 433.92MHz, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2%, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. RF FREQUENCY (2x ILNA)
+125C +85C +25C
MAX7042 toc04
MAX7042
DEEP-SLEEP CURRENT vs. TEMPERATURE
MAX7042 toc05
BIT-ERROR RATE vs. AVERAGE INPUT POWER (1x ILNA)
MAX7042 toc06
7.5 7.3 SUPPLY CURRENT (mA) 7.1 6.9 6.7 6.5 6.3 6.1 300 325 350 375 400 425 -40C
1000
100 fRF = 433.92MHz 10 BIT-ERROR RATE
DEEP-SLEEP CURRENT (nA)
800
600 VCC = +3.6V 400 VCC = +3.0V VCC = +2.4V
1 0.2% BER 0.1 fRF = 315MHz 0.01
200
0 450 -40 -15 10 35 60 85 110 RF FREQUENCY (MHz) TEMPERATURE (C)
-114
-112
-110
-108
-106
-104
AVERAGE INPUT POWER (dBm)
BIT-ERROR RATE vs. AVERAGE INPUT POWER (2x ILNA)
MAX7042 toc07
SENSITIVITY vs. TEMPERATURE (1x ILNA)
MAX7042 toc08
SENSITIVITY vs. TEMPERATURE (2x ILNA)
MAX7042 toc09
100 fRF = 433.92MHz 10
-103 -104 SENSITIVITY (dBm) -105 -106 fRF = 433.92MHz -107 -108 -109
-106 -107 SENSITIVITY (dBm) -108 -109 fRF = 433.92MHz -110 -111 -112
BIT-ERROR RATE
1 0.2% BER 0.1 fRF = 315MHz 0.01 -117 -115 -113 -111 -109 -107 AVERAGE INPUT POWER (dBm)
fRF = 315MHz -40 -15 10 35 60 85 110
fRF = 315MHz -40 -15 10 35 60 85 110
TEMPERATURE (C)
TEMPERATURE (C)
SENSITIVITY vs. FREQUENCY DEVIATION
FREQUENCY DEVIATION IS MEASURED FROM 0 TO PEAK
MAX7042 toc10
RSSI AND DELTA vs. IF INPUT POWER
1.8 1.5 1.2 RSSI (V) 0.9 0.6 DELTA 0.3 0 RSSI
MAX7042 toc11
FSK DEMODULATOR OUTPUT vs. IF FREQUENCY
MAX7042 toc12
-100 -102 SENSITIVITY (dBm) -104 -106 -108 -110 -112 1
3 FSK DEMODULATION OUTPUT (V) 2 1 DELTA (%) 0 -1 -2 -3
2.0
1.6
1.2
0.8
0.4
0 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0 IF FREQUENCY (MHz)
10 FREQUENCY DEVIATION (kHz)
100
-90
-70
-50
-30
-10
10
RF INPUT POWER (dBm)
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5
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
Typical Operating Characteristics (continued)
(Typical Application Circuit, VDD = 3.0V, fRF = 433.92MHz, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2%, TA = +25C, unless otherwise noted.)
SYSTEM GAIN vs. IF FREQUENCY (1x ILNA)
MAX7042 toc13
SYSTEM GAIN vs. IF FREQUENCY (2x ILNA)
MAX7042 toc14
IMAGE REJECTION vs. TEMPERATURE (1x ILNA)
MAX7042 toc15
50 40 SYSTEM GAIN (dB) 30 20 10 0 -10 0 5 10 15 20 25 45dB IMAGE REJECTION UPPER SIDEBAND FROM RFIN TO MIXOUT fRF = 433.92MHz
60 UPPER SIDEBAND 50 SYSTEM GAIN (dB) 40 30 20 10 0 -10 LOWER SIDEBAND 45dB IMAGE REJECTION FROM RFIN TO MIXOUT fRF = 433.92MHz
60 50 IMAGE REJECTION (dB) 40 30 20 10 0 fRF = 433.92MHz fRF = 315MHz
LOWER SIDEBAND
30
0
5
10
15
20
25
30
-40
-15
10
35
60
85
110
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
TEMPERATURE (C)
IMAGE REJECTION vs. TEMPERATURE (2x ILNA)
MAX7042 toc16
NORMALIZED IF GAIN vs. IF FREQUENCY
MAX7042 toc17
60 50 IMAGE REJECTION (dB) 40 30 20 10 0 -40 -15 10 35 60 85 110 TEMPERATURE (C) fRF = 433.92MHz fRF = 315MHz
0 -3 NORMALIZED IF GAIN (dB) -6 -9 -12 -15 -18 1 10 IF FREQUENCY (MHz)
100
S11 vs. RF FREQUENCY
MAX7042 toc18
0
-4 S11 (dB)
-8 433.92MHz -12
-16 100 250 400 550 700 850 1000 RF FREQUENCY (MHz)
6
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308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
Typical Operating Characteristics (continued)
(Typical Application Circuit, VDD = 3.0V, fRF = 433.92MHz, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2%, TA = +25C, unless otherwise noted.)
INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION
MAX7042 toc19
MAX7042
S11 SMITH PLOT OF RFIN
70
MAX7042 toc20
-150
fRF = 315MHz IMAGINARY IMPEDANCE () 60 REAL IMPEDANCE () -160
50
-170
433.92MHz
40
REAL IMPEDANCE IMAGINARY IMPEDANCE 1 10 INDUCTIVE DEGENERATION (nH) 100
-180
30
-190
20
-200
INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION
90 80 70 60 50 40 30 20 1 10 INDUCTIVE DEGENERATION (nH) 100 -140 REAL IMPEDANCE -130 IMAGINARY IMPEDANCE -120 PHASE NOISE (dBc/Hz) REAL IMPEDANCE () -110 IMAGINARY IMPEDANCE ()
MAX7042 toc21
PHASE NOISE vs. OFFSET FREQUENCY
fRF = 315MHz -80 fRF = 433.92MHz -90 -100 -110 -120 -130 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz)
MAX7042 toc22
fRF = 433.92MHz
-100
-70
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7
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
Pin Description
PIN 1, 2 3, 25, 32 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 EP NAME N.C. N.C. RSSI XTAL2 XTAL1 AVDD LNAIN LNASRC LNAOUT MIXIN+ MIXINMIXOUT AGND IFINIFIN+ PDMIN PDMAX DSDS+ OP+ DF DGND DVDD EN FSEL1 FSEL2 HVIN DATA LNASEL GND No Connection. Internally pulled down. No Connection. Not internally connected. Buffered Received-Signal-Strength-Indicator Output Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference. Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference. Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in +5V operation. Bypass AVDD to GND with 0.1F and 220pF capacitors placed as close to the pin as possible. Low-Noise Amplifier Input. Must be AC-coupled. Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set the LNA input impedance. Low-Noise Amplifier Output. Connect to AVDD through a parallel LC tank filter. AC-couple to MIXIN+. Noninverting Mixer Input. Must be AC-coupled to the LNA output. Inverting Mixer Input. Bypass to AVDD or AGND with a capacitor. 330 Mixer Output. Connect to the input of the 10.7MHz IF filter. Analog Ground Inverting 330 IF Limiter Amplifier Input. Bypass to AGND with a capacitor. Noninverting 330 IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter. Minimum-Level Peak Detector for Demodulator Output Maximum-Level Peak Detector for Demodulator Output Inverting Data-Slicer Input Noninverting Data-Slicer Input Noninverting Op-Amp Input for the Sallen-Key Data Filter Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. Digital Ground Digital Power-Supply Voltage. Bypass to DGND with 0.01F and 220pF capacitors placed as close to the pin as possible. Enable. Internally pulled down. Drive high for normal operation. Drive low or leave unconnected to put the device into shutdown mode. Frequency-Select Pin 1 (see Table 1). Internally pulled down. Connect to EN for logic-high operation. Frequency-Select Pin 2 (see Table 1). Internally pulled down. Connect to EN for logic-high operation. High-Voltage Supply Input. For +3V operation, connect HVIN to AVDD and DVDD. For +5V operation, connect only HVIN to +5V. Bypass HVIN to AGND with 0.01F and 220pF capacitors placed as close to the pin as possible. Receiver Data Output LNA Bias Current Select Pin. Internally pulled down. Set LNASEL to logic-low for low LNA current and set LNASEL to logic-high for high LNA current. Connect to EN for logic-high operation. Exposed Paddle. Connect to ground. FUNCTION
8
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308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
Functional Diagram
MAX7042
LNAOUT
MIXIN+
MIXIN-
MIXOUT IFIN-
IFIN+
10
11
12
IMAGE REJECTION
13
15
16
IF LIMITING AMPS
LNAIN
8
LNA
0
LNASRC
9
90
RSSI
AGND 14 XTAL1
4
RSSI
CRYSTAL OSCILLATOR
6
DIVIDEBY-32
VCO FSK FSK DEMODULATOR
XTAL2
5
PHASE DETECTOR LOOP FILTER RDF1 100k
27 FSEL1
EN 26 RDF2 100k DVDD 24 EXPOSED PADDLE*
MAX7042
FSK DATA FILTER
28 FSEL2
DGND 23
HVIN 29
3.0V REG
31 LNASEL
AVDD
7
3.0V
30
DATA
19
DS-
18
PDMAX
17
PDMIN
20
DS+
21
OP+
22
DF
*MUST BE CONNECTED TO AGND.
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9
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
Detailed Description
The MAX7042 CMOS superheterodyne receiver and a few external components provide a complete FSK receive chain from the antenna to the digital output data. FSK uses the difference in frequency of the carrier to represent a logic 0 and logic 1. Depending on signal power and component selection, data rates as high as 66kbps NRZ can be achieved. impedance such as a PC board trace antenna. A nominal value of this inductor for a 50 input impedance is 3.9nH at 315MHz and 0nH (short) at 433.92MHz, but is affected by the PC board trace. See the Typical Operating Characteristics for the relationship between the inductance and input impedance. The LC tank filter connected to LNAOUT consists of L2 and C9 (see the Typical Application Circuit). Select L2 and C9 to resonate at the desired RF input frequency. The resonant frequency is given by: f= 1 2 LTOTAL x CTOTAL
Frequency Selection
The MAX7042 can be tuned to one of four frequencies using the 2 frequency-select bits FSEL1 and FSEL2: 308, 315, 418, and 433.92MHz, as shown in Table 1. The LO frequencies are 32 times the reference crystal frequencies of 9.29063, 9.50939, 12.72813, and 13.22563MHz. The selected crystal frequency is used to calibrate the FSK detector PLL so that it operates at the middle of the 10.7MHz IF.
Table 1. Frequency Selection Table
FSEL2 0 0 1 1 FSEL1 0 1 0 1 FREQUENCY (MHz) 308 315 418 433.92
where LTOTAL = L2 + LPARASITICS and CTOTAL = C9 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PC board traces, package pins, mixer input impedance, LNA output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation is required to optimize the center frequency of the tank. The parasitic capacitance is generally 5pF to 7pF. There are two ways to verify experimentally that the resonant frequency of the tank is centered at the desired RF frequency: 1) Drive the crystal oscillator externally and sweep both the RF frequency and the LO frequency (FXTAL x 32) to keep the IF at 10.7MHz while monitoring the RSSI voltage (pin 4). There is a peak in the RSSI voltage at resonance. The external source must be AC-coupled into XTAL1 and the XTAL2 pin must have an AC bypass to ground. The recommended drive power is -10dBm. 2) Use a network analyzer to measure the resonance. The port 1 power from the network analyzer is input to the receiver, and this power must be -30dBm or less. A coaxial stub with the center conductor exposed (commonly called an RF "sniffer" is used to monitor the tank power and serves as the port 2 input to the network analyzer. The sniffer should be placed in close proximity to, but not actually touching, the tank inductor.
Low-Noise Amplifier (LNA)
The LNA is a cascode amplifier with off-chip inductive degeneration. The gain and the noise figure are dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer input. The MAX7042 allows for user programmability of the LNA bias current. Input LNASEL programs 1x to 2x bias currents in increments of 0.6mA from 0.6mA to 1.2mA. Setting LNASEL to logic-low programs the LNA to consume 1x bias current and setting LNASEL to logic-high programs the LNA to consume 2x bias current. Larger bias currents yield better sensitivity and gain at the expense of current drain. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible match to a low-input
10
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308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
TO FSK BASEBAND FILTER AND DATA SLICER IF LIMITING AMPS PHASE DETECTOR CHARGE PUMP LOOP FILTER 10.7MHz VCO 2.1mV/kHz
Figure 1. FSK Demodulator PLL Block Diagram
Mixer
A unique feature of the MAX7042 is the integrated image rejection of the mixer. This device is designed to eliminate the need for a costly front-end SAW filter in many applications. The advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double-balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz intermediate frequency (IF) with low-side injection (i.e., fLO = fRF - fIF). The image-rejection circuit then combines these signals to achieve a typical image rejection of approximately 45dB. Low-side injection is required as high-side injection is not possible due to the on-chip image rejection. The IF output is driven by a source follower, biased to create a driving impedance of 330 to interface with an off-chip 330 ceramic IF filter. Note that MIXIN+ and MIXIN- are functionally identical.
Intermediate Frequency (IF)
The IF section presents a differential 330 load to provide matching for the off-chip ceramic filter. The internal six AC-coupled limiting amplifiers produce an overall gain of approximately 65dB. The limiting amplifiers have a bandpass-filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. The limiter output is fed into a PLL to demodulate the IF, producing a baseband voltage with a demodulation slope of 2.1mV/kHz. The RSSI circuit produces a DC output proportional to the log of the IF signal level with a slope of approximately 16mV/dB.
FSK Demodulator
The FSK demodulator uses an integrated 10.7MHz PLL that tracks the input RF modulation and determines the difference between frequencies as logic ones and zeros. The PLL is illustrated in Figure 1. The input to the PLL comes from the output of the IF limiting amplifiers. The PLL control voltage responds to changes in the frequency of the input signal with a nominal gain of 2.1mV/kHz. For example, an FSK peak-to-peak deviation of 50kHz generates a 105mVP-P signal on the control line. This control line is then filtered and sliced by the FSK baseband circuitry. The FSK demodulator PLL requires calibration to overcome variations in process, voltage, and temperature. The maximum calibration time is 120s, which is included in the startup time. Recalibration is necessary after a significant change in temperature or supply voltage. Calibration occurs automatically each time the MAX7042 is powered up. Drive EN low and then high to force a recalibration.
Phase-Locked Loop (PLL)
The PLL block contains a phase detector, charge pump/integrated loop filter, voltage-controlled oscillator (VCO), asynchronous 32x frequency divider, and crystal oscillator. This PLL does not require any external components. The relationship between the RF, IF, and reference frequencies is given by: fREF = (fRF - fIF) 32
To allow the smallest possible IF bandwidth (for best sensitivity), minimize the tolerance of the reference.
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11
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
Crystal Oscillator
The XTAL oscillator in the MAX7042 is used to generate the LO for mixing with the received signal. The XTAL oscillator frequency sets the received signal frequency as: fRECEIVE = (fXTAL x 32) + 10.7MHz The received image frequency at: fIMAGE = (fXTAL x 32) - 10.7MHz is suppressed by the integrated quadrature imagerejection circuitry. The XTAL oscillator in the MAX7042 is designed to present a capacitance of approximately 3pF between XTAL1 and XTAL2. In most cases, this corresponds to a 4.5pF load capacitance applied to the external crystal when typical PC board parasitics are added. It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7042 crystal oscillator plus PC board parasitics. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its intended operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. In reality, the oscillator pulls every crystal. A crystal's natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: fp = 1 1 Cm - x 106 C 2 case + Cload Ccase + Cspec
Frequency Tolerance
The frequency tolerance of the crystal, the frequency and bandwidth tolerance of the IF filter, and the desired modulation bandwidth of the signal are all interrelated. The combination of these characteristics should be such to ensure that the modulated signal bandwidth stays within the passband of the IF filter after downconversion. As is shown below, a 50ppm tolerance crystal in combination with a 280kHz bandwidth IF filter is sufficient for most FSK-modulated signals. Smaller IF filter bandwidths can be used if high-tolerance crystals are used for generating both transmitter and MAX7042 receiver PLL references. The modulated spectrum of the transmitted signal must be downconverted by the MAX7042 to fall within the passband of the IF filter. The crystal tolerances must take into account the initial +25C tolerance, aging, load capacitance tolerances, and temperature drift for both the transmitter and MAX7042 receiver. To achieve acceptable signal reception, the following equation must hold: 2 x (FTX + FRX + FIF + FDEV + 5 x FMOD) < IFBWmin where: FTX = (transmitter crystal tolerance in ppm) x (carrier frequency in MHz). This includes aging, load capacitance, and temperature effects for the crystal tolerance. FRX = (MAX7042 crystal tolerance in ppm) x (carrier frequency in MHz). This includes aging, load capacitance, and temperature effects for the crystal tolerance. FIF = The center frequency tolerance of the selected IF filter. This includes temperature drift of the IF filter center frequency. FDEV = FSK frequency deviation from carrier frequency. FMOD = One half of NRZ data rate, or the data rate if Manchester coding is used. IFBWmin = The minimum bandwidth of the selected IF filter. As an example, assume 315MHz carrier frequency, 50ppm crystal tolerances for both transmitter and MAX7042, 30kHz IF filter center frequency tolerance, 50kHz frequency deviation, and 4.8kHz Manchester data rate: 2 x [(315 x 50) + (315 x 50) + 30000 +50000 + 5 x 4800] = 271kHz < IFBWmin This operating condition necessitates a 280kHz IF filter.
where: fp is the amount the crystal frequency is pulled in ppm. Cm is the motional capacitance of the crystal. Ccase is the case capacitance. Cspec is the specified load capacitance. Cload is the actual load capacitance. When the crystal is loaded as specified, i.e., Cload = Cspec, the frequency pulling equals zero.
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308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
Data Filters
The data filter is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency in kHz should be to approximately the fastest expected data rate in kbps for NRZ and twice the fastest expected data rate in kbps for Manchester coding from the transmitter. Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 2 creates a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of the capacitors, use the following equations along with the coefficients in Table 2: b a(100k)()(fC) a CF2 = 4(100k)()(fC) CF1 = where fC is the desired 3dB corner frequency. For example, choose a Butterworth filter response with a 5kHz corner frequency: CF1 = 1.000 450pF (1.414)(100k)(3.14)(5kHz) 1.414 CF2 = 225pF (4)(100k)(3.14)(5kHz)
DS+ CF2
Table 2. Coefficients to Calculate CF1 and CF2
FILTER TYPE Butterworth (Q = 0.707) Bessel (Q = 0.577) a 1.414 1.3617 b 1.000 0.618
MAX7042
MAX7042 FSK DEMOD
100k
100k
OP+ CF1
DF
Figure 2. Sallen-Key Lowpass Data Filter
Data Slicer
The purpose of a data slicer is to take the analog output of a data filter and convert it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. The threshold voltage is set by the voltage on the DS- pin, which is connected to the negative input of the data-slicer comparator. The positive input of the data-slicer comparator is connected to the output of the data filter internally.
Choosing standard capacitor values changes CF1 to 470pF and CF2 to 220pF. In the Typical Application Circuit, CF1 and CF2 are named C4 and C3, respectively.
______________________________________________________________________________________
13
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
Numerous configurations can be used to generate the data-slicer threshold. For example, the circuit in Figure 3 shows a simple method using only one resistor and one capacitor. This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R and C affect how fast the threshold tracks the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate. With this configuration, a long string of zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. Figure 4 shows a configuration that uses the positive and negative peak detectors to generate the threshold. This configuration sets the threshold to the midpoint between a high output and a low output of the data filter.
MAX7042
MAX7042 DATA SLICER
DATA
DSR C
DS+
Figure 3. Generating Data-Slicer Threshold
Peak Detectors
The maximum peak detector (PDMAX) and minimum peak detector (PDMIN) outputs, in conjunction with a resistor and capacitor connected to GND, create DC output voltages proportional to the high- and low-peak values of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output voltage. The positive and negative peak detectors can be used together to form a data-slicer threshold voltage at a midvalue between the most positive and most negative voltage levels of the data stream (see the Data Slicers section and Figure 4). Set the RC time constant of the peak-detector combining network to at least 5 times the data period. The MAX7042 peak detectors track the baseband filter output voltage until all internal circuits are stable following an enable pin low-to-high transition. This feature allows for an extremely fast startup because the peak detectors never "catch" a false level created by a startup transient. The peak detectors exhibit a fast-attack/slowdecay response.
MAX7042
DATA SLICER
PEAK DET
PEAK DET
DATA
PDMAX R C R
PDMIN
C
Figure 4. Generating Data-Slicer Threshold Using the Peak Detectors
chip linear regulator that reduces the 5V supply to 3V needed to operate the chip. To operate the MAX7042 from a 3V supply, connect DVDD, AVDD, and HVIN to the 3V supply. When using a 5V supply, connect the supply to HVIN only. In both cases, bypass DVDD and HVIN with a 0.01F capacitor and AV DD with a 0.1F capacitor. Place all bypass capacitors as close to the respective supply pin as possible.
Power-Supply Connections
The MAX7042 can be powered from a 2.4V to 3.6V supply or a 4.5V to 5.5V supply. The device has an on-
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308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
Layout Considerations
A properly designed PC board is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of /10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PC board trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capacitors close to all VDD or HVIN connections.
MAX7042
Typical Application Circuit
LNASEL VDD 3.0V VDD DATA FSEL2 FSEL1 EN
C16 31
LNASEL
30
DATA
29
HVIN
28
FSEL2
27
FSEL1
26
EN
VDD
DVDD DGND
C14
4 5
RSSI XTAL2
24 23 22 21 C3 C4 R1 C5 C1 C2
Y1
VDD
C15 6
XTAL1 DF MAX7042 OP+
7 C6 C13
AVDD DS+ DS-
20 19 18 17
C7 RF INPUT
L1
8
LNAIN
EXPOSED PADDLE LNAOUT MIXIN+ MIXOUT AGND MIXIN-
PDMAX PDMIN
LNASRC
9 10
11 C11
12 C8 C9
VDD
13 14 C12
15 16
L3
L2 C10
IN
GND Y2
OUT
______________________________________________________________________________________
IFIN+
IFIN-
15
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
Table 3. Component Values for Typical Application Circuit
COMPONENT C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 L1 L2 L3 R1 Y1 Y2 VALUE FOR 315MHz RF 0.01F 220pF 220pF 470pF 0.047F 0.1F 100pF 100pF 1.2pF 220pF 100pF 1500pF 220pF 100pF 100pF 0.1F 82nH 30nH 3.9nH 100k 9.50939MHz 10.7MHz ceramic filter VALUE FOR 433.92MHz RF 0.01F 220pF 220pF 470pF 0.047F 0.1F 100pF 100pF Open 220pF 100pF 1500pF 220pF 100pF 100pF 0.1F 39nH 16nH Short 100k 13.22563MHz 10.7MHz ceramic filter DESCRIPTION 5% 5% 5% 5% 10% 10% 10% 10% 0.1pF 10% 10% 10% 10% 10% 10% 10% Coilcraft 0603CS Murata LQW18A Coilcraft 0603CS 5% Crystal Murata SFECV10.7 series
Chip Information
PROCESS: CMOS
16
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308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX7042
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
XXXXX
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
1
2
______________________________________________________________________________________
QFN THIN.EPS
17
308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 T4055-1
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
A A1 A3 b D E e k L L1 N ND NE JEDEC
NOTES:
DOWN BONDS ALLOWED
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.25 0.30 0.35 4.90 5.00 5.10 4.90 5.00 5.10 0.65 BSC. 0.25 0 0.02 0.05 0.20 REF. 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 0.50 BSC. 0.25 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 0.40 BSC. 0.25 0.35 0.45 0.20 REF. 0.25 0.30 0.35 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.25 0.20 REF. 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 0.50 BSC. 0.25 -
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.20
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** ** **
NO YES NO NO YES NO YES NO NO YES YES NO NO YES YES NO NO YES NO NO YES
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 40 10 10 -----
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3, AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
3.30 3.40 3.20
** SEE COMMON DIMENSIONS TABLE
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
H
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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