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For Communications Equipment
MN6155
PLL LSI with Built-In Prescaler
Overview
The MN6155 is a CMOS LSI for a phase-locked loop (PLL) frequency synthesizer with serial data parameter input. It consists of a two-coefficient prescaler, variable frequency divider, phase comparator, and charge pump. It offers high-speed operation on a low power supply voltage (1.0 to 1.4 V) and low power consumption (1.65 mW for VDD=1.1 V, F IN= RIN =90 MHz). Other features include intermittent operation by the power save (PS) control signal and high-speed pull-in that rapidly corrects the phase differences occurring at the start of operation. It also offers two choices for the reference signal: selfexcited operation using the built-in inverter amplifier or use of an external, separately excited oscillator.
Pin Assignment
XIN XOUT FV VDD DOP VSS VCP FIN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
RIN RSL LC FR PS LE DATA CLK
(TOP VIEW) SSOP016-P-0225
Features
Low power supply voltage: VDD=1.0 to 1.4V Low power consumption: 1.65mW(VDD=1.10V, FIN =90MHz, RIN =90MHz) High-speed operation: FIN=90MHz, R IN=90MHz (VDD=1.1V) Frequency dividing ratios in reference frequency dividing stage 6 to 131,070 for RSL at "H" level (even number setting is available) 272 to 131,071 for RSL at "L" level Frequency dividing ratios for comparator stage: 272 to 262,143 Power supply pin for built-in charge pump VCP=2.5 to 3.2V Output monitor pins for both comparator and reference frequency dividing stages
MN6155
Block Diagram
RSL
15 4 6 13 FR Prescaler and phase adjustment Switching circuit Prescaler
Phase adjustment
VDD VSS
RIN
16 13-bit programmable counter
Swallow counter
XIN 3-bit counter
1
XOUT 17-bit latch
2 7 5
CLK Data control 18-bit shift register
9
VCP DOP
Phase comparator
DATA 18-bit latch
10
LE
11
PS
12
Control
14
LC 3
For Communications Equipment
FIN
8
Prescaler and phase adjustment Swallow counter
14-bit programmable counter
FV
For Communications Equipment
Pin Descriptions
Pin No. 1 2 Symbol XIN XOUT Function Description Crystal oscillator connection pins: XIN =Oscillator circuit input pin;
MN6155
(XIN is attached to a pull-up resistor when the PS or RSL pin is at "L" level.) XOUT=Oscillator circuit output pin. 3 4 5 6 7 8 9 10 FV V DD D OP V SS VCP FIN CLK DATA Frequency divider output signal in comparator stage. Phase comparator input monitor. Power supply Low-pass filter connection pin. Use a passive filter. Ground Power supply pin for built-in charge pump Frequency divider input pin in comparator stage. Shift register clock input pin. The chip latches data at the rising edge of the CLK signal. Shift register data input pin. The final two bits in the data select the write latch: "11" for R-latch; "01" for N-latch. 11 12 LE PS Load enable signal input pin. This is the latch-write-enable signal. It is at "H" level for write. Power save control signal input pin. "H" level input starts the frequency divider and places the chip in operational mode. "L" level input places the chip in standby mode, which saves power. The chip switches the internal charge pump output to the H-z state and the loop is opened. 13 14 FR LC Reference frequency divider output signal. Phase comparator input monitor. Charge pump control signal output pin. When frequency divider operation is stopped, this pin is at "L" level, the internal charge pump output is in the high-impedance state, and the loop is opened. 15 RSL Reference signal selection pin. "H" level selects self-excited oscillator (XIN and XOUT). "L" level selects external oscillator (RIN). 16 RIN External reference oscillation input pin. This pin is attached to a pull-up resistor when the PS pin is at "L" level or the RSL pin is at "H" level.
MN6155
MN6155 Frequency Dividing Data Settings
1) Comparator side frequency dividing data FV = FIN / {(16 x N) + A}
For Communications Equipment
2)
Reference side frequency dividing data a) Low-speed operation (RSL pin at "H" level, using XIN ) FR = XIN / R b) High-speed operation (RSL pin at "L" level, using RIN ) FR =RIN / {(16 x NR) + AR} where FIN : Comparator side frequency RIN : High-speed reference frequency XIN : Low-speed reference oscillator frequency FV : Comparator frequency divider stage output frequency FR : Reference frequency divider stage output frequency N : Setting for 14-bit programmable counter on comparator side A : Setting for 4-bit swallow counter on comparator side R : Setting for 17-bit programmable counter on low-speed reference side NR : Setting for 13-bit programmable counter on high-speed reference side AR : Setting for 4-bit swallow counter on low-speed reference side (Note that N should be greater than A; NR, greater than AR.) N-Side Latch Data
MSB
14 bits Programmable counter setting (N)
4 bits Swallow counter setting (A)
LSB
R-Side Latch Data Low-speed operation MSB 17 bits Programmable counter setting (N) LSB
High-speed operation MSB 13 bits Programmable counter setting (NR)
4 bits Swallow counter setting (AR)
LSB
For Communications Equipment
Note on Setting Frequency Dividing Data Input
1) Frequency dividing data input (1) Reference side
Data input direction MSB 17-bit frequency dividing data LSB 1 bit 1 bit Control bits
MN6155
"L"
Frequencey Write selection dividing stage "H" level selection "H" level 1 CLK 2 17 18 19
DATA MSB LE LSB
(2) Comparating side
Data input direction *1 3-bit test data 3 bits "L" level 18-bit frequency dividing data 1 bit 1 bit "L" Control bits
1 CLK
2
3
4
5
Frequencey Write selection dividing stage "H" level selection "L" level 21 22 23
DATA MSB LE
Notes
LSB
1.*1: Preceding the input of the frequency dividing data for the comparating side, input test pattern consisting
of three "L" level bits to produce normal operation. Never use any other pattern.
2. When the power is first applied, internal operation remains in an unstable state until data is written. To
eliminate the risk of excessive current consumption, keep the PS pin at "L" level.
3. When the power is first applied, the data settings are indeterminate. Always write data to the chip before
starting operation.
4. Enter the data to fill the entire latch:
Reference side: 19 bits (17 bits for the frequency divider setting and 2 for control bits) Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2 for control bits) Drive the LE pin at "L" level while writing the data. "H" level input from the LE pin causes the chip to read the data only when the CLK pin and the DATA pin are both at "L" level. Writes are possible when the PS pin is either "H" or "L" level. Input the data MSB first. The data are inputted at the rising edge of the CLK signal.
5. 6. 7. 8. 9.
MN6155
Absolute Maximum Ratings
Parameter Power supply voltage Power supply voltage Input pin voltage Output pin voltage Power dissipation Operating ambient temperature Storage temperature Symbol VDD VCP VI VO PD Topr Tstg
For Communications Equipment
Rating - 0.3 to +3.0 - 0.3 to +4.0 VSS - 0.3 to VDD +0.3 VSS - 0.3 to VDD +0.3 20 -10 to +60 -55 to +125
Unit
V
mW C
Operating Conditions
VSS=0V, Ta=-10 to +60C
Parameter Power supply voltage Power supply voltage
Symbol VDD VCP
Test Conditions
min 1.0 2.5
typ 1.1 3.0
max 1.4 3.2
Unit V V
Electric Characteristics
VCP=2.5V, Ta=-10 to +60C
Parameter Power supply pin Power supply current
Symbol VDD IDD IDstop
Test Conditions VDD =1.1V FIN =90MHz, RIN=90MHz, PS="H", RSL="L" PS="L" (Power Save operation)
min
typ
max 2.3 3
Unit mA A
Input Pins CLK, DATA, LE, and PS VDD =1.0 to 1.4 V "H" level input voltage "L" level input voltage Input leakage current Input Pins FIN , RIN Input voltage Input current Input leakage current Maximum operating frequency Minimum operating frequency VIH VIL ILI
VDD =1.0 to 1.4V
VDD - 0.2 VSS
VDD 0.2 1.0
V A Vp-p A
VIN IIF ILIF FINMAX RINMAX FINMIN RINMIN Pull-up resistor is present (PS="L") VIN =0 or VDD (PS="H") VIN =0.4 Vp-p VIN =0.4 Vp-p
0.4 -10 20 90 1.0
A MHz MHz
Input Pin X IN VDD=1.0 to 1.4V Input voltage Input current Input leakage current Maximum operating frequency VIN IIX ILIX XINMAX Pull-up resistor is present (PS="L") VIN =0 or VDD VIN =0.4 Vp-p 15 0.4 - 0.1 -1.5 5.0 Vp-p mA A MHz
For Communications Equipment
Electrical Characteristics (continued)
VCP=2.5V, Ta=-10 to +60C
MN6155
Parameter Symbol Test Conditions Crystal Oscillator Pins X IN, XOUT VDD =1.0 to 1.4V Crystal oscillator frequency Output Pins FV, FR, LC "H" level output voltage "L" level output voltage Output Pin XOUT "H" level output voltage "L" level output voltage Output Pin DOP "H" level output voltage "L" level output voltage Output leakage current Output leakage current Setup time *1 Hold time *1 fXtal
VDD=1.0 to 1.4V
min 15
typ
max
Unit MHz
VOH VOL
VDD =1.0 to 1.4V
I OH= -10A I OL=10A IXOH= -100A I XOL=100A VDop=V CP - 0.3V VDop=0.3V VDop=V CP VDop=0.0V
VDD- 0.3 VSS VDD- 0.3 VSS -100 -100
VDD 0.3 VDD 0.3
V
VXOH VXOL
VDD =1.0 to 1.4V
V
IDOH IDOL ILOH I LOL
VDD =1.0 to 1.4V
A 2.0 -2.0
tsul tsu2 tH
500 500 500
ns ns ns
Note*1: The following timing chart shows the setup and hold times.
DATA
50% tsu1 tH
CLK tsu2 LE
Usage Note
Be particularly careful with this product as it is more sensitive on the static electricity damage than most of our other products.
MN6155
MN6155
1 XIN
excited oscillator
RIN RSL LC 13 FR 12 PS LE DATA CLK 11 10 9 Intermittent operation control 14 15
16 Separately
2 XOUT FV 4 VDD DOP VSS VCP FIN 10k 0.1F 5 6 0.1F 1F 8 VCP=3V 1000pF 7 100 3 VDD=1.0V to 1.4V
Application Circuit Example
0.22F
35k
Frequency dividing data input Frequency dividing data input Frequency dividing data input
*1 Loop filter
VF VCO 80 to 90MHz
Amplifier
390 VCC 10F VCC=3V
For Communications Equipment
*1 VCO characteristics may necessitate design revisions.
For Communications Equipment
Package Dimensions (Unit: mm)
SSOP016-P-0225
MN6155
6.50.2 16 9
1.00.1 4.30.2 6.30.2
0.15 -0.05
+0.10
0 to 10 0.50.1 (0.45) 1.450.20 0.10.1 SEATING PLANE 1.550.30 1 8
0.8 0.15
0.350.10

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