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Philips Semiconductors
Product specification
PowerMOS transistor Voltage clamped logic level FET
GENERAL DESCRIPTION
Protected N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in automotive applications. It has built-in zener diodes providing active drain voltage clamping.
BUK563-48C
QUICK REFERENCE DATA
SYMBOL V(CL)DSR ID Ptot Tj WDSRR RDS(ON) PARAMETER Drain-source clamp voltage Drain current (DC) Total power dissipation Junction temperature Repetitive clamped turn off energy; Tj = 150C Drain-source on-state resistance; VGS = 5 V MIN. 40 TYP. 48 MAX. UNIT 58 21 75 175 50 85 V A W C mJ m
PINNING - SOT404
PIN 1 2 3 tab gate drain source drain DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2 1 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDG VGS ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction temperature CONDITIONS continuous continuous Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 - 55 MAX. 30 30 15 21 15 84 75 175 175 UNIT V V V A A A W C C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to heatsink Thermal resistance junction to ambient CONDITIONS with heatsink compound minimum footprint, FR4 board (see fig. 18) MIN. TYP. 50 MAX. 2 UNIT K/W K/W
February 1996
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Voltage clamped logic level FET
STATIC CHARACTERISTICS
Tj = 25 C unless otherwise specified SYMBOL V(BR)DG VGS(TO) VGS(ON) IDSS IGSS RDS(ON) PARAMETER Drain-gate zener voltage Gate threshold voltage Gate voltage Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS 0.2 < -IG < 0.4 mA; -55C < Tj < 150C VDS = VGS; ID = 1 mA VDS = 10 V; ID = 10 A; -55C < Tj < 150C VDS = 30 V; VGS = 0 V; Tj =150 C VGS = 15 V; VDS = 0 V; Tj =150 C VGS = 5 V; ID = 10 A MIN. 38 1.0 2.0 -
BUK563-48C
TYP. 45 1.5 3.1 0.01 0.1 65
MAX. 54 2.0 4.0 1.0 10 85
UNIT V V V mA A m
DYNAMIC CHARACTERISTICS
Tj = 25 C unless otherwise specified SYMBOL V(CL)DSR gfs Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Drain source clamp voltage (peak value) Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS RG = 10 k; ID = 10 A; -55 < Tj < 150C; Inductive load. VDS = 25 V; ID = 10 A VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. 40 7 TYP. 48 12 550 240 100 3.5 22 16 18 4.5 7.5 MAX. 58 825 350 160 UNIT V S pF pF pF s s s s nH nH
VDD = 12 V; ID = 5 A; VGS = 5 V; RG = 10 k;
Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25 C unless otherwise specified SYMBOL IDR IDRM VSD PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage CONDITIONS IF = 21 A ; VGS = 0 V MIN. TYP. 1.3 MAX. 21 84 1.7 UNIT A A V
February 1996
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Voltage clamped logic level FET
CLAMPED ENERGY LIMITING VALUE
SYMBOL WDSRS PARAMETER Non-repetitive drain-source clamped inductive turn off energy CONDITIONS Tj = 25C prior to clamping; ID = 10 A; VDD < 16 V; VGS = 5 V; RG = 10 k; inductive load MIN. -
BUK563-48C
MAX. 200
UNIT mJ
WDSRR
Drain-source repetitive clamped Tj = 150C prior to clamping; inductive turn off energy ID = 10 A; VDD < 16 V; VGS = 5 V; RG = 10 k; inductive load
-
50
mJ
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
Normalised Current Derating
0
20
40
60
80 100 Tmb / C
120
140
160
180
0
20
40
60
80 100 Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Fig.3. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
ID / A 100
S( O = N) VD ID
BUK553-48C
1E+01
Zth j-mb / (K/W)
ZTHX53
S/
tp =
10 us
RD
1E+00
100 us
0.5 0.2 0.1 0.05 0.02
P D tp D= tp T t
10
1 ms
1E-01
DC Self-clamped 1 1
10 ms 100 ms
0 1E-02 1E-07 1E-05 1E-03 t/s
T
10 VDS / V
100
1E-01
1E+01
Fig.2. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
February 1996
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Voltage clamped logic level FET
BUK563-48C
40
ID / A 10
BUK5Y3-48C VGS / V = 5
40
ID / A
BUK5Y3-48C
30
4.5 4
30
20 3.5 10 3 2.5 0 0 2 4 VDS / V 6 8 10
20
10
Tmb / degC = 150 25 -55 0 1 2 3 4 VGS / V 5 6 7
0
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
Fig.8. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V.
gfs / S BUK5Y3-48C
0.5
RDS(ON) / Ohm 2.5 3 3.5 VGS / V = 4
BUK5Y3-48C
20
0.4 4.5 0.3 5
15
10
0.2
5
0.1 10
150 25 -55
Tmb / degC =
0
0
10
20 VDS / V
30
40
0
0
10
20 Id / A
30
40
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
V(CL)DSR / V BUK5Y3-48C
Fig.9. Typical transconductance. gfs = f(ID); conditions: VDS = 25 V
V(CL)DSR / V
150 25 -55
51 50 49 48
58 56 54 52
BUK5Y3-48C
Tmb / degC =
47
50
46 45 44 43 0 2 4 6 ID / A 8 Tmb / degC = 150 25 -55 10 12
48 46 44
1
2
5 RG / kOhm
10
20
Fig.7. Typical clamping voltage V(CL)DSR = f(ID) ; conditions: RG = 10 k
Fig.10. Typical clamping voltgage V(CL)DSR = f(RG) ; conditions: ID = 10 A.
February 1996
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Voltage clamped logic level FET
BUK563-48C
2.0
a
Normalised RDS(ON) = f(Tj)
VGS(TO) / V max.
2
1.5
typ.
1.0
1
min.
0.5
0 -60 -20 20 60 Tj / C 100 140 180
0 -60 -20 20 60 Tj / C 100 140 180
Fig.11. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 10 A; VGS = 5 V
ID / A SUB-THRESHOLD CONDUCTION
Fig.14. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
IS / A Tmb / degC = BUK5Y3-48C
1E-01
40
1E-02
30
1E-03 2% typ 98 %
150 25 -55
20
1E-04
1E-05
10
1E-06 0 0.4 0.8 1.2 VGS / V 1.6 2 2.4
0
0
0.5
VSDS / V
1
1.5
Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
C / pF BUK5Y3-48C
Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
VGS / V VDD / V = 12 6 BUK5Y3-48C 30
2000
7
1000
5
500
Ciss
4 3
200
Coss
2
100 Crss 50 0.01 0.1 1 VDS / V 10 100
1 0
0
5
10 QG / nC
15
20
Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.16. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 10 A; parameter VDS
February 1996
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Voltage clamped logic level FET
BUK563-48C
VDD Load t p : adjust for correct Ic
I,V
V(CL)DSR 5V ID VDS VGS
D.U.T. RG
VGE
Id measure
t
P,E
PDS = ID x VDS E = PDS dt WDSR
0V
0R1
t
Fig.17. Inductive clamping test circuit.
Fig.18. Typical Inductive Clamping waveforms
February 1996
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Voltage clamped logic level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 1.4 g
10.3 max 4.5 max 1.4 max
BUK563-48C
11 max 15.4
2.5 0.85 max (x2) 2.54 (x2)
0.5
Fig.19. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5 2.0
3.8
5.08
Fig.20. SOT404 : soldering pattern for surface mounting.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8".
February 1996
7
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor Voltage clamped logic level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BUK563-48C
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
February 1996
8
Rev 1.000

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