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PRODUCT SPECIFICATION
PE4140
Product Description
The PE4140 is an ultra-high linearity, passive broadband Quad MOSFET array with high dynamic range performance capable of operation beyond 6.0 GHz. This quad array operates with differential signals at all ports (RF, LO, IF), allowing mixers to be built that use LO powers from -7 dBm to +20 dBm. Typical applications range from frequency up/down-conversion to phase detection for Cellular/PCS Base Stations, Wireless Broadband Communications and STB/Cable modems. The PE4140 is manufactured in Peregrine's patented Ultra Thin Silicon (UTSi) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram
Ultra-High Linearity Broadband Quad MOSFET Array
Features * Ultimate Quad MOSFET array * Ultra-high linearity, broadband performance beyond 6.0 GHz * Ideal for mixer applications * Up/down conversion * Low conversion loss * High LO Isolation * Packaged in small 3x3mm MLPM
Figure 2. Package Type
1
6 6-lead MLPM
3 x 3 mm
LO
IF
2 3
5 4
RF
Table 1. AC and DC Electrical Specifications @ +25 C
Symbol
FTYP VDS VDS Match VT R DS
Characteristics
Operating Frequency Range Drain-Source Voltage Drain-Source Voltage Match Threshold Voltage Drain-Source `ON' Resistance
1
Min
DC 260
Typ
6.0 320 12 -100
Max
380 40 9.5
Units
GHz mV mV mV
Test Conditions
VGS = +3V, IDS = 40 mA VDS = 0.1V; per ASTM F617-00 VGS = +3V, IDS = 40 mA
6.5
7.75
Note 1: Typical untested operating frequency range of Quad MOSFET transistors.
PEREGRINE SEMICONDUCTOR CORP. |
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Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 8
PE4140
Product Specification
Figure 3. Pin Configuration
Electrostatic Discharge (ESD) Precautions This MOSFET device has minimally protected inputs and is highly susceptible to ESD damage. When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Latch-Up Avoidance
4 LO2
IF1 RF1 RF2
1 2 3
Exposed Solder Pad
(bottom side)
6 5
IF2 LO1
Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. Device Description
Table 2. Pin Descriptions
Pin No.
1 2 3 4 5 6
Pin Name
IF1 RF1 RF2 LO2 LO1 IF2
Description
IF Output Connection (Drain) RF Input Connection (Source) RF Input Connection (Source) LO Input Connection (Gate) LO Input Connection (Gate) IF Output Connection (Drain)
The PE4140 passive broadband Quad MOSFET array is designed for use in up-conversion and down-conversion applications for high performance systems such as cellular infrastructure equipment and STB/CATV systems. The PE4140 is an ideal mixer core for a wide range of mixer products, including module level solutions that incorporate baluns or other single-ended matching structures enabling three-port operation. The performance level of this passive mixer is made possible by the very high linearity afforded by Peregrine's UTSi CMOS process. Marking Packaged devices are marked with part number "4140", date code and lot code.
Table 3. Absolute Maximum Ratings
Symbol
TST TOP VDC + AC
Parameter/Conditions
Storage temperature range Operating temperature range Maximum DC plus peak AC voltage across DrainSource Maximum DC plus peak AC voltage across GateDrain or Gate-Source ESD Sensitive Device
Min
-65 -40
Max
150 85 3.3
Units
C C V
VDC+AC VESD
4.2 250
V V
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0089~03B
| UTSi CMOS RFIC SOLUTIONS
Page 2 of 8
PE4140
Product Specification
Figure 4. Typical Schematic for a PCS Application
J3 LO Input
T1 M/A Com ETC1.6-4-2-3 4 5 3 2 1
R2 1.2 nH
R3 2.7 nH 4 5 PE4140 6 R8 2.7 nH 2 3 4 1 3 2 1
T2 M/A Com ETC1.6-4-2-3 1 5 2 3 4
R16 3 pF
J4 RF Input
R12 1.2 nH
5
T3 TOKO 617DB-1024
J6 IF Out
Table 4. Typical Performance in a PCS Application @ +25 C
Parameter
Frequency Range** LO RF IF Conversion Loss** (Includes balun losses) Isolation** LO-RF LO-IF Input IP3** Input 1 dB Compression**
Minimum
1630 1700
Typical
--70 8.5
Maximum
2130 2200
Units
MHz MHz MHz dB
36 26 32 22
dB dB dBm dBm
** Data taken on an Evaluation Board narrow-band tuned to cover the PCS band, IF = 73MHz low-side, LO drive = 17dBm.
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Copyright Peregrine Semiconductor Corp. 2003
Page 3 of 8
PE4140
Product Specification
Typical Performance Plots in a PCS Application @ +25 C (LO=17dBm, IF=73MHz Low-side) Figure 5. IIP3 vs. Frequency
40 35 30 IIP3 (dBm) @ 17dBm Lo 25 20 15 10 5 0 1700 5 1700 Conversion Loss (dB) @ 17dBm Lo IF=73Mhz Low-side 9
Figure 6. Conversion Loss vs. Frequency
10
8 Conversion Loss 7
6
1750
1800
1850
1900
1950
2000
2050
2100
1750
1800
1850
1900
1950
2000
2050
2100
Frequency (MHz)
Frequency (MHz)
Figure 7. LO-RF & LO-IF Isolation
0 -5 -10 -15 -20 -25 LO-RF -30 -35 -40 1700 LO-IF
Isolation (dB)
1750
1800
1850
1900
1950
2000
2050
2100
Frequency (MHz)
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0089~03B
| UTSi CMOS RFIC SOLUTIONS
Page 4 of 8
PE4140
Product Specification
Figure 8. Typical Schematic for a CATV Application
(Reference Designators Refer to locations on Evaluation Board: 101/0090~00A) 4.7nH L1 J3 LO Input 1 ETC1.6-4-2-3 4 T1 3 2 5 1 L2 4.7nH 4 5 6 MLP6-3X3 U1 3 2 1 ETC1.6-4-2-3 T2 1 2 RF Input 3 4 5 R16 3.0pF 1
J4
3
2
1 (Cut short between pads)
4
5 T3 ETC1-1-13
1
J6 IF Out
Note: L1 and L2 provide LO port matching for optimum performance. Typical gate capacitance is approximately 2.5 pF.
Table 5. Typical Performance in a CATV Application @ +25 C
Parameter
Frequency Range** LO RF IF Conversion Loss** (Includes balun losses) Isolation** LO-RF LO-IF Input IP3** Input 1 dB Compression**
Minimum
1116 54
Typical
--1062 6.5
Maximum
1926 864
Units
MHz MHz MHz dB
40 28 23 13
dB dB dBm dBm
** Data taken on an Evaluation Board tuned for a broadband CATV application, IF = 1062MHz, RF drive = -5dBm, LO drive = 10dBm.
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Copyright Peregrine Semiconductor Corp. 2003
Page 5 of 8
PE4140
Product Specification
Typical Performance Plots in a CATV Application @ +25 C Figure 9. IIP3 vs. Frequency
30
Figure 10. Conversion Loss vs. Frequency
10
25
20
Conversion Loss (dB) @10dBm LO
0 200 400 600 800 1000
8
IIP3 (dBm) @10dBm LO
6
15
4
10
5
2
0
0 0 200 400 600 800 1000
Frequency (MHz)
Frequency (MHz)
Figure 11. LO-RF & LO-IF Isolation
0
-10
-20 Isolation (dB) LO-IF -30
-40
-50
LO-RF
-60 1000
1200
1400
1600
1800
2000
Frequency (MHz)
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0089~03B
| UTSi CMOS RFIC SOLUTIONS
Page 6 of 8
PE4140
Product Specification
Figure 12. Package Drawing
6-lead MLPM
3.00 C L -A-B4
6 0.125
5
C L
PIN 1 MARK 4 4
3.00
0.10 C 1 0.10 C 2 3 0.125
10+2 -10 0.100 C 0.90 0.10 0.080 C
3
TOP VIEW
DETAIL C 0.025 0.025 0.70 0.05 0.20 0.05 SEATING PLANE -CDETAIL B
0.0250.025
SIDE VIEW
SEE DETAIL B
0.95 EXPOSED PAD
C L
0.35 +0.08 -0.02 0.10 0.05 C 3
0.17 MIN. CAB 0.29 +0.16 -0.09 EXPOSED SLUG/ HEAT SINK 0.24 +0.20 -0.08 0.125 0.17 0.30
1
2
SEE DETAIL A R 0.15 TYP
R0.127 TYP 1.21 0.10 0.605 0.05 THIS FEATURE APPLIES TO BOTH ENDS OF THE PKG. DETAIL A
EXPOSED METALIZED FEATURE EDGE OF PLASTIC BODY
EXPOSED (2X)
6
5
4
3
0.20 MIN.
1.050.05 2.010.10
BOTTOM VIEW
1. DIMENSIONS AND TOLERANCES ARE PER ANSi Y14.5 2. DIMENSIONS ARE IN MILLIMETERS, ANGLES ARE IN DEGREES. 3 4 COPLANARITY APPLIES TO EXPOSED HEAT SLUG AS WELL AS THE TERMINALS. PROFILE TOLERANCE APPLIES TO PLASTIC BODY ONLY.
Table 6. Ordering Information
Order Code
PE4140-01 PE4140-02 PE4140-00
Part Marking
4140 4140 PE4140-EK
Description
PE4140-06MLP3x3-12800F PE4140-06MLP3x3-3000C PE4140-06MLP3x3-EK
Package
6-lead 3x3 MLPM 6-lead 3x3 MLPM Evaluation Kit
Shipping Method
12800 units / Canister 3000 units / T&R 1 / box
PEREGRINE SEMICONDUCTOR CORP. |
http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 7 of 8
PE4140
Product Specification
Sales Offices
United States
Peregrine Semiconductor Corp.
6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 03-3507-5755 Fax: 03-3507-5601
Europe
Peregrine Semiconductor Europe
Batiment Maine 13-15 rue des Quatre Vents F- 92380 Garches Tel 33-1-47-41-91-73 Fax 33-1-47-41-91-73
For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice.
The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents are pending.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice).
Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright (c) 2003 Peregrine Semiconductor Corp. All rights reserved.
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0089~03B
| UTSi CMOS RFIC SOLUTIONS
Page 8 of 8

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